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add write dpc 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-06 14:34:12 +08:00
parent c934727ea8
commit e714a0ba63
1 changed files with 8 additions and 0 deletions
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8
rtl/debug/jtag_dm.v
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@ -108,6 +108,7 @@ module jtag_dm(
localparam SBADDRESS0 = 6'h39; localparam SBADDRESS0 = 6'h39;
localparam SBDATA0 = 6'h3C; localparam SBDATA0 = 6'h3C;
localparam COMMAND = 6'h17; localparam COMMAND = 6'h17;
localparam DPC = 16'h7b1;
localparam OP_SUCC = 2'b00; localparam OP_SUCC = 2'b00;
@ -130,6 +131,7 @@ module jtag_dm(
if (state == STATE_IDLE) begin if (state == STATE_IDLE) begin
dm_mem_we <= 1'b0; dm_mem_we <= 1'b0;
dm_reg_we <= 1'b0; dm_reg_we <= 1'b0;
dm_reset_req <= 1'b0;
if (dtm_req_valid == `DTM_REQ_VALID) begin if (dtm_req_valid == `DTM_REQ_VALID) begin
state <= STATE_EX; state <= STATE_EX;
op <= dtm_req_data[DMI_OP_BITS - 1:0]; op <= dtm_req_data[DMI_OP_BITS - 1:0];
@ -272,6 +274,12 @@ module jtag_dm(
if (data[15:0] == DCSR) begin if (data[15:0] == DCSR) begin
data0 <= dcsr; data0 <= dcsr;
end end
// write
end else begin
// when write dpc, we reset cpu here
if (data[15:0] == DPC) begin
dm_reset_req <= 1'b1;
end
end end
end end
end end