bus: fix bug

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-04-30 08:59:10 +08:00
parent f9412fca3c
commit dfa8bf490e
1 changed files with 24 additions and 12 deletions

View File

@ -96,24 +96,36 @@ module obi_interconnect #(
end end
end end
// master信号赋值 logic [SLAVE_BITS-1:0] slave_sel_int_q[MASTERS];
generate generate
for (m = 0; m < MASTERS; m = m + 1) begin: master_gnt_rdata for (m = 0; m < MASTERS; m = m + 1) begin: master_data_q
assign master_gnt_o[m] = master_sel_or[m]; always_ff @ (posedge clk_i or negedge rst_ni) begin
assign master_rdata_o[m] = slave_rdata_i[slave_sel_int[m]]; if (!rst_ni) begin
slave_sel_int_q[m] <= 'b0;
end else begin
slave_sel_int_q[m] <= slave_sel_int[m];
end
end
end end
endgenerate endgenerate
// master信号赋值 logic [MASTERS-1:0] master_sel_or_q;
generate
for (m = 0; m < MASTERS; m = m + 1) begin: master_rvalid
always_ff @ (posedge clk_i or negedge rst_ni) begin always_ff @ (posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin if (!rst_ni) begin
master_rvalid_o[m] <= 'b0; master_sel_or_q <= 'b0;
end else begin end else begin
master_rvalid_o[m] <= master_sel_or[m]; master_sel_or_q <= master_sel_or;
end end
end end
// master信号赋值
generate
for (m = 0; m < MASTERS; m = m + 1) begin: master_data
assign master_gnt_o[m] = master_sel_or[m];
assign master_rdata_o[m] = slave_rdata_i[slave_sel_int_q[m]];
assign master_rvalid_o[m] = master_sel_or_q[m];
end end
endgenerate endgenerate