From dfa8bf490ea13864dddbd6d207e378888886645c Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Fri, 30 Apr 2021 08:59:10 +0800 Subject: [PATCH] bus: fix bug Signed-off-by: liangkangnan --- rtl/sys_bus/obi_interconnect.sv | 36 ++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/rtl/sys_bus/obi_interconnect.sv b/rtl/sys_bus/obi_interconnect.sv index 9e99096..7768b9a 100644 --- a/rtl/sys_bus/obi_interconnect.sv +++ b/rtl/sys_bus/obi_interconnect.sv @@ -96,25 +96,37 @@ module obi_interconnect #( end end - // master信号赋值 - generate - for (m = 0; m < MASTERS; m = m + 1) begin: master_gnt_rdata - assign master_gnt_o[m] = master_sel_or[m]; - assign master_rdata_o[m] = slave_rdata_i[slave_sel_int[m]]; - end - endgenerate + logic [SLAVE_BITS-1:0] slave_sel_int_q[MASTERS]; - // master信号赋值 generate - for (m = 0; m < MASTERS; m = m + 1) begin: master_rvalid - always_ff @(posedge clk_i or negedge rst_ni) begin + for (m = 0; m < MASTERS; m = m + 1) begin: master_data_q + always_ff @ (posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - master_rvalid_o[m] <= 'b0; + slave_sel_int_q[m] <= 'b0; end else begin - master_rvalid_o[m] <= master_sel_or[m]; + slave_sel_int_q[m] <= slave_sel_int[m]; end end end endgenerate + logic [MASTERS-1:0] master_sel_or_q; + + always_ff @ (posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + master_sel_or_q <= 'b0; + end else begin + master_sel_or_q <= master_sel_or; + end + end + + // master信号赋值 + generate + for (m = 0; m < MASTERS; m = m + 1) begin: master_data + assign master_gnt_o[m] = master_sel_or[m]; + assign master_rdata_o[m] = slave_rdata_i[slave_sel_int_q[m]]; + assign master_rvalid_o[m] = master_sel_or_q[m]; + end + endgenerate + endmodule