zcy
/
tinyriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add code comments 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-18 20:14:37 +08:00
parent 73098bdcd8
commit dcac95dfab
13 changed files with 312 additions and 270 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
rtl/core/clint.v
View File

@ -24,26 +24,28 @@ module clint(
input wire clk, input wire clk,
input wire rst, input wire rst,
// from core
input wire[`INT_BUS] int_flag_i, // 中断输入信号
// from id // from id
input wire[`INT_BUS] int_flag_i, input wire[`InstBus] inst_i, // 指令内容
input wire[`InstBus] inst_i, input wire[`InstAddrBus] inst_addr_i, // 指令地址
input wire[`InstAddrBus] inst_addr_i,
// from ctrl // from ctrl
input wire[`Hold_Flag_Bus] hold_flag_i, input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
// from csr_reg // from csr_reg
input wire[`RegBus] data_i, input wire[`RegBus] data_i, // CSR寄存器输入数据
// to csr_reg // to csr_reg
output reg we_o, output reg we_o, // 写CSR寄存器标志
output reg[`MemAddrBus] waddr_o, output reg[`MemAddrBus] waddr_o, // 写CSR寄存器地址
output reg[`MemAddrBus] raddr_o, output reg[`MemAddrBus] raddr_o, // 读CSR寄存器地址
output reg[`RegBus] data_o, output reg[`RegBus] data_o, // 写CSR寄存器数据
// to ex // to ex
output reg[`InstAddrBus] int_addr_o, output reg[`InstAddrBus] int_addr_o, // 被中断的指令地址
output reg int_assert_o output reg int_assert_o // 中断标志
); );

13
rtl/core/csr_reg.v
View File

@ -16,23 +16,28 @@
`include "defines.v" `include "defines.v"
// csr reg module // CSR寄存器模块
module csr_reg( module csr_reg(
input wire clk, input wire clk,
input wire rst, input wire rst,
// form ex
input wire we_i, input wire we_i,
input wire[`MemAddrBus] raddr_i, input wire[`MemAddrBus] raddr_i,
input wire[`MemAddrBus] waddr_i, input wire[`MemAddrBus] waddr_i,
input wire[`RegBus] data_i, input wire[`RegBus] data_i,
// from clint
input wire clint_we_i, input wire clint_we_i,
input wire[`MemAddrBus] clint_raddr_i, input wire[`MemAddrBus] clint_raddr_i,
input wire[`MemAddrBus] clint_waddr_i, input wire[`MemAddrBus] clint_waddr_i,
input wire[`RegBus] clint_data_i, input wire[`RegBus] clint_data_i,
// to clint
output reg[`RegBus] clint_data_o, output reg[`RegBus] clint_data_o,
// to ex
output reg[`RegBus] data_o output reg[`RegBus] data_o
); );
@ -45,6 +50,7 @@ module csr_reg(
// cycle counter // cycle counter
// 复位撤销后就一直计数
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
cycle <= {`ZeroWord, `ZeroWord}; cycle <= {`ZeroWord, `ZeroWord};
@ -54,12 +60,14 @@ module csr_reg(
end end
// write reg // write reg
// 写寄存器操作
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
mtvec <= `ZeroWord; mtvec <= `ZeroWord;
mcause <= `ZeroWord; mcause <= `ZeroWord;
mepc <= `ZeroWord; mepc <= `ZeroWord;
end else begin end else begin
// 优先响应ex模块的写操作
if (we_i == `WriteEnable) begin if (we_i == `WriteEnable) begin
case (waddr_i[11:0]) case (waddr_i[11:0])
`CSR_MTVEC: begin `CSR_MTVEC: begin
@ -75,6 +83,7 @@ module csr_reg(
end end
endcase endcase
// clint模块写操作
end else if (clint_we_i == `WriteEnable) begin end else if (clint_we_i == `WriteEnable) begin
case (clint_waddr_i[11:0]) case (clint_waddr_i[11:0])
`CSR_MTVEC: begin `CSR_MTVEC: begin
@ -95,6 +104,7 @@ module csr_reg(
end end
// read reg // read reg
// ex模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o <= `ZeroWord; data_o <= `ZeroWord;
@ -123,6 +133,7 @@ module csr_reg(
end end
// read reg // read reg
// clint模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
clint_data_o <= `ZeroWord; clint_data_o <= `ZeroWord;

14
rtl/core/ctrl.v
View File

@ -16,17 +16,26 @@
`include "defines.v" `include "defines.v"
// 控制模块
// 发出跳转、暂停流水线信号
module ctrl( module ctrl(
input wire rst, input wire rst,
// from ex
input wire jump_flag_i, input wire jump_flag_i,
input wire[`InstAddrBus] jump_addr_i, input wire[`InstAddrBus] jump_addr_i,
input wire hold_flag_ex_i, input wire hold_flag_ex_i,
// from rib
input wire hold_flag_rib_i, input wire hold_flag_rib_i,
// from jtag
input wire jtag_halt_flag_i, input wire jtag_halt_flag_i,
output reg[`Hold_Flag_Bus] hold_flag_o, output reg[`Hold_Flag_Bus] hold_flag_o,
// to pc_reg
output reg jump_flag_o, output reg jump_flag_o,
output reg[`InstAddrBus] jump_addr_o output reg[`InstAddrBus] jump_addr_o
@ -41,12 +50,17 @@ module ctrl(
end else begin end else begin
jump_addr_o <= jump_addr_i; jump_addr_o <= jump_addr_i;
jump_flag_o <= jump_flag_i; jump_flag_o <= jump_flag_i;
// 默认不暂停
hold_flag_o <= `Hold_None; hold_flag_o <= `Hold_None;
// 按优先级处理不同模块的请求
if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o <= `Hold_Id; hold_flag_o <= `Hold_Id;
end else if (hold_flag_rib_i == `HoldEnable) begin end else if (hold_flag_rib_i == `HoldEnable) begin
// 暂停PC，即取指地址不变
hold_flag_o <= `Hold_Pc; hold_flag_o <= `Hold_Pc;
end else if (jtag_halt_flag_i == `HoldEnable) begin end else if (jtag_halt_flag_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o <= `Hold_Id; hold_flag_o <= `Hold_Id;
end else begin end else begin
hold_flag_o <= `Hold_None; hold_flag_o <= `Hold_None;

34
rtl/core/div.v
View File

@ -16,26 +16,31 @@
`include "defines.v" `include "defines.v"
// 除法模块
// 试商法实现32位整数除法
// 每次除法运算至少需要32个时钟周期才能完成
module div( module div(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire[`RegBus] dividend_i, // from ex
input wire[`RegBus] divisor_i, input wire[`RegBus] dividend_i, // 被除数
input wire start_i, input wire[`RegBus] divisor_i, // 除数
input wire[2:0] op_i, input wire start_i, // 开始信号，运算期间这个信号需要一直保持有效
input wire[`RegAddrBus] reg_waddr_i, input wire[2:0] op_i, // 具体是哪一条指令
input wire[`RegAddrBus] reg_waddr_i, // 运算结束后需要写的寄存器
output reg[`DoubleRegBus] result_o, // to ex
output reg ready_o, output reg[`DoubleRegBus] result_o, // 除法结果，高32位是余数，低32位是商
output wire busy_o, output reg ready_o, // 运算结束信号
output reg[2:0] op_o, output wire busy_o, // 正在运算信号
output reg[`RegAddrBus] reg_waddr_o output reg[2:0] op_o, // 具体是哪一条指令
output reg[`RegAddrBus] reg_waddr_o // 运算结束后需要写的寄存器
); );
// 状态定义
localparam STATE_IDLE = 0; localparam STATE_IDLE = 0;
localparam STATE_START = 1; localparam STATE_START = 1;
localparam STATE_INVERT = 2; localparam STATE_INVERT = 2;
@ -55,6 +60,7 @@ module div(
assign busy_o = (state != STATE_IDLE)? `True : `False; assign busy_o = (state != STATE_IDLE)? `True : `False;
// 状态机实现
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
state <= STATE_IDLE; state <= STATE_IDLE;
@ -75,16 +81,20 @@ module div(
op_o <= op_i; op_o <= op_i;
reg_waddr_o <= reg_waddr_i; reg_waddr_o <= reg_waddr_i;
// 除数为0
if (divisor_i == `ZeroWord) begin if (divisor_i == `ZeroWord) begin
ready_o <= `DivResultReady; ready_o <= `DivResultReady;
result_o <= {dividend_i, divisor_zero_result}; result_o <= {dividend_i, divisor_zero_result};
// 除数不为0
end else begin end else begin
count <= 7'd31; count <= 7'd31;
state <= STATE_START; state <= STATE_START;
div_result <= `ZeroWord; div_result <= `ZeroWord;
div_remain <= `ZeroWord; div_remain <= `ZeroWord;
// DIV和REM这两条指令是有符号数运算
if ((op_i == `INST_DIV) || (op_i == `INST_REM)) begin if ((op_i == `INST_DIV) || (op_i == `INST_REM)) begin
// 被除数求补码
if (dividend_i[31] == 1'b1) begin if (dividend_i[31] == 1'b1) begin
dividend_temp <= ~dividend_i + 1; dividend_temp <= ~dividend_i + 1;
minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1; minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1;
@ -92,6 +102,7 @@ module div(
dividend_temp <= dividend_i; dividend_temp <= dividend_i;
minuend <= (dividend_i >> 7'd31) & 1'b1; minuend <= (dividend_i >> 7'd31) & 1'b1;
end end
// 除数求补码
if (divisor_i[31] == 1'b1) begin if (divisor_i[31] == 1'b1) begin
divisor_temp <= ~divisor_i + 1; divisor_temp <= ~divisor_i + 1;
end else begin end else begin
@ -103,6 +114,7 @@ module div(
divisor_temp <= divisor_i; divisor_temp <= divisor_i;
end end
// 运算结束后是否要对结果取补码
if (((op_i == `INST_DIV) && (dividend_i[31] ^ divisor_i[31] == 1'b1)) if (((op_i == `INST_DIV) && (dividend_i[31] ^ divisor_i[31] == 1'b1))
|| ((op_i == `INST_REM) && (dividend_i[31] == 1'b1))) begin || ((op_i == `INST_REM) && (dividend_i[31] == 1'b1))) begin
invert_result <= 1'b1; invert_result <= 1'b1;

130
rtl/core/ex.v
View File

@ -16,62 +16,63 @@
`include "defines.v" `include "defines.v"
// execute and writeback module // 执行模块
// 纯组合逻辑电路
module ex( module ex(
input wire rst, input wire rst,
// from id // from id
input wire[`InstBus] inst_i, // inst content input wire[`InstBus] inst_i, // 指令内容
input wire[`InstAddrBus] inst_addr_i, // inst addr input wire[`InstAddrBus] inst_addr_i, // 指令地址
input wire reg_we_i, input wire reg_we_i, // 是否写通用寄存器
input wire[`RegAddrBus] reg_waddr_i, input wire[`RegAddrBus] reg_waddr_i, // 写通用寄存器地址
input wire[`RegBus] reg1_rdata_i, // reg1 read data input wire[`RegBus] reg1_rdata_i, // 通用寄存器1输入数据
input wire[`RegBus] reg2_rdata_i, // reg2 read data input wire[`RegBus] reg2_rdata_i, // 通用寄存器2输入数据
input wire csr_we_i, input wire csr_we_i, // 是否写CSR寄存器
input wire[`MemAddrBus] csr_waddr_i, input wire[`MemAddrBus] csr_waddr_i, // 写CSR寄存器地址
input wire[`RegBus] csr_rdata_i, input wire[`RegBus] csr_rdata_i, // CSR寄存器输入数据
input wire int_assert_i, input wire int_assert_i, // 中断发生标志
input wire[`InstAddrBus] int_addr_i, input wire[`InstAddrBus] int_addr_i, // 中断跳转地址
// from mem // from mem
input wire[`MemBus] mem_rdata_i, // mem read data input wire[`MemBus] mem_rdata_i, // 内存输入数据
// from div // from div
input wire div_ready_i, input wire div_ready_i, // 除法运算完成标志
input wire[`DoubleRegBus] div_result_i, input wire[`DoubleRegBus] div_result_i, // 除法运算结果
input wire div_busy_i, input wire div_busy_i, // 除法运算忙标志
input wire[2:0] div_op_i, input wire[2:0] div_op_i, // 具体是哪一条除法指令
input wire[`RegAddrBus] div_reg_waddr_i, input wire[`RegAddrBus] div_reg_waddr_i,// 除法运算结束后要写的寄存器地址
// to mem // to mem
output reg[`MemBus] mem_wdata_o, // mem write data output reg[`MemBus] mem_wdata_o, // 写内存数据
output reg[`MemAddrBus] mem_raddr_o, // mem read addr output reg[`MemAddrBus] mem_raddr_o, // 读内存地址
output reg[`MemAddrBus] mem_waddr_o, // mem write addr output reg[`MemAddrBus] mem_waddr_o, // 写内存地址
output wire mem_we_o, // mem write enable output wire mem_we_o, // 是否要写内存
output wire mem_req_o, output wire mem_req_o, // 请求访问内存标志
// to regs // to regs
output wire[`RegBus] reg_wdata_o, // reg write data output wire[`RegBus] reg_wdata_o, // 写寄存器数据
output wire reg_we_o, // reg write enable output wire reg_we_o, // 是否要写通用寄存器
output wire[`RegAddrBus] reg_waddr_o, // reg write addr output wire[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
// to csr reg // to csr reg
output reg[`RegBus] csr_wdata_o, // reg write data output reg[`RegBus] csr_wdata_o, // 写CSR寄存器数据
output wire csr_we_o, // reg write enable output wire csr_we_o, // 是否要写CSR寄存器
output wire[`MemAddrBus] csr_waddr_o, output wire[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址
// to div // to div
output reg div_start_o, output reg div_start_o, // 开始除法运算标志
output reg[`RegBus] div_dividend_o, output reg[`RegBus] div_dividend_o, // 被除数
output reg[`RegBus] div_divisor_o, output reg[`RegBus] div_divisor_o, // 除数
output reg[2:0] div_op_o, output reg[2:0] div_op_o, // 具体是哪一条除法指令
output reg[`RegAddrBus] div_reg_waddr_o, output reg[`RegAddrBus] div_reg_waddr_o,// 除法运算结束后要写的寄存器地址
// to ctrl // to ctrl
output wire hold_flag_o, output wire hold_flag_o, // 是否暂停标志
output wire jump_flag_o, // whether jump or not flag output wire jump_flag_o, // 是否跳转标志
output wire[`InstAddrBus] jump_addr_o // jump dest addr output wire[`InstAddrBus] jump_addr_o // 跳转目的地址
); );
@ -119,22 +120,26 @@ module ex(
assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11; assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
assign reg_wdata_o = reg_wdata | div_wdata; assign reg_wdata_o = reg_wdata | div_wdata;
// 响应中断时不写通用寄存器
assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we); assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we);
assign reg_waddr_o = reg_waddr | div_waddr; assign reg_waddr_o = reg_waddr | div_waddr;
// 响应中断时不写内存
assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we; assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we;
// 响应中断时不向总线请求访问内存
assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req; assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req;
assign hold_flag_o = hold_flag || div_hold_flag; assign hold_flag_o = hold_flag || div_hold_flag;
assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable); assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable);
assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr); assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr);
// 响应中断时不写CSR寄存器
assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i; assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i;
assign csr_waddr_o = csr_waddr_i; assign csr_waddr_o = csr_waddr_i;
// handle mul // 处理除法指令
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
mul_op1 <= `ZeroWord; mul_op1 <= `ZeroWord;
@ -170,7 +175,7 @@ module ex(
end end
end end
// handle div // 处理乘法指令
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
div_dividend_o <= `ZeroWord; div_dividend_o <= `ZeroWord;
@ -287,7 +292,7 @@ module ex(
mem_req <= `RIB_NREQ; mem_req <= `RIB_NREQ;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
reg_we <= `WriteDisable; reg_we <= `WriteDisable;
reg_waddr <= `ZeroWord; reg_waddr <= `ZeroReg;
csr_wdata_o <= `ZeroWord; csr_wdata_o <= `ZeroWord;
end else begin end else begin
reg_we <= reg_we_i; reg_we <= reg_we_i;
@ -613,47 +618,7 @@ module ex(
end else begin end else begin
reg_wdata <= mul_temp[63:32]; reg_wdata <= mul_temp[63:32];
end end
end/*
`INST_DIV: begin
jump_flag <= `JumpDisable;
hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord;
end end
`INST_DIVU: begin
jump_flag <= `JumpDisable;
hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord;
end
`INST_REM: begin
jump_flag <= `JumpDisable;
hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord;
end
`INST_REMU: begin
jump_flag <= `JumpDisable;
hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord;
end*/
default: begin default: begin
jump_flag <= `JumpDisable; jump_flag <= `JumpDisable;
hold_flag <= `HoldDisable; hold_flag <= `HoldDisable;
@ -685,7 +650,6 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]};
@ -704,7 +668,6 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]};
@ -719,7 +682,6 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
reg_wdata <= mem_rdata_i; reg_wdata <= mem_rdata_i;
end end
@ -730,7 +692,6 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {24'h0, mem_rdata_i[7:0]}; reg_wdata <= {24'h0, mem_rdata_i[7:0]};
@ -749,7 +710,6 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {16'h0, mem_rdata_i[15:0]}; reg_wdata <= {16'h0, mem_rdata_i[15:0]};

42
rtl/core/id.v
View File

@ -16,44 +16,45 @@
`include "defines.v" `include "defines.v"
// identification module // 译码模块
// 纯组合逻辑电路
module id( module id(
input wire rst, input wire rst,
// from if_id // from if_id
input wire[`InstBus] inst_i, // inst content input wire[`InstBus] inst_i, // 指令内容
input wire[`InstAddrBus] inst_addr_i, // inst addr input wire[`InstAddrBus] inst_addr_i, // 指令地址
// from regs // from regs
input wire[`RegBus] reg1_rdata_i, // reg1 read data input wire[`RegBus] reg1_rdata_i, // 通用寄存器1输入数据
input wire[`RegBus] reg2_rdata_i, // reg2 read data input wire[`RegBus] reg2_rdata_i, // 通用寄存器2输入数据
// from csr reg // from csr reg
input wire[`RegBus] csr_rdata_i, input wire[`RegBus] csr_rdata_i, // CSR寄存器输入数据
// from ex // from ex
input wire ex_jump_flag_i, input wire ex_jump_flag_i, // 跳转标志
// to regs // to regs
output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr output reg[`RegAddrBus] reg1_raddr_o, // 读通用寄存器1地址
output reg[`RegAddrBus] reg2_raddr_o, // reg2 read addr output reg[`RegAddrBus] reg2_raddr_o, // 读通用寄存器2地址
// to csr reg // to csr reg
output reg[`MemAddrBus] csr_raddr_o, output reg[`MemAddrBus] csr_raddr_o, // 读CSR寄存器地址
output wire mem_req_o, output wire mem_req_o, // 向总线请求访问内存标志
// to ex // to ex
output reg[`InstBus] inst_o, output reg[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o, output reg[`InstAddrBus] inst_addr_o, // 指令地址
output reg[`RegBus] reg1_rdata_o, // reg1 read data output reg[`RegBus] reg1_rdata_o, // 通用寄存器1数据
output reg[`RegBus] reg2_rdata_o, // reg2 read data output reg[`RegBus] reg2_rdata_o, // 通用寄存器2数据
output reg reg_we_o, // reg write enable output reg reg_we_o, // 写通用寄存器标志
output reg[`RegAddrBus] reg_waddr_o, // reg write addr output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
output reg csr_we_o, output reg csr_we_o, // 写CSR寄存器标志
output reg[`RegBus] csr_rdata_o, output reg[`RegBus] csr_rdata_o, // CSR寄存器数据
output reg[`MemAddrBus] csr_waddr_o output reg[`MemAddrBus] csr_waddr_o // 写CSR寄存器地址
); );
@ -66,6 +67,7 @@ module id(
reg mem_req; reg mem_req;
// 跳转时不向总线请求访问内存
assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable)); assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable));

41
rtl/core/id_ex.v
View File

@ -16,33 +16,33 @@
`include "defines.v" `include "defines.v"
// identification to execute module // 将译码结果向执行模块传递
module id_ex( module id_ex(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire[`InstBus] inst_i, // inst content input wire[`InstBus] inst_i, // 指令内容
input wire[`InstAddrBus] inst_addr_i, // inst addr input wire[`InstAddrBus] inst_addr_i, // 指令地址
input wire reg_we_i, input wire reg_we_i, // 写通用寄存器标志
input wire[`RegAddrBus] reg_waddr_i, input wire[`RegAddrBus] reg_waddr_i, // 写通用寄存器地址
input wire[`RegBus] reg1_rdata_i, // reg1 read data input wire[`RegBus] reg1_rdata_i, // 通用寄存器1读数据
input wire[`RegBus] reg2_rdata_i, // reg2 read data input wire[`RegBus] reg2_rdata_i, // 通用寄存器2读数据
input wire csr_we_i, input wire csr_we_i, // 写CSR寄存器标志
input wire[`MemAddrBus] csr_waddr_i, input wire[`MemAddrBus] csr_waddr_i, // 写CSR寄存器地址
input wire[`RegBus] csr_rdata_i, input wire[`RegBus] csr_rdata_i, // CSR寄存器读数据
input wire[`Hold_Flag_Bus] hold_flag_i, input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
output reg[`InstBus] inst_o, // inst content output reg[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o, // inst addr output reg[`InstAddrBus] inst_addr_o, // 指令地址
output reg reg_we_o, output reg reg_we_o, // 写通用寄存器标志
output reg[`RegAddrBus] reg_waddr_o, output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
output reg[`RegBus] reg1_rdata_o, // reg1 read data output reg[`RegBus] reg1_rdata_o, // 通用寄存器1读数据
output reg[`RegBus] reg2_rdata_o, // reg2 read data output reg[`RegBus] reg2_rdata_o, // 通用寄存器2读数据
output reg csr_we_o, output reg csr_we_o, // 写CSR寄存器标志
output reg[`MemAddrBus] csr_waddr_o, output reg[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址
output reg[`RegBus] csr_rdata_o output reg[`RegBus] csr_rdata_o // CSR寄存器读数据
); );
@ -58,6 +58,7 @@ module id_ex(
csr_waddr_o <= `ZeroWord; csr_waddr_o <= `ZeroWord;
csr_rdata_o <= `ZeroWord; csr_rdata_o <= `ZeroWord;
end else begin end else begin
// 流水线暂停时传递默认值
if (hold_flag_i >= `Hold_Id) begin if (hold_flag_i >= `Hold_Id) begin
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= inst_addr_i; inst_addr_o <= inst_addr_i;

13
rtl/core/if_id.v
View File

@ -16,19 +16,19 @@
`include "defines.v" `include "defines.v"
// inst fetch module // 将指令向译码模块传递
module if_id( module if_id(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire[`InstBus] inst_i, // inst content input wire[`InstBus] inst_i, // 指令内容
input wire[`InstAddrBus] inst_addr_i, // inst addr input wire[`InstAddrBus] inst_addr_i, // 指令地址
input wire[`Hold_Flag_Bus] hold_flag_i, input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
output reg[`InstBus] inst_o, output reg[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o output reg[`InstAddrBus] inst_addr_o // 指令地址
); );
@ -36,6 +36,7 @@ module if_id(
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord; inst_addr_o <= `ZeroWord;
// 流水线暂停时传递默认值
end else if (hold_flag_i >= `Hold_If) begin end else if (hold_flag_i >= `Hold_If) begin
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= inst_addr_i; inst_addr_o <= inst_addr_i;

16
rtl/core/pc_reg.v
View File

@ -16,29 +16,33 @@
`include "defines.v" `include "defines.v"
// pc reg module // PC寄存器模块
module pc_reg( module pc_reg(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire jump_flag_i, input wire jump_flag_i, // 跳转标志
input wire[`InstAddrBus] jump_addr_i, input wire[`InstAddrBus] jump_addr_i, // 跳转地址
input wire[`Hold_Flag_Bus] hold_flag_i, input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
input wire jtag_reset_flag_i, input wire jtag_reset_flag_i, // 复位标志
output reg[`InstAddrBus] pc_o output reg[`InstAddrBus] pc_o // PC指针
); );
always @ (posedge clk) begin always @ (posedge clk) begin
// 复位
if (rst == `RstEnable || jtag_reset_flag_i == 1'b1) begin if (rst == `RstEnable || jtag_reset_flag_i == 1'b1) begin
pc_o <= `CpuResetAddr; pc_o <= `CpuResetAddr;
// 跳转
end else if (jump_flag_i == `JumpEnable) begin end else if (jump_flag_i == `JumpEnable) begin
pc_o <= jump_addr_i; pc_o <= jump_addr_i;
// 暂停
end else if (hold_flag_i >= `Hold_Pc) begin end else if (hold_flag_i >= `Hold_Pc) begin
pc_o <= pc_o; pc_o <= pc_o;
// 地址加4
end else begin end else begin
pc_o <= pc_o + 4'h4; pc_o <= pc_o + 4'h4;
end end

44
rtl/core/regs.v
View File

@ -16,35 +16,45 @@
`include "defines.v" `include "defines.v"
// common reg module // 通用寄存器模块
module regs( module regs(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire we_i, // reg write enable // from ex
input wire[`RegAddrBus] waddr_i, // reg write addr input wire we_i, // 写寄存器标志
input wire[`RegBus] wdata_i, // reg write data input wire[`RegAddrBus] waddr_i, // 写寄存器地址
input wire[`RegBus] wdata_i, // 写寄存器数据
input wire jtag_we_i, // reg write enable // from jtag
input wire[`RegAddrBus] jtag_addr_i, // reg write addr input wire jtag_we_i, // 写寄存器标志
input wire[`RegBus] jtag_data_i, // reg write data input wire[`RegAddrBus] jtag_addr_i, // 读、写寄存器地址
input wire[`RegBus] jtag_data_i, // 写寄存器数据
input wire[`RegAddrBus] raddr1_i, // reg1 read addr // from id
output reg[`RegBus] rdata1_o, // reg1 read data input wire[`RegAddrBus] raddr1_i, // 读寄存器1地址
input wire[`RegAddrBus] raddr2_i, // reg2 read addr // to id
output reg[`RegBus] rdata2_o, // reg2 read data output reg[`RegBus] rdata1_o, // 读寄存器1数据
output reg[`RegBus] jtag_data_o // from id
input wire[`RegAddrBus] raddr2_i, // 读寄存器2地址
// to id
output reg[`RegBus] rdata2_o, // 读寄存器2数据
// to jtag
output reg[`RegBus] jtag_data_o // 读寄存器数据
); );
reg[`RegBus] regs[0:`RegNum - 1]; reg[`RegBus] regs[0:`RegNum - 1];
// write reg // 写寄存器
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstDisable) begin if (rst == `RstDisable) begin
// 优先ex模块写操作
if ((we_i == `WriteEnable) && (waddr_i != `RegNumLog2'h0)) begin if ((we_i == `WriteEnable) && (waddr_i != `RegNumLog2'h0)) begin
regs[waddr_i] <= wdata_i; regs[waddr_i] <= wdata_i;
end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `RegNumLog2'h0)) begin end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `RegNumLog2'h0)) begin
@ -53,12 +63,13 @@ module regs(
end end
end end
// read reg1 // 读寄存器1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
rdata1_o <= `ZeroWord; rdata1_o <= `ZeroWord;
end else if (raddr1_i == `RegNumLog2'h0) begin end else if (raddr1_i == `RegNumLog2'h0) begin
rdata1_o <= `ZeroWord; rdata1_o <= `ZeroWord;
// 如果读地址等于写地址，并且正在写操作，则直接返回写数据
end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin
rdata1_o <= wdata_i; rdata1_o <= wdata_i;
end else begin end else begin
@ -66,12 +77,13 @@ module regs(
end end
end end
// read reg2 // 读寄存器2
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
rdata2_o <= `ZeroWord; rdata2_o <= `ZeroWord;
end else if (raddr2_i == `RegNumLog2'h0) begin end else if (raddr2_i == `RegNumLog2'h0) begin
rdata2_o <= `ZeroWord; rdata2_o <= `ZeroWord;
// 如果读地址等于写地址，并且正在写操作，则直接返回写数据
end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin
rdata2_o <= wdata_i; rdata2_o <= wdata_i;
end else begin end else begin
@ -79,7 +91,7 @@ module regs(
end end
end end
// jtag read reg // jtag读寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
jtag_data_o <= `ZeroWord; jtag_data_o <= `ZeroWord;

111
rtl/core/rib.v
View File

@ -17,81 +17,83 @@
`include "defines.v" `include "defines.v"
// RIB总线模块
module rib( module rib(
input wire clk, input wire clk,
input wire rst, input wire rst,
// master 0 interface // master 0 interface
input wire[`MemAddrBus] m0_addr_i, input wire[`MemAddrBus] m0_addr_i, // 主设备0读、写地址
input wire[`MemBus] m0_data_i, input wire[`MemBus] m0_data_i, // 主设备0写数据
output reg[`MemBus] m0_data_o, output reg[`MemBus] m0_data_o, // 主设备0读取到的数据
output reg m0_ack_o, output reg m0_ack_o, // 主设备0访问完成标志
input wire m0_req_i, input wire m0_req_i, // 主设备0访问请求标志
input wire m0_we_i, input wire m0_we_i, // 主设备0写标志
// master 1 interface // master 1 interface
input wire[`MemAddrBus] m1_addr_i, input wire[`MemAddrBus] m1_addr_i, // 主设备1读、写地址
input wire[`MemBus] m1_data_i, input wire[`MemBus] m1_data_i, // 主设备1写数据
output reg[`MemBus] m1_data_o, output reg[`MemBus] m1_data_o, // 主设备1读取到的数据
output reg m1_ack_o, output reg m1_ack_o, // 主设备1访问完成标志
input wire m1_req_i, input wire m1_req_i, // 主设备1访问请求标志
input wire m1_we_i, input wire m1_we_i, // 主设备1写标志
// master 2 interface // master 2 interface
input wire[`MemAddrBus] m2_addr_i, input wire[`MemAddrBus] m2_addr_i, // 主设备2读、写地址
input wire[`MemBus] m2_data_i, input wire[`MemBus] m2_data_i, // 主设备2写数据
output reg[`MemBus] m2_data_o, output reg[`MemBus] m2_data_o, // 主设备2读取到的数据
output reg m2_ack_o, output reg m2_ack_o, // 主设备2访问完成标志
input wire m2_req_i, input wire m2_req_i, // 主设备2访问请求标志
input wire m2_we_i, input wire m2_we_i, // 主设备2写标志
// slave 0 interface // slave 0 interface
output reg[`MemAddrBus] s0_addr_o, output reg[`MemAddrBus] s0_addr_o, // 从设备0读、写地址
output reg[`MemBus] s0_data_o, output reg[`MemBus] s0_data_o, // 从设备0写数据
input wire[`MemBus] s0_data_i, input wire[`MemBus] s0_data_i, // 从设备0读取到的数据
input wire s0_ack_i, input wire s0_ack_i, // 从设备0访问完成标志
output reg s0_req_o, output reg s0_req_o, // 从设备0访问请求标志
output reg s0_we_o, output reg s0_we_o, // 从设备0写标志
// slave 1 interface // slave 1 interface
output reg[`MemAddrBus] s1_addr_o, output reg[`MemAddrBus] s1_addr_o, // 从设备1读、写地址
output reg[`MemBus] s1_data_o, output reg[`MemBus] s1_data_o, // 从设备1写数据
input wire[`MemBus] s1_data_i, input wire[`MemBus] s1_data_i, // 从设备1读取到的数据
input wire s1_ack_i, input wire s1_ack_i, // 从设备1访问完成标志
output reg s1_req_o, output reg s1_req_o, // 从设备1访问请求标志
output reg s1_we_o, output reg s1_we_o, // 从设备1写标志
// slave 2 interface // slave 2 interface
output reg[`MemAddrBus] s2_addr_o, output reg[`MemAddrBus] s2_addr_o, // 从设备2读、写地址
output reg[`MemBus] s2_data_o, output reg[`MemBus] s2_data_o, // 从设备2写数据
input wire[`MemBus] s2_data_i, input wire[`MemBus] s2_data_i, // 从设备2读取到的数据
input wire s2_ack_i, input wire s2_ack_i, // 从设备2访问完成标志
output reg s2_req_o, output reg s2_req_o, // 从设备2访问请求标志
output reg s2_we_o, output reg s2_we_o, // 从设备2写标志
// slave 3 interface // slave 3 interface
output reg[`MemAddrBus] s3_addr_o, output reg[`MemAddrBus] s3_addr_o, // 从设备3读、写地址
output reg[`MemBus] s3_data_o, output reg[`MemBus] s3_data_o, // 从设备3写数据
input wire[`MemBus] s3_data_i, input wire[`MemBus] s3_data_i, // 从设备3读取到的数据
input wire s3_ack_i, input wire s3_ack_i, // 从设备3访问完成标志
output reg s3_req_o, output reg s3_req_o, // 从设备3访问请求标志
output reg s3_we_o, output reg s3_we_o, // 从设备3写标志
// slave 4 interface // slave 4 interface
output reg[`MemAddrBus] s4_addr_o, output reg[`MemAddrBus] s4_addr_o, // 从设备4读、写地址
output reg[`MemBus] s4_data_o, output reg[`MemBus] s4_data_o, // 从设备4写数据
input wire[`MemBus] s4_data_i, input wire[`MemBus] s4_data_i, // 从设备4读取到的数据
input wire s4_ack_i, input wire s4_ack_i, // 从设备4访问完成标志
output reg s4_req_o, output reg s4_req_o, // 从设备4访问请求标志
output reg s4_we_o, output reg s4_we_o, // 从设备4写标志
output reg hold_flag_o output reg hold_flag_o // 暂停流水线标志
); );
// 访问地址的最高4位决定要访问的是哪一个从设备
// 因此最高支持16个从设备
parameter [3:0]slave_0 = 4'b0000; parameter [3:0]slave_0 = 4'b0000;
parameter [3:0]slave_1 = 4'b0001; parameter [3:0]slave_1 = 4'b0001;
parameter [3:0]slave_2 = 4'b0010; parameter [3:0]slave_2 = 4'b0010;
@ -108,10 +110,11 @@ module rib(
reg[1:0] next_grant; reg[1:0] next_grant;
// 主设备请求信号
assign req = {m2_req_i, m1_req_i, m0_req_i}; assign req = {m2_req_i, m1_req_i, m0_req_i};
// 授权主设备切换
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
grant <= grant1; grant <= grant1;
@ -120,7 +123,9 @@ module rib(
end end
end end
// arb // 仲裁逻辑
// 固定优先级仲裁机制
// 优先级由高到低：主设备0，主设备2，主设备1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
next_grant <= grant1; next_grant <= grant1;
@ -171,7 +176,7 @@ module rib(
end end
end end
// 根据授权结果，选择(访问)对应的从设备
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
m0_ack_o <= `RIB_NACK; m0_ack_o <= `RIB_NACK;

62
rtl/core/tinyriscv.v
View File

@ -16,42 +16,42 @@
`include "defines.v" `include "defines.v"
// CPU core top module // tinyriscv处理器核顶层模块
module tinyriscv( module tinyriscv(
input wire clk, input wire clk,
input wire rst, input wire rst,
output wire[`MemAddrBus] rib_ex_addr_o, output wire[`MemAddrBus] rib_ex_addr_o, // 读、写外设的地址
input wire[`MemBus] rib_ex_data_i, input wire[`MemBus] rib_ex_data_i, // 从外设读取的数据
output wire[`MemBus] rib_ex_data_o, output wire[`MemBus] rib_ex_data_o, // 写入外设的数据
output wire rib_ex_req_o, output wire rib_ex_req_o, // 访问外设请求
output wire rib_ex_we_o, output wire rib_ex_we_o, // 写外设标志
output wire[`MemAddrBus] rib_pc_addr_o, output wire[`MemAddrBus] rib_pc_addr_o, // 取指地址
input wire[`MemBus] rib_pc_data_i, input wire[`MemBus] rib_pc_data_i, // 取到的指令内容
input wire[`RegAddrBus] jtag_reg_addr_i, input wire[`RegAddrBus] jtag_reg_addr_i, // jtag模块读、写寄存器的地址
input wire[`RegBus] jtag_reg_data_i, input wire[`RegBus] jtag_reg_data_i, // jtag模块写寄存器数据
input wire jtag_reg_we_i, input wire jtag_reg_we_i, // jtag模块写寄存器标志
output wire[`RegBus] jtag_reg_data_o, output wire[`RegBus] jtag_reg_data_o, // jtag模块读取到的寄存器数据
input wire rib_hold_flag_i, input wire rib_hold_flag_i, // 总线暂停标志
input wire jtag_halt_flag_i, input wire jtag_halt_flag_i, // jtag暂停标志
input wire jtag_reset_flag_i, input wire jtag_reset_flag_i, // jtag复位PC标志
input wire[`INT_BUS] int_i input wire[`INT_BUS] int_i // 中断信号
); );
// pc_reg // pc_reg模块输出信号
wire[`InstAddrBus] pc_pc_o; wire[`InstAddrBus] pc_pc_o;
// if_id // if_id模块输出信号
wire[`InstBus] if_inst_o; wire[`InstBus] if_inst_o;
wire[`InstAddrBus] if_inst_addr_o; wire[`InstAddrBus] if_inst_addr_o;
// id // id模块输出信号
wire[`RegAddrBus] id_reg1_raddr_o; wire[`RegAddrBus] id_reg1_raddr_o;
wire[`RegAddrBus] id_reg2_raddr_o; wire[`RegAddrBus] id_reg2_raddr_o;
wire id_mem_req_o; wire id_mem_req_o;
@ -66,7 +66,7 @@ module tinyriscv(
wire[`RegBus] id_csr_rdata_o; wire[`RegBus] id_csr_rdata_o;
wire[`MemAddrBus] id_csr_waddr_o; wire[`MemAddrBus] id_csr_waddr_o;
// id_ex // id_ex模块输出信号
wire[`InstBus] ie_inst_o; wire[`InstBus] ie_inst_o;
wire[`InstAddrBus] ie_inst_addr_o; wire[`InstAddrBus] ie_inst_addr_o;
wire ie_reg_we_o; wire ie_reg_we_o;
@ -77,7 +77,7 @@ module tinyriscv(
wire[`MemAddrBus] ie_csr_waddr_o; wire[`MemAddrBus] ie_csr_waddr_o;
wire[`RegBus] ie_csr_rdata_o; wire[`RegBus] ie_csr_rdata_o;
// ex // ex模块输出信号
wire[`MemBus] ex_mem_wdata_o; wire[`MemBus] ex_mem_wdata_o;
wire[`MemAddrBus] ex_mem_raddr_o; wire[`MemAddrBus] ex_mem_raddr_o;
wire[`MemAddrBus] ex_mem_waddr_o; wire[`MemAddrBus] ex_mem_waddr_o;
@ -98,27 +98,27 @@ module tinyriscv(
wire ex_csr_we_o; wire ex_csr_we_o;
wire[`MemAddrBus] ex_csr_waddr_o; wire[`MemAddrBus] ex_csr_waddr_o;
// regs // regs模块输出信号
wire[`RegBus] regs_rdata1_o; wire[`RegBus] regs_rdata1_o;
wire[`RegBus] regs_rdata2_o; wire[`RegBus] regs_rdata2_o;
// csr reg // csr_reg模块输出信号
wire[`RegBus] csr_data_o; wire[`RegBus] csr_data_o;
wire[`RegBus] csr_clint_data_o; wire[`RegBus] csr_clint_data_o;
// ctrl // ctrl模块输出信号
wire[`Hold_Flag_Bus] ctrl_hold_flag_o; wire[`Hold_Flag_Bus] ctrl_hold_flag_o;
wire ctrl_jump_flag_o; wire ctrl_jump_flag_o;
wire[`InstAddrBus] ctrl_jump_addr_o; wire[`InstAddrBus] ctrl_jump_addr_o;
// div // div模块输出信号
wire[`DoubleRegBus] div_result_o; wire[`DoubleRegBus] div_result_o;
wire div_ready_o; wire div_ready_o;
wire div_busy_o; wire div_busy_o;
wire[2:0] div_op_o; wire[2:0] div_op_o;
wire[`RegAddrBus] div_reg_waddr_o; wire[`RegAddrBus] div_reg_waddr_o;
// clint // clint模块输出信号
wire clint_we_o; wire clint_we_o;
wire[`MemAddrBus] clint_waddr_o; wire[`MemAddrBus] clint_waddr_o;
wire[`MemAddrBus] clint_raddr_o; wire[`MemAddrBus] clint_raddr_o;
@ -135,6 +135,7 @@ module tinyriscv(
assign rib_pc_addr_o = pc_pc_o; assign rib_pc_addr_o = pc_pc_o;
// pc_reg模块例化
pc_reg u_pc_reg( pc_reg u_pc_reg(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -145,6 +146,7 @@ module tinyriscv(
.jump_addr_i(ctrl_jump_addr_o) .jump_addr_i(ctrl_jump_addr_o)
); );
// ctrl模块例化
ctrl u_ctrl( ctrl u_ctrl(
.rst(rst), .rst(rst),
.jump_flag_i(ex_jump_flag_o), .jump_flag_i(ex_jump_flag_o),
@ -157,6 +159,7 @@ module tinyriscv(
.jtag_halt_flag_i(jtag_halt_flag_i) .jtag_halt_flag_i(jtag_halt_flag_i)
); );
// regs模块例化
regs u_regs( regs u_regs(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -173,6 +176,7 @@ module tinyriscv(
.jtag_data_o(jtag_reg_data_o) .jtag_data_o(jtag_reg_data_o)
); );
// csr_reg模块例化
csr_reg u_csr_reg( csr_reg u_csr_reg(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -188,6 +192,7 @@ module tinyriscv(
.clint_data_o(csr_clint_data_o) .clint_data_o(csr_clint_data_o)
); );
// if_id模块例化
if_id u_if_id( if_id u_if_id(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -198,6 +203,7 @@ module tinyriscv(
.inst_addr_o(if_inst_addr_o) .inst_addr_o(if_inst_addr_o)
); );
// id模块例化
id u_id( id u_id(
.rst(rst), .rst(rst),
.inst_i(if_inst_o), .inst_i(if_inst_o),
@ -221,6 +227,7 @@ module tinyriscv(
.csr_waddr_o(id_csr_waddr_o) .csr_waddr_o(id_csr_waddr_o)
); );
// id_ex模块例化
id_ex u_id_ex( id_ex u_id_ex(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -245,6 +252,7 @@ module tinyriscv(
.csr_rdata_o(ie_csr_rdata_o) .csr_rdata_o(ie_csr_rdata_o)
); );
// ex模块例化
ex u_ex( ex u_ex(
.rst(rst), .rst(rst),
.inst_i(ie_inst_o), .inst_i(ie_inst_o),
@ -285,6 +293,7 @@ module tinyriscv(
.csr_waddr_o(ex_csr_waddr_o) .csr_waddr_o(ex_csr_waddr_o)
); );
// div模块例化
div u_div( div u_div(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -300,6 +309,7 @@ module tinyriscv(
.reg_waddr_o(div_reg_waddr_o) .reg_waddr_o(div_reg_waddr_o)
); );
// clint模块例化
clint u_clint( clint u_clint(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),

36
rtl/soc/tinyriscv_soc_top.v
View File

@ -16,24 +16,24 @@
`include "defines.v" `include "defines.v"
// tinyriscv soc顶层模块
module tinyriscv_soc_top( module tinyriscv_soc_top(
input wire clk, input wire clk,
input wire rst, input wire rst,
output reg over, output reg over, // 测试是否完成信号
output reg succ, output reg succ, // 测试是否成功信号
output wire halted_ind, output wire halted_ind, // jtag是否已经halt住CPU信号
output wire tx_pin, output wire tx_pin, // UART发送引脚
output wire io_pin, output wire io_pin, // GPIO引脚
input wire jtag_TCK, input wire jtag_TCK, // JTAG TCK引脚
input wire jtag_TMS, input wire jtag_TMS, // JTAG TMS引脚
input wire jtag_TDI, input wire jtag_TDI, // JTAG TDI引脚
output wire jtag_TDO output wire jtag_TDO // JTAG TDO引脚
); );
@ -124,6 +124,8 @@ module tinyriscv_soc_top(
assign int_flag = {7'h0, timer0_int}; assign int_flag = {7'h0, timer0_int};
// 低电平点亮LED
// 低电平表示已经halt住CPU
assign halted_ind = ~jtag_halt_req_o; assign halted_ind = ~jtag_halt_req_o;
@ -133,11 +135,11 @@ module tinyriscv_soc_top(
succ <= 1'b1; succ <= 1'b1;
end else begin end else begin
over <= ~u_tinyriscv.u_regs.regs[26]; // when = 1, run over over <= ~u_tinyriscv.u_regs.regs[26]; // when = 1, run over
succ <= ~u_tinyriscv.u_regs.regs[27]; // when = 1, succ succ <= ~u_tinyriscv.u_regs.regs[27]; // when = 1, run succ, otherwise fail
end end
end end
// tinyriscv处理器核模块例化
tinyriscv u_tinyriscv( tinyriscv u_tinyriscv(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -162,6 +164,7 @@ module tinyriscv_soc_top(
.int_i(int_flag) .int_i(int_flag)
); );
// rom模块例化
rom u_rom( rom u_rom(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -173,6 +176,7 @@ module tinyriscv_soc_top(
.ack_o(s0_ack_i) .ack_o(s0_ack_i)
); );
// ram模块例化
ram u_ram( ram u_ram(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -184,6 +188,7 @@ module tinyriscv_soc_top(
.ack_o(s1_ack_i) .ack_o(s1_ack_i)
); );
// timer模块例化
timer timer_0( timer timer_0(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -196,6 +201,7 @@ module tinyriscv_soc_top(
.ack_o(s2_ack_i) .ack_o(s2_ack_i)
); );
// uart_tx模块例化
uart_tx uart_tx_0( uart_tx uart_tx_0(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -208,6 +214,7 @@ module tinyriscv_soc_top(
.tx_pin(tx_pin) .tx_pin(tx_pin)
); );
// gpio模块例化
gpio gpio_0( gpio gpio_0(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -220,6 +227,7 @@ module tinyriscv_soc_top(
.io_pin(io_pin) .io_pin(io_pin)
); );
// rib模块例化
rib u_rib( rib u_rib(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
@ -291,8 +299,7 @@ module tinyriscv_soc_top(
.hold_flag_o(rib_hold_flag_o) .hold_flag_o(rib_hold_flag_o)
); );
// jtag模块复位逻辑
// jtag module reset logic
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
jtag_rst <= 1'b1; jtag_rst <= 1'b1;
@ -307,6 +314,7 @@ module tinyriscv_soc_top(
end end
end end
// jtag模块例化
jtag_top u_jtag_top( jtag_top u_jtag_top(
.jtag_rst_n(jtag_rst), .jtag_rst_n(jtag_rst),
.jtag_pin_TCK(jtag_TCK), .jtag_pin_TCK(jtag_TCK),