From dcac95dfab9e2ced7d7c6bb1a48805df20be6208 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Sat, 18 Apr 2020 20:14:37 +0800 Subject: [PATCH] add code comments Signed-off-by: liangkangnan --- rtl/core/clint.v | 24 ++++--- rtl/core/csr_reg.v | 13 +++- rtl/core/ctrl.v | 14 ++++ rtl/core/div.v | 34 +++++++--- rtl/core/ex.v | 130 +++++++++++++----------------------- rtl/core/id.v | 42 ++++++------ rtl/core/id_ex.v | 43 ++++++------ rtl/core/if_id.v | 13 ++-- rtl/core/pc_reg.v | 16 +++-- rtl/core/regs.v | 44 +++++++----- rtl/core/rib.v | 111 +++++++++++++++--------------- rtl/core/tinyriscv.v | 62 +++++++++-------- rtl/soc/tinyriscv_soc_top.v | 36 ++++++---- 13 files changed, 312 insertions(+), 270 deletions(-) diff --git a/rtl/core/clint.v b/rtl/core/clint.v index c085e14..242d8cb 100644 --- a/rtl/core/clint.v +++ b/rtl/core/clint.v @@ -24,26 +24,28 @@ module clint( input wire clk, input wire rst, + // from core + input wire[`INT_BUS] int_flag_i, // 中断输入信号 + // from id - input wire[`INT_BUS] int_flag_i, - input wire[`InstBus] inst_i, - input wire[`InstAddrBus] inst_addr_i, + input wire[`InstBus] inst_i, // 指令内容 + input wire[`InstAddrBus] inst_addr_i, // 指令地址 // from ctrl - input wire[`Hold_Flag_Bus] hold_flag_i, + input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志 // from csr_reg - input wire[`RegBus] data_i, + input wire[`RegBus] data_i, // CSR寄存器输入数据 // to csr_reg - output reg we_o, - output reg[`MemAddrBus] waddr_o, - output reg[`MemAddrBus] raddr_o, - output reg[`RegBus] data_o, + output reg we_o, // 写CSR寄存器标志 + output reg[`MemAddrBus] waddr_o, // 写CSR寄存器地址 + output reg[`MemAddrBus] raddr_o, // 读CSR寄存器地址 + output reg[`RegBus] data_o, // 写CSR寄存器数据 // to ex - output reg[`InstAddrBus] int_addr_o, - output reg int_assert_o + output reg[`InstAddrBus] int_addr_o, // 被中断的指令地址 + output reg int_assert_o // 中断标志 ); diff --git a/rtl/core/csr_reg.v b/rtl/core/csr_reg.v index 9943db0..54fdef1 100644 --- a/rtl/core/csr_reg.v +++ b/rtl/core/csr_reg.v @@ -16,23 +16,28 @@ `include "defines.v" -// csr reg module +// CSR瀵勫瓨鍣ㄦā鍧 module csr_reg( input wire clk, input wire rst, + // form ex input wire we_i, input wire[`MemAddrBus] raddr_i, input wire[`MemAddrBus] waddr_i, input wire[`RegBus] data_i, + // from clint input wire clint_we_i, input wire[`MemAddrBus] clint_raddr_i, input wire[`MemAddrBus] clint_waddr_i, input wire[`RegBus] clint_data_i, + // to clint output reg[`RegBus] clint_data_o, + + // to ex output reg[`RegBus] data_o ); @@ -45,6 +50,7 @@ module csr_reg( // cycle counter + // 澶嶄綅鎾ら攢鍚庡氨涓鐩磋鏁 always @ (posedge clk) begin if (rst == `RstEnable) begin cycle <= {`ZeroWord, `ZeroWord}; @@ -54,12 +60,14 @@ module csr_reg( end // write reg + // 鍐欏瘎瀛樺櫒鎿嶄綔 always @ (posedge clk) begin if (rst == `RstEnable) begin mtvec <= `ZeroWord; mcause <= `ZeroWord; mepc <= `ZeroWord; end else begin + // 浼樺厛鍝嶅簲ex妯″潡鐨勫啓鎿嶄綔 if (we_i == `WriteEnable) begin case (waddr_i[11:0]) `CSR_MTVEC: begin @@ -75,6 +83,7 @@ module csr_reg( end endcase + // clint妯″潡鍐欐搷浣 end else if (clint_we_i == `WriteEnable) begin case (clint_waddr_i[11:0]) `CSR_MTVEC: begin @@ -95,6 +104,7 @@ module csr_reg( end // read reg + // ex妯″潡璇籆SR瀵勫瓨鍣 always @ (*) begin if (rst == `RstEnable) begin data_o <= `ZeroWord; @@ -123,6 +133,7 @@ module csr_reg( end // read reg + // clint妯″潡璇籆SR瀵勫瓨鍣 always @ (*) begin if (rst == `RstEnable) begin clint_data_o <= `ZeroWord; diff --git a/rtl/core/ctrl.v b/rtl/core/ctrl.v index 725cf97..6e719b2 100644 --- a/rtl/core/ctrl.v +++ b/rtl/core/ctrl.v @@ -16,17 +16,26 @@ `include "defines.v" +// 鎺у埗妯″潡 +// 鍙戝嚭璺宠浆銆佹殏鍋滄祦姘寸嚎淇″彿 module ctrl( input wire rst, + // from ex input wire jump_flag_i, input wire[`InstAddrBus] jump_addr_i, input wire hold_flag_ex_i, + + // from rib input wire hold_flag_rib_i, + + // from jtag input wire jtag_halt_flag_i, output reg[`Hold_Flag_Bus] hold_flag_o, + + // to pc_reg output reg jump_flag_o, output reg[`InstAddrBus] jump_addr_o @@ -41,12 +50,17 @@ module ctrl( end else begin jump_addr_o <= jump_addr_i; jump_flag_o <= jump_flag_i; + // 榛樿涓嶆殏鍋 hold_flag_o <= `Hold_None; + // 鎸変紭鍏堢骇澶勭悊涓嶅悓妯″潡鐨勮姹 if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin + // 鏆傚仠鏁存潯娴佹按绾 hold_flag_o <= `Hold_Id; end else if (hold_flag_rib_i == `HoldEnable) begin + // 鏆傚仠PC锛屽嵆鍙栨寚鍦板潃涓嶅彉 hold_flag_o <= `Hold_Pc; end else if (jtag_halt_flag_i == `HoldEnable) begin + // 鏆傚仠鏁存潯娴佹按绾 hold_flag_o <= `Hold_Id; end else begin hold_flag_o <= `Hold_None; diff --git a/rtl/core/div.v b/rtl/core/div.v index 6e7596c..b68b627 100644 --- a/rtl/core/div.v +++ b/rtl/core/div.v @@ -16,26 +16,31 @@ `include "defines.v" - +// 闄ゆ硶妯″潡 +// 璇曞晢娉曞疄鐜32浣嶆暣鏁伴櫎娉 +// 姣忔闄ゆ硶杩愮畻鑷冲皯闇瑕32涓椂閽熷懆鏈熸墠鑳藉畬鎴 module div( input wire clk, input wire rst, - input wire[`RegBus] dividend_i, - input wire[`RegBus] divisor_i, - input wire start_i, - input wire[2:0] op_i, - input wire[`RegAddrBus] reg_waddr_i, + // from ex + input wire[`RegBus] dividend_i, // 琚櫎鏁 + input wire[`RegBus] divisor_i, // 闄ゆ暟 + input wire start_i, // 寮濮嬩俊鍙凤紝杩愮畻鏈熼棿杩欎釜淇″彿闇瑕佷竴鐩翠繚鎸佹湁鏁 + input wire[2:0] op_i, // 鍏蜂綋鏄摢涓鏉℃寚浠 + input wire[`RegAddrBus] reg_waddr_i, // 杩愮畻缁撴潫鍚庨渶瑕佸啓鐨勫瘎瀛樺櫒 - output reg[`DoubleRegBus] result_o, - output reg ready_o, - output wire busy_o, - output reg[2:0] op_o, - output reg[`RegAddrBus] reg_waddr_o + // to ex + output reg[`DoubleRegBus] result_o, // 闄ゆ硶缁撴灉锛岄珮32浣嶆槸浣欐暟锛屼綆32浣嶆槸鍟 + output reg ready_o, // 杩愮畻缁撴潫淇″彿 + output wire busy_o, // 姝ｅ湪杩愮畻淇″彿 + output reg[2:0] op_o, // 鍏蜂綋鏄摢涓鏉℃寚浠 + output reg[`RegAddrBus] reg_waddr_o // 杩愮畻缁撴潫鍚庨渶瑕佸啓鐨勫瘎瀛樺櫒 ); + // 鐘舵佸畾涔 localparam STATE_IDLE = 0; localparam STATE_START = 1; localparam STATE_INVERT = 2; @@ -55,6 +60,7 @@ module div( assign busy_o = (state != STATE_IDLE)? `True : `False; + // 鐘舵佹満瀹炵幇 always @ (posedge clk) begin if (rst == `RstEnable) begin state <= STATE_IDLE; @@ -75,16 +81,20 @@ module div( op_o <= op_i; reg_waddr_o <= reg_waddr_i; + // 闄ゆ暟涓0 if (divisor_i == `ZeroWord) begin ready_o <= `DivResultReady; result_o <= {dividend_i, divisor_zero_result}; + // 闄ゆ暟涓嶄负0 end else begin count <= 7'd31; state <= STATE_START; div_result <= `ZeroWord; div_remain <= `ZeroWord; + // DIV鍜孯EM杩欎袱鏉℃寚浠ゆ槸鏈夌鍙锋暟杩愮畻 if ((op_i == `INST_DIV) || (op_i == `INST_REM)) begin + // 琚櫎鏁版眰琛ョ爜 if (dividend_i[31] == 1'b1) begin dividend_temp <= ~dividend_i + 1; minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1; @@ -92,6 +102,7 @@ module div( dividend_temp <= dividend_i; minuend <= (dividend_i >> 7'd31) & 1'b1; end + // 闄ゆ暟姹傝ˉ鐮 if (divisor_i[31] == 1'b1) begin divisor_temp <= ~divisor_i + 1; end else begin @@ -103,6 +114,7 @@ module div( divisor_temp <= divisor_i; end + // 杩愮畻缁撴潫鍚庢槸鍚﹁瀵圭粨鏋滃彇琛ョ爜 if (((op_i == `INST_DIV) && (dividend_i[31] ^ divisor_i[31] == 1'b1)) || ((op_i == `INST_REM) && (dividend_i[31] == 1'b1))) begin invert_result <= 1'b1; diff --git a/rtl/core/ex.v b/rtl/core/ex.v index c4c6616..2babcb8 100644 --- a/rtl/core/ex.v +++ b/rtl/core/ex.v @@ -16,62 +16,63 @@ `include "defines.v" -// execute and writeback module +// 鎵ц妯″潡 +// 绾粍鍚堥昏緫鐢佃矾 module ex( input wire rst, // from id - input wire[`InstBus] inst_i, // inst content - input wire[`InstAddrBus] inst_addr_i, // inst addr - input wire reg_we_i, - input wire[`RegAddrBus] reg_waddr_i, - input wire[`RegBus] reg1_rdata_i, // reg1 read data - input wire[`RegBus] reg2_rdata_i, // reg2 read data - input wire csr_we_i, - input wire[`MemAddrBus] csr_waddr_i, - input wire[`RegBus] csr_rdata_i, - input wire int_assert_i, - input wire[`InstAddrBus] int_addr_i, + input wire[`InstBus] inst_i, // 鎸囦护鍐呭 + input wire[`InstAddrBus] inst_addr_i, // 鎸囦护鍦板潃 + input wire reg_we_i, // 鏄惁鍐欓氱敤瀵勫瓨鍣 + input wire[`RegAddrBus] reg_waddr_i, // 鍐欓氱敤瀵勫瓨鍣ㄥ湴鍧 + input wire[`RegBus] reg1_rdata_i, // 閫氱敤瀵勫瓨鍣1杈撳叆鏁版嵁 + input wire[`RegBus] reg2_rdata_i, // 閫氱敤瀵勫瓨鍣2杈撳叆鏁版嵁 + input wire csr_we_i, // 鏄惁鍐機SR瀵勫瓨鍣 + input wire[`MemAddrBus] csr_waddr_i, // 鍐機SR瀵勫瓨鍣ㄥ湴鍧 + input wire[`RegBus] csr_rdata_i, // CSR瀵勫瓨鍣ㄨ緭鍏ユ暟鎹 + input wire int_assert_i, // 涓柇鍙戠敓鏍囧織 + input wire[`InstAddrBus] int_addr_i, // 涓柇璺宠浆鍦板潃 // from mem - input wire[`MemBus] mem_rdata_i, // mem read data + input wire[`MemBus] mem_rdata_i, // 鍐呭瓨杈撳叆鏁版嵁 // from div - input wire div_ready_i, - input wire[`DoubleRegBus] div_result_i, - input wire div_busy_i, - input wire[2:0] div_op_i, - input wire[`RegAddrBus] div_reg_waddr_i, + input wire div_ready_i, // 闄ゆ硶杩愮畻瀹屾垚鏍囧織 + input wire[`DoubleRegBus] div_result_i, // 闄ゆ硶杩愮畻缁撴灉 + input wire div_busy_i, // 闄ゆ硶杩愮畻蹇欐爣蹇 + input wire[2:0] div_op_i, // 鍏蜂綋鏄摢涓鏉￠櫎娉曟寚浠 + input wire[`RegAddrBus] div_reg_waddr_i,// 闄ゆ硶杩愮畻缁撴潫鍚庤鍐欑殑瀵勫瓨鍣ㄥ湴鍧 // to mem - output reg[`MemBus] mem_wdata_o, // mem write data - output reg[`MemAddrBus] mem_raddr_o, // mem read addr - output reg[`MemAddrBus] mem_waddr_o, // mem write addr - output wire mem_we_o, // mem write enable - output wire mem_req_o, + output reg[`MemBus] mem_wdata_o, // 鍐欏唴瀛樻暟鎹 + output reg[`MemAddrBus] mem_raddr_o, // 璇诲唴瀛樺湴鍧 + output reg[`MemAddrBus] mem_waddr_o, // 鍐欏唴瀛樺湴鍧 + output wire mem_we_o, // 鏄惁瑕佸啓鍐呭瓨 + output wire mem_req_o, // 璇锋眰璁块棶鍐呭瓨鏍囧織 // to regs - output wire[`RegBus] reg_wdata_o, // reg write data - output wire reg_we_o, // reg write enable - output wire[`RegAddrBus] reg_waddr_o, // reg write addr + output wire[`RegBus] reg_wdata_o, // 鍐欏瘎瀛樺櫒鏁版嵁 + output wire reg_we_o, // 鏄惁瑕佸啓閫氱敤瀵勫瓨鍣 + output wire[`RegAddrBus] reg_waddr_o, // 鍐欓氱敤瀵勫瓨鍣ㄥ湴鍧 // to csr reg - output reg[`RegBus] csr_wdata_o, // reg write data - output wire csr_we_o, // reg write enable - output wire[`MemAddrBus] csr_waddr_o, + output reg[`RegBus] csr_wdata_o, // 鍐機SR瀵勫瓨鍣ㄦ暟鎹 + output wire csr_we_o, // 鏄惁瑕佸啓CSR瀵勫瓨鍣 + output wire[`MemAddrBus] csr_waddr_o, // 鍐機SR瀵勫瓨鍣ㄥ湴鍧 // to div - output reg div_start_o, - output reg[`RegBus] div_dividend_o, - output reg[`RegBus] div_divisor_o, - output reg[2:0] div_op_o, - output reg[`RegAddrBus] div_reg_waddr_o, + output reg div_start_o, // 寮濮嬮櫎娉曡繍绠楁爣蹇 + output reg[`RegBus] div_dividend_o, // 琚櫎鏁 + output reg[`RegBus] div_divisor_o, // 闄ゆ暟 + output reg[2:0] div_op_o, // 鍏蜂綋鏄摢涓鏉￠櫎娉曟寚浠 + output reg[`RegAddrBus] div_reg_waddr_o,// 闄ゆ硶杩愮畻缁撴潫鍚庤鍐欑殑瀵勫瓨鍣ㄥ湴鍧 // to ctrl - output wire hold_flag_o, - output wire jump_flag_o, // whether jump or not flag - output wire[`InstAddrBus] jump_addr_o // jump dest addr + output wire hold_flag_o, // 鏄惁鏆傚仠鏍囧織 + output wire jump_flag_o, // 鏄惁璺宠浆鏍囧織 + output wire[`InstAddrBus] jump_addr_o // 璺宠浆鐩殑鍦板潃 ); @@ -119,22 +120,26 @@ module ex( assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11; assign reg_wdata_o = reg_wdata | div_wdata; + // 鍝嶅簲涓柇鏃朵笉鍐欓氱敤瀵勫瓨鍣 assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we); assign reg_waddr_o = reg_waddr | div_waddr; + // 鍝嶅簲涓柇鏃朵笉鍐欏唴瀛 assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we; + // 鍝嶅簲涓柇鏃朵笉鍚戞荤嚎璇锋眰璁块棶鍐呭瓨 assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req; assign hold_flag_o = hold_flag || div_hold_flag; assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable); assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr); + // 鍝嶅簲涓柇鏃朵笉鍐機SR瀵勫瓨鍣 assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i; assign csr_waddr_o = csr_waddr_i; - // handle mul + // 澶勭悊闄ゆ硶鎸囦护 always @ (*) begin if (rst == `RstEnable) begin mul_op1 <= `ZeroWord; @@ -170,7 +175,7 @@ module ex( end end - // handle div + // 澶勭悊涔樻硶鎸囦护 always @ (*) begin if (rst == `RstEnable) begin div_dividend_o <= `ZeroWord; @@ -287,7 +292,7 @@ module ex( mem_req <= `RIB_NREQ; reg_wdata <= `ZeroWord; reg_we <= `WriteDisable; - reg_waddr <= `ZeroWord; + reg_waddr <= `ZeroReg; csr_wdata_o <= `ZeroWord; end else begin reg_we <= reg_we_i; @@ -613,47 +618,7 @@ module ex( end else begin reg_wdata <= mul_temp[63:32]; end - end/* - `INST_DIV: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; end - `INST_DIVU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - end - `INST_REM: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - end - `INST_REMU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - end*/ default: begin jump_flag <= `JumpDisable; hold_flag <= `HoldDisable; @@ -685,7 +650,6 @@ module ex( mem_wdata_o <= `ZeroWord; mem_waddr_o <= `ZeroWord; mem_we <= `WriteDisable; - //mem_req <= `RIB_REQ; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; @@ -704,7 +668,6 @@ module ex( mem_wdata_o <= `ZeroWord; mem_waddr_o <= `ZeroWord; mem_we <= `WriteDisable; - //mem_req <= `RIB_REQ; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; @@ -719,7 +682,6 @@ module ex( mem_wdata_o <= `ZeroWord; mem_waddr_o <= `ZeroWord; mem_we <= `WriteDisable; - //mem_req <= `RIB_REQ; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; reg_wdata <= mem_rdata_i; end @@ -730,7 +692,6 @@ module ex( mem_wdata_o <= `ZeroWord; mem_waddr_o <= `ZeroWord; mem_we <= `WriteDisable; - //mem_req <= `RIB_REQ; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin reg_wdata <= {24'h0, mem_rdata_i[7:0]}; @@ -749,7 +710,6 @@ module ex( mem_wdata_o <= `ZeroWord; mem_waddr_o <= `ZeroWord; mem_we <= `WriteDisable; - //mem_req <= `RIB_REQ; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin reg_wdata <= {16'h0, mem_rdata_i[15:0]}; diff --git a/rtl/core/id.v b/rtl/core/id.v index 8eb7461..34876c3 100644 --- a/rtl/core/id.v +++ b/rtl/core/id.v @@ -16,44 +16,45 @@ `include "defines.v" -// identification module +// 璇戠爜妯″潡 +// 绾粍鍚堥昏緫鐢佃矾 module id( input wire rst, // from if_id - input wire[`InstBus] inst_i, // inst content - input wire[`InstAddrBus] inst_addr_i, // inst addr + input wire[`InstBus] inst_i, // 鎸囦护鍐呭 + input wire[`InstAddrBus] inst_addr_i, // 鎸囦护鍦板潃 // from regs - input wire[`RegBus] reg1_rdata_i, // reg1 read data - input wire[`RegBus] reg2_rdata_i, // reg2 read data + input wire[`RegBus] reg1_rdata_i, // 閫氱敤瀵勫瓨鍣1杈撳叆鏁版嵁 + input wire[`RegBus] reg2_rdata_i, // 閫氱敤瀵勫瓨鍣2杈撳叆鏁版嵁 // from csr reg - input wire[`RegBus] csr_rdata_i, + input wire[`RegBus] csr_rdata_i, // CSR瀵勫瓨鍣ㄨ緭鍏ユ暟鎹 // from ex - input wire ex_jump_flag_i, + input wire ex_jump_flag_i, // 璺宠浆鏍囧織 // to regs - output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr - output reg[`RegAddrBus] reg2_raddr_o, // reg2 read addr + output reg[`RegAddrBus] reg1_raddr_o, // 璇婚氱敤瀵勫瓨鍣1鍦板潃 + output reg[`RegAddrBus] reg2_raddr_o, // 璇婚氱敤瀵勫瓨鍣2鍦板潃 // to csr reg - output reg[`MemAddrBus] csr_raddr_o, + output reg[`MemAddrBus] csr_raddr_o, // 璇籆SR瀵勫瓨鍣ㄥ湴鍧 - output wire mem_req_o, + output wire mem_req_o, // 鍚戞荤嚎璇锋眰璁块棶鍐呭瓨鏍囧織 // to ex - output reg[`InstBus] inst_o, - output reg[`InstAddrBus] inst_addr_o, - output reg[`RegBus] reg1_rdata_o, // reg1 read data - output reg[`RegBus] reg2_rdata_o, // reg2 read data - output reg reg_we_o, // reg write enable - output reg[`RegAddrBus] reg_waddr_o, // reg write addr - output reg csr_we_o, - output reg[`RegBus] csr_rdata_o, - output reg[`MemAddrBus] csr_waddr_o + output reg[`InstBus] inst_o, // 鎸囦护鍐呭 + output reg[`InstAddrBus] inst_addr_o, // 鎸囦护鍦板潃 + output reg[`RegBus] reg1_rdata_o, // 閫氱敤瀵勫瓨鍣1鏁版嵁 + output reg[`RegBus] reg2_rdata_o, // 閫氱敤瀵勫瓨鍣2鏁版嵁 + output reg reg_we_o, // 鍐欓氱敤瀵勫瓨鍣ㄦ爣蹇 + output reg[`RegAddrBus] reg_waddr_o, // 鍐欓氱敤瀵勫瓨鍣ㄥ湴鍧 + output reg csr_we_o, // 鍐機SR瀵勫瓨鍣ㄦ爣蹇 + output reg[`RegBus] csr_rdata_o, // CSR瀵勫瓨鍣ㄦ暟鎹 + output reg[`MemAddrBus] csr_waddr_o // 鍐機SR瀵勫瓨鍣ㄥ湴鍧 ); @@ -66,6 +67,7 @@ module id( reg mem_req; + // 璺宠浆鏃朵笉鍚戞荤嚎璇锋眰璁块棶鍐呭瓨 assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable)); diff --git a/rtl/core/id_ex.v b/rtl/core/id_ex.v index 453b88d..50ee00f 100644 --- a/rtl/core/id_ex.v +++ b/rtl/core/id_ex.v @@ -16,33 +16,33 @@ `include "defines.v" -// identification to execute module +// 灏嗚瘧鐮佺粨鏋滃悜鎵ц妯″潡浼犻 module id_ex( input wire clk, - input wire rst, + input wire rst, - input wire[`InstBus] inst_i, // inst content - input wire[`InstAddrBus] inst_addr_i, // inst addr - input wire reg_we_i, - input wire[`RegAddrBus] reg_waddr_i, - input wire[`RegBus] reg1_rdata_i, // reg1 read data - input wire[`RegBus] reg2_rdata_i, // reg2 read data - input wire csr_we_i, - input wire[`MemAddrBus] csr_waddr_i, - input wire[`RegBus] csr_rdata_i, + input wire[`InstBus] inst_i, // 鎸囦护鍐呭 + input wire[`InstAddrBus] inst_addr_i, // 鎸囦护鍦板潃 + input wire reg_we_i, // 鍐欓氱敤瀵勫瓨鍣ㄦ爣蹇 + input wire[`RegAddrBus] reg_waddr_i, // 鍐欓氱敤瀵勫瓨鍣ㄥ湴鍧 + input wire[`RegBus] reg1_rdata_i, // 閫氱敤瀵勫瓨鍣1璇绘暟鎹 + input wire[`RegBus] reg2_rdata_i, // 閫氱敤瀵勫瓨鍣2璇绘暟鎹 + input wire csr_we_i, // 鍐機SR瀵勫瓨鍣ㄦ爣蹇 + input wire[`MemAddrBus] csr_waddr_i, // 鍐機SR瀵勫瓨鍣ㄥ湴鍧 + input wire[`RegBus] csr_rdata_i, // CSR瀵勫瓨鍣ㄨ鏁版嵁 - input wire[`Hold_Flag_Bus] hold_flag_i, + input wire[`Hold_Flag_Bus] hold_flag_i, // 娴佹按绾挎殏鍋滄爣蹇 - output reg[`InstBus] inst_o, // inst content - output reg[`InstAddrBus] inst_addr_o, // inst addr - output reg reg_we_o, - output reg[`RegAddrBus] reg_waddr_o, - output reg[`RegBus] reg1_rdata_o, // reg1 read data - output reg[`RegBus] reg2_rdata_o, // reg2 read data - output reg csr_we_o, - output reg[`MemAddrBus] csr_waddr_o, - output reg[`RegBus] csr_rdata_o + output reg[`InstBus] inst_o, // 鎸囦护鍐呭 + output reg[`InstAddrBus] inst_addr_o, // 鎸囦护鍦板潃 + output reg reg_we_o, // 鍐欓氱敤瀵勫瓨鍣ㄦ爣蹇 + output reg[`RegAddrBus] reg_waddr_o, // 鍐欓氱敤瀵勫瓨鍣ㄥ湴鍧 + output reg[`RegBus] reg1_rdata_o, // 閫氱敤瀵勫瓨鍣1璇绘暟鎹 + output reg[`RegBus] reg2_rdata_o, // 閫氱敤瀵勫瓨鍣2璇绘暟鎹 + output reg csr_we_o, // 鍐機SR瀵勫瓨鍣ㄦ爣蹇 + output reg[`MemAddrBus] csr_waddr_o, // 鍐機SR瀵勫瓨鍣ㄥ湴鍧 + output reg[`RegBus] csr_rdata_o // CSR瀵勫瓨鍣ㄨ鏁版嵁 ); @@ -58,6 +58,7 @@ module id_ex( csr_waddr_o <= `ZeroWord; csr_rdata_o <= `ZeroWord; end else begin + // 娴佹按绾挎殏鍋滄椂浼犻掗粯璁ゅ if (hold_flag_i >= `Hold_Id) begin inst_o <= `INST_NOP; inst_addr_o <= inst_addr_i; diff --git a/rtl/core/if_id.v b/rtl/core/if_id.v index b9cfb85..f23f1c4 100644 --- a/rtl/core/if_id.v +++ b/rtl/core/if_id.v @@ -16,19 +16,19 @@ `include "defines.v" -// inst fetch module +// 灏嗘寚浠ゅ悜璇戠爜妯″潡浼犻 module if_id( input wire clk, input wire rst, - input wire[`InstBus] inst_i, // inst content - input wire[`InstAddrBus] inst_addr_i, // inst addr + input wire[`InstBus] inst_i, // 鎸囦护鍐呭 + input wire[`InstAddrBus] inst_addr_i, // 鎸囦护鍦板潃 - input wire[`Hold_Flag_Bus] hold_flag_i, + input wire[`Hold_Flag_Bus] hold_flag_i, // 娴佹按绾挎殏鍋滄爣蹇 - output reg[`InstBus] inst_o, - output reg[`InstAddrBus] inst_addr_o + output reg[`InstBus] inst_o, // 鎸囦护鍐呭 + output reg[`InstAddrBus] inst_addr_o // 鎸囦护鍦板潃 ); @@ -36,6 +36,7 @@ module if_id( if (rst == `RstEnable) begin inst_o <= `INST_NOP; inst_addr_o <= `ZeroWord; + // 娴佹按绾挎殏鍋滄椂浼犻掗粯璁ゅ end else if (hold_flag_i >= `Hold_If) begin inst_o <= `INST_NOP; inst_addr_o <= inst_addr_i; diff --git a/rtl/core/pc_reg.v b/rtl/core/pc_reg.v index 36821bd..a997805 100644 --- a/rtl/core/pc_reg.v +++ b/rtl/core/pc_reg.v @@ -16,29 +16,33 @@ `include "defines.v" -// pc reg module +// PC瀵勫瓨鍣ㄦā鍧 module pc_reg( input wire clk, input wire rst, - input wire jump_flag_i, - input wire[`InstAddrBus] jump_addr_i, - input wire[`Hold_Flag_Bus] hold_flag_i, - input wire jtag_reset_flag_i, + input wire jump_flag_i, // 璺宠浆鏍囧織 + input wire[`InstAddrBus] jump_addr_i, // 璺宠浆鍦板潃 + input wire[`Hold_Flag_Bus] hold_flag_i, // 娴佹按绾挎殏鍋滄爣蹇 + input wire jtag_reset_flag_i, // 澶嶄綅鏍囧織 - output reg[`InstAddrBus] pc_o + output reg[`InstAddrBus] pc_o // PC鎸囬拡 ); always @ (posedge clk) begin + // 澶嶄綅 if (rst == `RstEnable || jtag_reset_flag_i == 1'b1) begin pc_o <= `CpuResetAddr; + // 璺宠浆 end else if (jump_flag_i == `JumpEnable) begin pc_o <= jump_addr_i; + // 鏆傚仠 end else if (hold_flag_i >= `Hold_Pc) begin pc_o <= pc_o; + // 鍦板潃鍔4 end else begin pc_o <= pc_o + 4'h4; end diff --git a/rtl/core/regs.v b/rtl/core/regs.v index 8a65b0b..5bc0a39 100644 --- a/rtl/core/regs.v +++ b/rtl/core/regs.v @@ -16,35 +16,45 @@ `include "defines.v" -// common reg module +// 閫氱敤瀵勫瓨鍣ㄦā鍧 module regs( input wire clk, input wire rst, - input wire we_i, // reg write enable - input wire[`RegAddrBus] waddr_i, // reg write addr - input wire[`RegBus] wdata_i, // reg write data + // from ex + input wire we_i, // 鍐欏瘎瀛樺櫒鏍囧織 + input wire[`RegAddrBus] waddr_i, // 鍐欏瘎瀛樺櫒鍦板潃 + input wire[`RegBus] wdata_i, // 鍐欏瘎瀛樺櫒鏁版嵁 - input wire jtag_we_i, // reg write enable - input wire[`RegAddrBus] jtag_addr_i, // reg write addr - input wire[`RegBus] jtag_data_i, // reg write data + // from jtag + input wire jtag_we_i, // 鍐欏瘎瀛樺櫒鏍囧織 + input wire[`RegAddrBus] jtag_addr_i, // 璇汇佸啓瀵勫瓨鍣ㄥ湴鍧 + input wire[`RegBus] jtag_data_i, // 鍐欏瘎瀛樺櫒鏁版嵁 - input wire[`RegAddrBus] raddr1_i, // reg1 read addr - output reg[`RegBus] rdata1_o, // reg1 read data + // from id + input wire[`RegAddrBus] raddr1_i, // 璇诲瘎瀛樺櫒1鍦板潃 - input wire[`RegAddrBus] raddr2_i, // reg2 read addr - output reg[`RegBus] rdata2_o, // reg2 read data + // to id + output reg[`RegBus] rdata1_o, // 璇诲瘎瀛樺櫒1鏁版嵁 - output reg[`RegBus] jtag_data_o + // from id + input wire[`RegAddrBus] raddr2_i, // 璇诲瘎瀛樺櫒2鍦板潃 + + // to id + output reg[`RegBus] rdata2_o, // 璇诲瘎瀛樺櫒2鏁版嵁 + + // to jtag + output reg[`RegBus] jtag_data_o // 璇诲瘎瀛樺櫒鏁版嵁 ); reg[`RegBus] regs[0:`RegNum - 1]; - // write reg + // 鍐欏瘎瀛樺櫒 always @ (posedge clk) begin if (rst == `RstDisable) begin + // 浼樺厛ex妯″潡鍐欐搷浣 if ((we_i == `WriteEnable) && (waddr_i != `RegNumLog2'h0)) begin regs[waddr_i] <= wdata_i; end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `RegNumLog2'h0)) begin @@ -53,12 +63,13 @@ module regs( end end - // read reg1 + // 璇诲瘎瀛樺櫒1 always @ (*) begin if (rst == `RstEnable) begin rdata1_o <= `ZeroWord; end else if (raddr1_i == `RegNumLog2'h0) begin rdata1_o <= `ZeroWord; + // 濡傛灉璇诲湴鍧绛変簬鍐欏湴鍧锛屽苟涓旀鍦ㄥ啓鎿嶄綔锛屽垯鐩存帴杩斿洖鍐欐暟鎹 end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin rdata1_o <= wdata_i; end else begin @@ -66,12 +77,13 @@ module regs( end end - // read reg2 + // 璇诲瘎瀛樺櫒2 always @ (*) begin if (rst == `RstEnable) begin rdata2_o <= `ZeroWord; end else if (raddr2_i == `RegNumLog2'h0) begin rdata2_o <= `ZeroWord; + // 濡傛灉璇诲湴鍧绛変簬鍐欏湴鍧锛屽苟涓旀鍦ㄥ啓鎿嶄綔锛屽垯鐩存帴杩斿洖鍐欐暟鎹 end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin rdata2_o <= wdata_i; end else begin @@ -79,7 +91,7 @@ module regs( end end - // jtag read reg + // jtag璇诲瘎瀛樺櫒 always @ (*) begin if (rst == `RstEnable) begin jtag_data_o <= `ZeroWord; diff --git a/rtl/core/rib.v b/rtl/core/rib.v index 27b1d61..9679876 100644 --- a/rtl/core/rib.v +++ b/rtl/core/rib.v @@ -17,81 +17,83 @@ `include "defines.v" - +// RIB鎬荤嚎妯″潡 module rib( input wire clk, input wire rst, // master 0 interface - input wire[`MemAddrBus] m0_addr_i, - input wire[`MemBus] m0_data_i, - output reg[`MemBus] m0_data_o, - output reg m0_ack_o, - input wire m0_req_i, - input wire m0_we_i, + input wire[`MemAddrBus] m0_addr_i, // 涓昏澶0璇汇佸啓鍦板潃 + input wire[`MemBus] m0_data_i, // 涓昏澶0鍐欐暟鎹 + output reg[`MemBus] m0_data_o, // 涓昏澶0璇诲彇鍒扮殑鏁版嵁 + output reg m0_ack_o, // 涓昏澶0璁块棶瀹屾垚鏍囧織 + input wire m0_req_i, // 涓昏澶0璁块棶璇锋眰鏍囧織 + input wire m0_we_i, // 涓昏澶0鍐欐爣蹇 // master 1 interface - input wire[`MemAddrBus] m1_addr_i, - input wire[`MemBus] m1_data_i, - output reg[`MemBus] m1_data_o, - output reg m1_ack_o, - input wire m1_req_i, - input wire m1_we_i, + input wire[`MemAddrBus] m1_addr_i, // 涓昏澶1璇汇佸啓鍦板潃 + input wire[`MemBus] m1_data_i, // 涓昏澶1鍐欐暟鎹 + output reg[`MemBus] m1_data_o, // 涓昏澶1璇诲彇鍒扮殑鏁版嵁 + output reg m1_ack_o, // 涓昏澶1璁块棶瀹屾垚鏍囧織 + input wire m1_req_i, // 涓昏澶1璁块棶璇锋眰鏍囧織 + input wire m1_we_i, // 涓昏澶1鍐欐爣蹇 // master 2 interface - input wire[`MemAddrBus] m2_addr_i, - input wire[`MemBus] m2_data_i, - output reg[`MemBus] m2_data_o, - output reg m2_ack_o, - input wire m2_req_i, - input wire m2_we_i, + input wire[`MemAddrBus] m2_addr_i, // 涓昏澶2璇汇佸啓鍦板潃 + input wire[`MemBus] m2_data_i, // 涓昏澶2鍐欐暟鎹 + output reg[`MemBus] m2_data_o, // 涓昏澶2璇诲彇鍒扮殑鏁版嵁 + output reg m2_ack_o, // 涓昏澶2璁块棶瀹屾垚鏍囧織 + input wire m2_req_i, // 涓昏澶2璁块棶璇锋眰鏍囧織 + input wire m2_we_i, // 涓昏澶2鍐欐爣蹇 // slave 0 interface - output reg[`MemAddrBus] s0_addr_o, - output reg[`MemBus] s0_data_o, - input wire[`MemBus] s0_data_i, - input wire s0_ack_i, - output reg s0_req_o, - output reg s0_we_o, + output reg[`MemAddrBus] s0_addr_o, // 浠庤澶0璇汇佸啓鍦板潃 + output reg[`MemBus] s0_data_o, // 浠庤澶0鍐欐暟鎹 + input wire[`MemBus] s0_data_i, // 浠庤澶0璇诲彇鍒扮殑鏁版嵁 + input wire s0_ack_i, // 浠庤澶0璁块棶瀹屾垚鏍囧織 + output reg s0_req_o, // 浠庤澶0璁块棶璇锋眰鏍囧織 + output reg s0_we_o, // 浠庤澶0鍐欐爣蹇 // slave 1 interface - output reg[`MemAddrBus] s1_addr_o, - output reg[`MemBus] s1_data_o, - input wire[`MemBus] s1_data_i, - input wire s1_ack_i, - output reg s1_req_o, - output reg s1_we_o, + output reg[`MemAddrBus] s1_addr_o, // 浠庤澶1璇汇佸啓鍦板潃 + output reg[`MemBus] s1_data_o, // 浠庤澶1鍐欐暟鎹 + input wire[`MemBus] s1_data_i, // 浠庤澶1璇诲彇鍒扮殑鏁版嵁 + input wire s1_ack_i, // 浠庤澶1璁块棶瀹屾垚鏍囧織 + output reg s1_req_o, // 浠庤澶1璁块棶璇锋眰鏍囧織 + output reg s1_we_o, // 浠庤澶1鍐欐爣蹇 // slave 2 interface - output reg[`MemAddrBus] s2_addr_o, - output reg[`MemBus] s2_data_o, - input wire[`MemBus] s2_data_i, - input wire s2_ack_i, - output reg s2_req_o, - output reg s2_we_o, + output reg[`MemAddrBus] s2_addr_o, // 浠庤澶2璇汇佸啓鍦板潃 + output reg[`MemBus] s2_data_o, // 浠庤澶2鍐欐暟鎹 + input wire[`MemBus] s2_data_i, // 浠庤澶2璇诲彇鍒扮殑鏁版嵁 + input wire s2_ack_i, // 浠庤澶2璁块棶瀹屾垚鏍囧織 + output reg s2_req_o, // 浠庤澶2璁块棶璇锋眰鏍囧織 + output reg s2_we_o, // 浠庤澶2鍐欐爣蹇 // slave 3 interface - output reg[`MemAddrBus] s3_addr_o, - output reg[`MemBus] s3_data_o, - input wire[`MemBus] s3_data_i, - input wire s3_ack_i, - output reg s3_req_o, - output reg s3_we_o, + output reg[`MemAddrBus] s3_addr_o, // 浠庤澶3璇汇佸啓鍦板潃 + output reg[`MemBus] s3_data_o, // 浠庤澶3鍐欐暟鎹 + input wire[`MemBus] s3_data_i, // 浠庤澶3璇诲彇鍒扮殑鏁版嵁 + input wire s3_ack_i, // 浠庤澶3璁块棶瀹屾垚鏍囧織 + output reg s3_req_o, // 浠庤澶3璁块棶璇锋眰鏍囧織 + output reg s3_we_o, // 浠庤澶3鍐欐爣蹇 // slave 4 interface - output reg[`MemAddrBus] s4_addr_o, - output reg[`MemBus] s4_data_o, - input wire[`MemBus] s4_data_i, - input wire s4_ack_i, - output reg s4_req_o, - output reg s4_we_o, + output reg[`MemAddrBus] s4_addr_o, // 浠庤澶4璇汇佸啓鍦板潃 + output reg[`MemBus] s4_data_o, // 浠庤澶4鍐欐暟鎹 + input wire[`MemBus] s4_data_i, // 浠庤澶4璇诲彇鍒扮殑鏁版嵁 + input wire s4_ack_i, // 浠庤澶4璁块棶瀹屾垚鏍囧織 + output reg s4_req_o, // 浠庤澶4璁块棶璇锋眰鏍囧織 + output reg s4_we_o, // 浠庤澶4鍐欐爣蹇 - output reg hold_flag_o + output reg hold_flag_o // 鏆傚仠娴佹按绾挎爣蹇 ); + // 璁块棶鍦板潃鐨勬渶楂4浣嶅喅瀹氳璁块棶鐨勬槸鍝竴涓粠璁惧 + // 鍥犳鏈楂樻敮鎸16涓粠璁惧 parameter [3:0]slave_0 = 4'b0000; parameter [3:0]slave_1 = 4'b0001; parameter [3:0]slave_2 = 4'b0010; @@ -108,10 +110,11 @@ module rib( reg[1:0] next_grant; + // 涓昏澶囪姹備俊鍙 assign req = {m2_req_i, m1_req_i, m0_req_i}; - + // 鎺堟潈涓昏澶囧垏鎹 always @ (posedge clk) begin if (rst == `RstEnable) begin grant <= grant1; @@ -120,7 +123,9 @@ module rib( end end - // arb + // 浠茶閫昏緫 + // 鍥哄畾浼樺厛绾т徊瑁佹満鍒 + // 浼樺厛绾х敱楂樺埌浣庯細涓昏澶0锛屼富璁惧2锛屼富璁惧1 always @ (*) begin if (rst == `RstEnable) begin next_grant <= grant1; @@ -171,7 +176,7 @@ module rib( end end - + // 鏍规嵁鎺堟潈缁撴灉锛岄夋嫨(璁块棶)瀵瑰簲鐨勪粠璁惧 always @ (*) begin if (rst == `RstEnable) begin m0_ack_o <= `RIB_NACK; diff --git a/rtl/core/tinyriscv.v b/rtl/core/tinyriscv.v index ba41c2f..effbfc4 100644 --- a/rtl/core/tinyriscv.v +++ b/rtl/core/tinyriscv.v @@ -16,42 +16,42 @@ `include "defines.v" -// CPU core top module +// tinyriscv澶勭悊鍣ㄦ牳椤跺眰妯″潡 module tinyriscv( input wire clk, input wire rst, - output wire[`MemAddrBus] rib_ex_addr_o, - input wire[`MemBus] rib_ex_data_i, - output wire[`MemBus] rib_ex_data_o, - output wire rib_ex_req_o, - output wire rib_ex_we_o, + output wire[`MemAddrBus] rib_ex_addr_o, // 璇汇佸啓澶栬鐨勫湴鍧 + input wire[`MemBus] rib_ex_data_i, // 浠庡璁捐鍙栫殑鏁版嵁 + output wire[`MemBus] rib_ex_data_o, // 鍐欏叆澶栬鐨勬暟鎹 + output wire rib_ex_req_o, // 璁块棶澶栬璇锋眰 + output wire rib_ex_we_o, // 鍐欏璁炬爣蹇 - output wire[`MemAddrBus] rib_pc_addr_o, - input wire[`MemBus] rib_pc_data_i, + output wire[`MemAddrBus] rib_pc_addr_o, // 鍙栨寚鍦板潃 + input wire[`MemBus] rib_pc_data_i, // 鍙栧埌鐨勬寚浠ゅ唴瀹 - input wire[`RegAddrBus] jtag_reg_addr_i, - input wire[`RegBus] jtag_reg_data_i, - input wire jtag_reg_we_i, - output wire[`RegBus] jtag_reg_data_o, + input wire[`RegAddrBus] jtag_reg_addr_i, // jtag妯″潡璇汇佸啓瀵勫瓨鍣ㄧ殑鍦板潃 + input wire[`RegBus] jtag_reg_data_i, // jtag妯″潡鍐欏瘎瀛樺櫒鏁版嵁 + input wire jtag_reg_we_i, // jtag妯″潡鍐欏瘎瀛樺櫒鏍囧織 + output wire[`RegBus] jtag_reg_data_o, // jtag妯″潡璇诲彇鍒扮殑瀵勫瓨鍣ㄦ暟鎹 - input wire rib_hold_flag_i, - input wire jtag_halt_flag_i, - input wire jtag_reset_flag_i, + input wire rib_hold_flag_i, // 鎬荤嚎鏆傚仠鏍囧織 + input wire jtag_halt_flag_i, // jtag鏆傚仠鏍囧織 + input wire jtag_reset_flag_i, // jtag澶嶄綅PC鏍囧織 - input wire[`INT_BUS] int_i + input wire[`INT_BUS] int_i // 涓柇淇″彿 ); - // pc_reg + // pc_reg妯″潡杈撳嚭淇″彿 wire[`InstAddrBus] pc_pc_o; - // if_id + // if_id妯″潡杈撳嚭淇″彿 wire[`InstBus] if_inst_o; wire[`InstAddrBus] if_inst_addr_o; - // id + // id妯″潡杈撳嚭淇″彿 wire[`RegAddrBus] id_reg1_raddr_o; wire[`RegAddrBus] id_reg2_raddr_o; wire id_mem_req_o; @@ -66,7 +66,7 @@ module tinyriscv( wire[`RegBus] id_csr_rdata_o; wire[`MemAddrBus] id_csr_waddr_o; - // id_ex + // id_ex妯″潡杈撳嚭淇″彿 wire[`InstBus] ie_inst_o; wire[`InstAddrBus] ie_inst_addr_o; wire ie_reg_we_o; @@ -77,7 +77,7 @@ module tinyriscv( wire[`MemAddrBus] ie_csr_waddr_o; wire[`RegBus] ie_csr_rdata_o; - // ex + // ex妯″潡杈撳嚭淇″彿 wire[`MemBus] ex_mem_wdata_o; wire[`MemAddrBus] ex_mem_raddr_o; wire[`MemAddrBus] ex_mem_waddr_o; @@ -98,27 +98,27 @@ module tinyriscv( wire ex_csr_we_o; wire[`MemAddrBus] ex_csr_waddr_o; - // regs + // regs妯″潡杈撳嚭淇″彿 wire[`RegBus] regs_rdata1_o; wire[`RegBus] regs_rdata2_o; - // csr reg + // csr_reg妯″潡杈撳嚭淇″彿 wire[`RegBus] csr_data_o; wire[`RegBus] csr_clint_data_o; - // ctrl + // ctrl妯″潡杈撳嚭淇″彿 wire[`Hold_Flag_Bus] ctrl_hold_flag_o; wire ctrl_jump_flag_o; wire[`InstAddrBus] ctrl_jump_addr_o; - // div + // div妯″潡杈撳嚭淇″彿 wire[`DoubleRegBus] div_result_o; wire div_ready_o; wire div_busy_o; wire[2:0] div_op_o; wire[`RegAddrBus] div_reg_waddr_o; - // clint + // clint妯″潡杈撳嚭淇″彿 wire clint_we_o; wire[`MemAddrBus] clint_waddr_o; wire[`MemAddrBus] clint_raddr_o; @@ -135,6 +135,7 @@ module tinyriscv( assign rib_pc_addr_o = pc_pc_o; + // pc_reg妯″潡渚嬪寲 pc_reg u_pc_reg( .clk(clk), .rst(rst), @@ -145,6 +146,7 @@ module tinyriscv( .jump_addr_i(ctrl_jump_addr_o) ); + // ctrl妯″潡渚嬪寲 ctrl u_ctrl( .rst(rst), .jump_flag_i(ex_jump_flag_o), @@ -157,6 +159,7 @@ module tinyriscv( .jtag_halt_flag_i(jtag_halt_flag_i) ); + // regs妯″潡渚嬪寲 regs u_regs( .clk(clk), .rst(rst), @@ -173,6 +176,7 @@ module tinyriscv( .jtag_data_o(jtag_reg_data_o) ); + // csr_reg妯″潡渚嬪寲 csr_reg u_csr_reg( .clk(clk), .rst(rst), @@ -188,6 +192,7 @@ module tinyriscv( .clint_data_o(csr_clint_data_o) ); + // if_id妯″潡渚嬪寲 if_id u_if_id( .clk(clk), .rst(rst), @@ -198,6 +203,7 @@ module tinyriscv( .inst_addr_o(if_inst_addr_o) ); + // id妯″潡渚嬪寲 id u_id( .rst(rst), .inst_i(if_inst_o), @@ -221,6 +227,7 @@ module tinyriscv( .csr_waddr_o(id_csr_waddr_o) ); + // id_ex妯″潡渚嬪寲 id_ex u_id_ex( .clk(clk), .rst(rst), @@ -245,6 +252,7 @@ module tinyriscv( .csr_rdata_o(ie_csr_rdata_o) ); + // ex妯″潡渚嬪寲 ex u_ex( .rst(rst), .inst_i(ie_inst_o), @@ -285,6 +293,7 @@ module tinyriscv( .csr_waddr_o(ex_csr_waddr_o) ); + // div妯″潡渚嬪寲 div u_div( .clk(clk), .rst(rst), @@ -300,6 +309,7 @@ module tinyriscv( .reg_waddr_o(div_reg_waddr_o) ); + // clint妯″潡渚嬪寲 clint u_clint( .clk(clk), .rst(rst), diff --git a/rtl/soc/tinyriscv_soc_top.v b/rtl/soc/tinyriscv_soc_top.v index 9a638a1..05f16c8 100644 --- a/rtl/soc/tinyriscv_soc_top.v +++ b/rtl/soc/tinyriscv_soc_top.v @@ -16,24 +16,24 @@ `include "defines.v" - +// tinyriscv soc椤跺眰妯″潡 module tinyriscv_soc_top( input wire clk, input wire rst, - output reg over, - output reg succ, + output reg over, // 娴嬭瘯鏄惁瀹屾垚淇″彿 + output reg succ, // 娴嬭瘯鏄惁鎴愬姛淇″彿 - output wire halted_ind, + output wire halted_ind, // jtag鏄惁宸茬粡halt浣廋PU淇″彿 - output wire tx_pin, - output wire io_pin, + output wire tx_pin, // UART鍙戦佸紩鑴 + output wire io_pin, // GPIO寮曡剼 - input wire jtag_TCK, - input wire jtag_TMS, - input wire jtag_TDI, - output wire jtag_TDO + input wire jtag_TCK, // JTAG TCK寮曡剼 + input wire jtag_TMS, // JTAG TMS寮曡剼 + input wire jtag_TDI, // JTAG TDI寮曡剼 + output wire jtag_TDO // JTAG TDO寮曡剼 ); @@ -124,6 +124,8 @@ module tinyriscv_soc_top( assign int_flag = {7'h0, timer0_int}; + // 浣庣數骞崇偣浜甃ED + // 浣庣數骞宠〃绀哄凡缁廻alt浣廋PU assign halted_ind = ~jtag_halt_req_o; @@ -133,11 +135,11 @@ module tinyriscv_soc_top( succ <= 1'b1; end else begin over <= ~u_tinyriscv.u_regs.regs[26]; // when = 1, run over - succ <= ~u_tinyriscv.u_regs.regs[27]; // when = 1, succ + succ <= ~u_tinyriscv.u_regs.regs[27]; // when = 1, run succ, otherwise fail end end - + // tinyriscv澶勭悊鍣ㄦ牳妯″潡渚嬪寲 tinyriscv u_tinyriscv( .clk(clk), .rst(rst), @@ -162,6 +164,7 @@ module tinyriscv_soc_top( .int_i(int_flag) ); + // rom妯″潡渚嬪寲 rom u_rom( .clk(clk), .rst(rst), @@ -173,6 +176,7 @@ module tinyriscv_soc_top( .ack_o(s0_ack_i) ); + // ram妯″潡渚嬪寲 ram u_ram( .clk(clk), .rst(rst), @@ -184,6 +188,7 @@ module tinyriscv_soc_top( .ack_o(s1_ack_i) ); + // timer妯″潡渚嬪寲 timer timer_0( .clk(clk), .rst(rst), @@ -196,6 +201,7 @@ module tinyriscv_soc_top( .ack_o(s2_ack_i) ); + // uart_tx妯″潡渚嬪寲 uart_tx uart_tx_0( .clk(clk), .rst(rst), @@ -208,6 +214,7 @@ module tinyriscv_soc_top( .tx_pin(tx_pin) ); + // gpio妯″潡渚嬪寲 gpio gpio_0( .clk(clk), .rst(rst), @@ -220,6 +227,7 @@ module tinyriscv_soc_top( .io_pin(io_pin) ); + // rib妯″潡渚嬪寲 rib u_rib( .clk(clk), .rst(rst), @@ -291,8 +299,7 @@ module tinyriscv_soc_top( .hold_flag_o(rib_hold_flag_o) ); - - // jtag module reset logic + // jtag妯″潡澶嶄綅閫昏緫 always @ (posedge clk) begin if (rst == `RstEnable) begin jtag_rst <= 1'b1; @@ -307,6 +314,7 @@ module tinyriscv_soc_top( end end + // jtag妯″潡渚嬪寲 jtag_top u_jtag_top( .jtag_rst_n(jtag_rst), .jtag_pin_TCK(jtag_TCK),