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fix reg1 reg2 bits width 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-18 11:35:43 +08:00
parent b29781a8de
commit ce225394df
1 changed files with 76 additions and 76 deletions
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152
rtl/core/id.v
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@ -71,8 +71,8 @@ module id(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
csr_raddr_o <= `ZeroWord; csr_raddr_o <= `ZeroWord;
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord; inst_addr_o <= `ZeroWord;
@ -81,7 +81,7 @@ module id(
csr_rdata_o <= `ZeroWord; csr_rdata_o <= `ZeroWord;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
csr_we_o <= `WriteDisable; csr_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
csr_waddr_o <= `ZeroWord; csr_waddr_o <= `ZeroWord;
mem_req <= `RIB_NREQ; mem_req <= `RIB_NREQ;
end else begin end else begin
@ -102,55 +102,55 @@ module id(
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_SLTI: begin `INST_SLTI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_SLTIU: begin `INST_SLTIU: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_XORI: begin `INST_XORI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_ORI: begin `INST_ORI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_ANDI: begin `INST_ANDI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_SLLI: begin `INST_SLLI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_SRI: begin `INST_SRI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
endcase endcase
end end
@ -207,9 +207,9 @@ module id(
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
endcase endcase
end else if (funct7 == 7'b0000001) begin end else if (funct7 == 7'b0000001) begin
@ -264,60 +264,60 @@ module id(
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
endcase endcase
end else begin end else begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
end end
`INST_TYPE_L: begin `INST_TYPE_L: begin
case (funct3) case (funct3)
`INST_LB: begin `INST_LB: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_LH: begin `INST_LH: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_LW: begin `INST_LW: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_LBU: begin `INST_LBU: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_LHU: begin `INST_LHU: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
endcase endcase
end end
@ -327,28 +327,28 @@ module id(
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_SH: begin `INST_SH: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
`INST_SW: begin `INST_SW: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
mem_req <= `RIB_REQ; mem_req <= `RIB_REQ;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
endcase endcase
end end
@ -358,19 +358,19 @@ module id(
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
`INST_BNE: begin `INST_BNE: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
`INST_BLT: begin `INST_BLT: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
`INST_BGE: begin `INST_BGE: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
@ -382,122 +382,122 @@ module id(
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
`INST_BGEU: begin `INST_BGEU: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2; reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
end end
endcase endcase
end end
`INST_JAL: begin `INST_JAL: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_JALR: begin `INST_JALR: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_waddr_o <= rd; reg_waddr_o <= rd;
end end
`INST_LUI: begin `INST_LUI: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_AUIPC: begin `INST_AUIPC: begin
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_NOP: begin `INST_NOP: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_FENCE: begin `INST_FENCE: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
`INST_CSR: begin `INST_CSR: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
csr_raddr_o <= {20'h0, inst_i[31:20]}; csr_raddr_o <= {20'h0, inst_i[31:20]};
csr_waddr_o <= {20'h0, inst_i[31:20]}; csr_waddr_o <= {20'h0, inst_i[31:20]};
case (funct3) case (funct3)
`INST_CSRRW: begin `INST_CSRRW: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
`INST_CSRRS: begin `INST_CSRRS: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
`INST_CSRRC: begin `INST_CSRRC: begin
reg1_raddr_o <= rs1; reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
`INST_CSRRWI: begin `INST_CSRRWI: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
`INST_CSRRSI: begin `INST_CSRRSI: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
`INST_CSRRCI: begin `INST_CSRRCI: begin
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o <= `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o <= rd;
csr_we_o <= `WriteEnable; csr_we_o <= `WriteEnable;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
csr_we_o <= `WriteDisable; csr_we_o <= `WriteDisable;
end end
endcase endcase
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroReg;
reg1_raddr_o <= `ZeroWord; reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroWord; reg2_raddr_o <= `ZeroReg;
end end
endcase endcase
end end