rtl: perips: fix machine timer
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/4/head
parent
646bc96419
commit
c847244c5b
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@ -22,7 +22,7 @@ module machine_timer(
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input wire[31:0] data_i,
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input wire[31:0] data_i,
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input wire[3:0] sel_i,
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input wire[3:0] sel_i,
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input wire we_i,
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input wire we_i,
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output wire[31:0] data_o,
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output wire[31:0] data_o,
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output wire irq_o
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output wire irq_o
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);
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);
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@ -37,7 +37,7 @@ module machine_timer(
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reg[31:0] mtime_ctrl_d, mtime_ctrl_q;
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reg[31:0] mtime_ctrl_d, mtime_ctrl_q;
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reg[31:0] mtime_cmp_d, mtime_cmp_q;
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reg[31:0] mtime_cmp_d, mtime_cmp_q;
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reg[31:0] mtime_count_q;
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reg[31:0] mtime_count_q;
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reg data_q;
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reg[31:0] data_d, data_q;
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wire[3:0] rw_addr = addr_i[3:0];
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wire[3:0] rw_addr = addr_i[3:0];
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wire w0 = we_i & sel_i[0];
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wire w0 = we_i & sel_i[0];
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@ -77,12 +77,12 @@ module machine_timer(
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// read
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// read
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always @ (*) begin
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always @ (*) begin
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data_q = 32'h0;
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data_d = data_q;
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case (rw_addr)
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case (rw_addr)
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mtime_ctrl_reg: data_q = mtime_ctrl_q;
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mtime_ctrl_reg: data_d = mtime_ctrl_q;
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mtime_cmp_reg: data_q = mtime_cmp_q;
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mtime_cmp_reg: data_d = mtime_cmp_q;
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mtime_count_reg: data_q = mtime_count_q;
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mtime_count_reg: data_d = mtime_count_q;
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default:;
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default:;
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endcase
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endcase
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end
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end
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@ -93,9 +93,11 @@ module machine_timer(
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if (!rst_n) begin
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if (!rst_n) begin
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mtime_ctrl_q <= 32'h0;
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mtime_ctrl_q <= 32'h0;
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mtime_cmp_q <= 32'h0;
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mtime_cmp_q <= 32'h0;
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data_q <= 32'h0;
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end else begin
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end else begin
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mtime_ctrl_q <= mtime_ctrl_d;
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mtime_ctrl_q <= mtime_ctrl_d;
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mtime_cmp_q <= mtime_cmp_d;
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mtime_cmp_q <= mtime_cmp_d;
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data_q <= data_d;
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end
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end
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end
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end
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