parent
fd5413791d
commit
c6163aaff1
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@ -22,6 +22,7 @@
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`define CAUSE_EXCEP_ECALL_M {1'b0, 31'd11}
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`define CAUSE_EXCEP_ECALL_M {1'b0, 31'd11}
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`define CAUSE_EXCEP_EBREAK_M {1'b0, 31'd3}
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`define CAUSE_EXCEP_EBREAK_M {1'b0, 31'd3}
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`define CAUSE_EXCEP_ILLEGAL_INST_M {1'b0, 31'd2}
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`define MIE_MTIE_BIT 7
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`define MIE_MTIE_BIT 7
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`define MIE_MEIE_BIT 11
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`define MIE_MEIE_BIT 11
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@ -48,6 +49,8 @@ module exception (
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input wire inst_dret_i, // dret指令
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input wire inst_dret_i, // dret指令
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input wire[31:0] inst_addr_i, // 指令地址
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input wire[31:0] inst_addr_i, // 指令地址
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input wire illegal_inst_i,
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input wire[31:0] mtvec_i, // mtvec寄存器
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input wire[31:0] mtvec_i, // mtvec寄存器
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input wire[31:0] mepc_i, // mepc寄存器
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input wire[31:0] mepc_i, // mepc寄存器
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input wire[31:0] mstatus_i, // mstatus寄存器
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input wire[31:0] mstatus_i, // mstatus寄存器
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@ -166,7 +169,11 @@ module exception (
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reg[31:0] exception_offset;
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reg[31:0] exception_offset;
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always @ (*) begin
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always @ (*) begin
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if (inst_ecall_i & inst_valid_i) begin
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if (illegal_inst_i) begin
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exception_req = 1'b1;
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exception_cause = `CAUSE_EXCEP_ILLEGAL_INST_M;
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exception_offset = ILLEGAL_INSTR_OFFSET;
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end else if (inst_ecall_i & inst_valid_i) begin
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exception_req = 1'b1;
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exception_req = 1'b1;
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exception_cause = `CAUSE_EXCEP_ECALL_M;
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exception_cause = `CAUSE_EXCEP_ECALL_M;
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exception_offset = ECALL_OFFSET;
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exception_offset = ECALL_OFFSET;
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@ -32,6 +32,7 @@ module idu(
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input wire[31:0] rs2_rdata_i, // 通用寄存器2输入数据
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input wire[31:0] rs2_rdata_i, // 通用寄存器2输入数据
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output wire stall_o,
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output wire stall_o,
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output wire illegal_inst_o,
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// to id_ex
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// to id_ex
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output wire[31:0] inst_o,
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output wire[31:0] inst_o,
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@ -302,4 +303,6 @@ module idu(
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assign stall_o = 1'b0;
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assign stall_o = 1'b0;
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assign illegal_inst_o = ~(|dec_info_bus_o);
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endmodule
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endmodule
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@ -78,6 +78,7 @@ module tinyriscv_core #(
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wire id_stall_o;
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wire id_stall_o;
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wire[31:0] id_rs1_rdata_o;
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wire[31:0] id_rs1_rdata_o;
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wire[31:0] id_rs2_rdata_o;
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wire[31:0] id_rs2_rdata_o;
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wire id_illegal_inst_o;
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// idu_exu模块输出信号
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// idu_exu模块输出信号
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wire[31:0] ie_inst_o;
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wire[31:0] ie_inst_o;
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@ -233,6 +234,7 @@ module tinyriscv_core #(
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.rs1_rdata_o(id_rs1_rdata_o),
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.rs1_rdata_o(id_rs1_rdata_o),
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.rs2_rdata_o(id_rs2_rdata_o),
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.rs2_rdata_o(id_rs2_rdata_o),
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.stall_o(id_stall_o),
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.stall_o(id_stall_o),
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.illegal_inst_o(id_illegal_inst_o),
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.dec_info_bus_o(id_dec_info_bus_o),
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.dec_info_bus_o(id_dec_info_bus_o),
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.dec_imm_o(id_dec_imm_o),
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.dec_imm_o(id_dec_imm_o),
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.dec_pc_o(id_dec_pc_o),
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.dec_pc_o(id_dec_pc_o),
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exception u_exception(
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exception u_exception(
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.clk(clk),
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.clk(clk),
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.rst_n(rst_n),
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.rst_n(rst_n),
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.illegal_inst_i(id_illegal_inst_o),
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.inst_valid_i(ie_inst_valid_o),
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.inst_valid_i(ie_inst_valid_o),
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.inst_executed_i(ex_inst_executed_o),
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.inst_executed_i(ex_inst_executed_o),
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.inst_ecall_i(ex_inst_ecall_o),
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.inst_ecall_i(ex_inst_ecall_o),
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@ -46,7 +46,13 @@ handle_exception_unknown:
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j handle_exception_unknown
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j handle_exception_unknown
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illegal_instruction_handler:
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illegal_instruction_handler:
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j illegal_instruction_handler
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#ifdef SIMULATION
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call sim_ctrl_init
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la a0, illegal_instruction_msg
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jal ra, xputs
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#endif
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illegal_instruction_loop:
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j illegal_instruction_loop
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instruction_addr_misaligned_handler:
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instruction_addr_misaligned_handler:
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j instruction_addr_misaligned_handler
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j instruction_addr_misaligned_handler
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fast_irq_handler:
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fast_irq_handler:
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j fast_irq_handler
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j fast_irq_handler
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.section .rodata
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illegal_instruction_msg:
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.string "illegal instruction exception handler entered\n"
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Loading…
Reference in New Issue