diff --git a/rtl/core/exception.sv b/rtl/core/exception.sv
index 72003d7..dc68f6f 100644
--- a/rtl/core/exception.sv
+++ b/rtl/core/exception.sv
@@ -22,6 +22,7 @@
 
 `define CAUSE_EXCEP_ECALL_M     {1'b0, 31'd11}
 `define CAUSE_EXCEP_EBREAK_M    {1'b0, 31'd3}
+`define CAUSE_EXCEP_ILLEGAL_INST_M     {1'b0, 31'd2}
 
 `define MIE_MTIE_BIT            7
 `define MIE_MEIE_BIT            11
@@ -48,6 +49,8 @@ module exception (
     input wire inst_dret_i,                     // dret指令
     input wire[31:0] inst_addr_i,               // 指令地址
 
+    input wire illegal_inst_i,
+
     input wire[31:0] mtvec_i,                   // mtvec寄存器
     input wire[31:0] mepc_i,                    // mepc寄存器
     input wire[31:0] mstatus_i,                 // mstatus寄存器
@@ -166,7 +169,11 @@ module exception (
     reg[31:0] exception_offset;
 
     always @ (*) begin
-        if (inst_ecall_i & inst_valid_i) begin
+        if (illegal_inst_i) begin
+            exception_req = 1'b1;
+            exception_cause = `CAUSE_EXCEP_ILLEGAL_INST_M;
+            exception_offset = ILLEGAL_INSTR_OFFSET;
+        end else if (inst_ecall_i & inst_valid_i) begin
             exception_req = 1'b1;
             exception_cause = `CAUSE_EXCEP_ECALL_M;
             exception_offset = ECALL_OFFSET;
diff --git a/rtl/core/idu.sv b/rtl/core/idu.sv
index a568143..8e021dd 100644
--- a/rtl/core/idu.sv
+++ b/rtl/core/idu.sv
@@ -32,6 +32,7 @@ module idu(
     input wire[31:0] rs2_rdata_i,      // 通用寄存器2输入数据
 
     output wire stall_o,
+    output wire illegal_inst_o,
 
     // to id_ex
     output wire[31:0] inst_o,
@@ -302,4 +303,6 @@ module idu(
 
     assign stall_o = 1'b0;
 
+    assign illegal_inst_o = ~(|dec_info_bus_o);
+
 endmodule
diff --git a/rtl/core/tinyriscv_core.sv b/rtl/core/tinyriscv_core.sv
index 9d938e0..4110748 100644
--- a/rtl/core/tinyriscv_core.sv
+++ b/rtl/core/tinyriscv_core.sv
@@ -78,6 +78,7 @@ module tinyriscv_core #(
     wire id_stall_o;
     wire[31:0] id_rs1_rdata_o;
     wire[31:0] id_rs2_rdata_o;
+    wire id_illegal_inst_o;
 
     // idu_exu模块输出信号
     wire[31:0] ie_inst_o;
@@ -233,6 +234,7 @@ module tinyriscv_core #(
         .rs1_rdata_o(id_rs1_rdata_o),
         .rs2_rdata_o(id_rs2_rdata_o),
         .stall_o(id_stall_o),
+        .illegal_inst_o(id_illegal_inst_o),
         .dec_info_bus_o(id_dec_info_bus_o),
         .dec_imm_o(id_dec_imm_o),
         .dec_pc_o(id_dec_pc_o),
@@ -314,6 +316,7 @@ module tinyriscv_core #(
     exception u_exception(
         .clk(clk),
         .rst_n(rst_n),
+        .illegal_inst_i(id_illegal_inst_o),
         .inst_valid_i(ie_inst_valid_o),
         .inst_executed_i(ex_inst_executed_o),
         .inst_ecall_i(ex_inst_ecall_o),
diff --git a/sdk/bsp/vector_table.S b/sdk/bsp/vector_table.S
index d4d3345..ca1c022 100644
--- a/sdk/bsp/vector_table.S
+++ b/sdk/bsp/vector_table.S
@@ -46,7 +46,13 @@ handle_exception_unknown:
     j handle_exception_unknown
 
 illegal_instruction_handler:
-    j illegal_instruction_handler
+#ifdef SIMULATION
+    call sim_ctrl_init
+    la a0, illegal_instruction_msg
+    jal ra, xputs
+#endif
+illegal_instruction_loop:
+    j illegal_instruction_loop
 
 instruction_addr_misaligned_handler:
     j instruction_addr_misaligned_handler
@@ -89,3 +95,7 @@ fast_irq4_handler:
 
 fast_irq_handler:
     j fast_irq_handler
+
+.section .rodata
+illegal_instruction_msg:
+	.string "illegal instruction exception handler entered\n"