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temp commit 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-04-12 19:18:35 +08:00
parent 16fa475ba7
commit bd2d372c66
2 changed files with 22 additions and 7 deletions
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21
rtl/core/defines.sv
View File

@ -14,15 +14,30 @@
limitations under the License. limitations under the License.
*/ */
`define CPU_RESET_ADDR 32'h0 // CPU复位地址 `define CPU_RESET_ADDR 32'h00000000 // CPU复位地址
`define CPU_CLOCK_HZ 50000000 // CPU时钟(50MHZ) `define CPU_CLOCK_HZ 50000000 // CPU时钟(50MHZ)
`define INST_MEM_START_ADDR 32'h0 // 指令存储器起始地址
`define INST_MEM_END_ADDR 32'h0fffffff // 指令存储器结束地址
`define JTAG_RESET_FF_LEVELS 5 `define JTAG_RESET_FF_LEVELS 5
`define ROM_DEPTH 8192 // 指令存储器深度，单位为word(4字节) `define ROM_DEPTH 8192 // 指令存储器深度，单位为word(4字节)
`define RAM_DEPTH 4096 // 数据存储器深度，单位为word(4字节) `define RAM_DEPTH 4096 // 数据存储器深度，单位为word(4字节)
// 外设地址、大小
// ROM
`define ROM_ADDR_MASK ~32'hfffff
`define ROM_ADDR_BASE 32'h00000000
// RAM
`define RAM_ADDR_MASK ~32'hfffff
`define RAM_ADDR_BASE 32'h10000000
// GPIO
`define GPIO_ADDR_MASK ~32'hffff
`define GPIO_ADDR_BASE 32'h40000000
// Timer
`define TIMER_ADDR_MASK ~32'hffff
`define TIMER_ADDR_BASE 32'h20000000
// UART
`define UART_ADDR_MASK ~32'hffff
`define UART_ADDR_BASE 32'h30000000
`define INT_WIDTH 8 `define INT_WIDTH 8
`define INT_NONE 8'h0 `define INT_NONE 8'h0

8
rtl/top/tinyriscv_soc_top.sv
View File

@ -96,8 +96,8 @@ module tinyriscv_soc_top(
); );
assign slave_addr_mask[Rom] = ~32'hfffff; assign slave_addr_mask[Rom] = `ROM_ADDR_MASK;
assign slave_addr_base[Rom] = 32'h00000000; assign slave_addr_base[Rom] = `ROM_ADDR_BASE;
// 指令存储器 // 指令存储器
rom #( rom #(
.DP(`ROM_DEPTH) .DP(`ROM_DEPTH)
@ -111,8 +111,8 @@ module tinyriscv_soc_top(
.data_o(slave_rdata[Rom]) .data_o(slave_rdata[Rom])
); );
assign slave_addr_mask[Ram] = ~32'hfffff; assign slave_addr_mask[Ram] = `RAM_ADDR_MASK;
assign slave_addr_base[Ram] = 32'h10000000; assign slave_addr_base[Ram] = `RAM_ADDR_BASE;
// 数据存储器 // 数据存储器
ram #( ram #(
.DP(`RAM_DEPTH) .DP(`RAM_DEPTH)