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tb: add tests type macro 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-06-05 16:59:26 +08:00
parent d9a1f89fd2
commit b7b8572542
1 changed files with 47 additions and 23 deletions
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70
sim/tb_top_verilator.sv
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@ -14,6 +14,12 @@
limitations under the License. limitations under the License.
*/ */
// 二选一，都不选时表示测试用户自定义程序
// tests/isa测试
//`define TEST_ISA 1
// tests/riscv-compliance测试
//`define TEST_RISCV_COMPLIANCE 1
module tb_top_verilator #( module tb_top_verilator #(
) ( ) (
@ -23,9 +29,14 @@ module tb_top_verilator #(
wire halted; wire halted;
wire[31:0] x3 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[3];
wire[31:0] x26 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[26]; wire[31:0] x26 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[26];
wire[31:0] x27 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[27]; wire[31:0] x27 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[27];
wire[31:0] end_flag = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[4];
wire[31:0] begin_signature = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[2];
wire[31:0] end_signature = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[3];
initial begin: load_prog initial begin: load_prog
automatic logic [1023:0] firmware; automatic logic [1023:0] firmware;
@ -38,6 +49,7 @@ module tb_top_verilator #(
end end
end end
integer r;
reg result_printed; reg result_printed;
always @(posedge clk_i or negedge rst_ni) begin always @(posedge clk_i or negedge rst_ni) begin
@ -47,30 +59,42 @@ module tb_top_verilator #(
if (u_tinyriscv_soc_top.ndmreset) begin if (u_tinyriscv_soc_top.ndmreset) begin
result_printed <= 1'b0; result_printed <= 1'b0;
end else if (!result_printed) begin end else if (!result_printed) begin
if (x26 == 32'b1) begin `ifdef TEST_RISCV_COMPLIANCE
if (x27 == 32'b1) begin if (end_flag == 32'h1) begin
$display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~"); for (r = begin_signature; r < end_signature; r = r + 4) begin
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("%x", u_tinyriscv_soc_top.u_rom.u_gen_ram.ram[r[31:2]]);
$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~"); end
$display("~~~~~~~~~ # # # # # # ~~~~~~~~~"); $finish;
$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~");
$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # #~~~~~~~~~");
$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end else begin
$display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # ######~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end end
result_printed <= 1'b1; `else
end if (x26 == 32'b1) begin
if (x27 == 32'b1) begin
$display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # ~~~~~~~~~");
$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~");
$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # #~~~~~~~~~");
$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end else begin
$display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
$display("~~~~~~~~~~# # # # ######~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
`ifdef TEST_ISA
$display("fail testnum = %2d", x3);
`endif
end
result_printed <= 1'b1;
end
`endif
end end
end end
end end