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rtl: timing optimization 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-09-09 21:00:14 +08:00
parent 5e4ab8c33c
commit b57bfe7736
9 changed files with 1313 additions and 1306 deletions
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135
rtl/core/csr_reg.v
View File

@ -47,7 +47,6 @@ module csr_reg(
); );
reg[`DoubleRegBus] cycle; reg[`DoubleRegBus] cycle;
reg[`RegBus] mtvec; reg[`RegBus] mtvec;
reg[`RegBus] mcause; reg[`RegBus] mcause;
@ -56,14 +55,12 @@ module csr_reg(
reg[`RegBus] mstatus; reg[`RegBus] mstatus;
reg[`RegBus] mscratch; reg[`RegBus] mscratch;
assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False; assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False;
assign clint_csr_mtvec = mtvec; assign clint_csr_mtvec = mtvec;
assign clint_csr_mepc = mepc; assign clint_csr_mepc = mepc;
assign clint_csr_mstatus = mstatus; assign clint_csr_mstatus = mstatus;
// cycle counter // cycle counter
// 复位撤销后就一直计数 // 复位撤销后就一直计数
always @ (posedge clk) begin always @ (posedge clk) begin
@ -142,84 +139,76 @@ module csr_reg(
// read reg // read reg
// ex模块读CSR寄存器 // ex模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin
data_o = `ZeroWord; data_o = data_i;
end else begin end else begin
if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin case (raddr_i[11:0])
data_o = data_i; `CSR_CYCLE: begin
end else begin data_o = cycle[31:0];
case (raddr_i[11:0]) end
`CSR_CYCLE: begin `CSR_CYCLEH: begin
data_o = cycle[31:0]; data_o = cycle[63:32];
end end
`CSR_CYCLEH: begin `CSR_MTVEC: begin
data_o = cycle[63:32]; data_o = mtvec;
end end
`CSR_MTVEC: begin `CSR_MCAUSE: begin
data_o = mtvec; data_o = mcause;
end end
`CSR_MCAUSE: begin `CSR_MEPC: begin
data_o = mcause; data_o = mepc;
end end
`CSR_MEPC: begin `CSR_MIE: begin
data_o = mepc; data_o = mie;
end end
`CSR_MIE: begin `CSR_MSTATUS: begin
data_o = mie; data_o = mstatus;
end end
`CSR_MSTATUS: begin `CSR_MSCRATCH: begin
data_o = mstatus; data_o = mscratch;
end end
`CSR_MSCRATCH: begin default: begin
data_o = mscratch; data_o = `ZeroWord;
end end
default: begin endcase
data_o = `ZeroWord;
end
endcase
end
end end
end end
// read reg // read reg
// clint模块读CSR寄存器 // clint模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin
clint_data_o = `ZeroWord; clint_data_o = clint_data_i;
end else begin end else begin
if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin case (clint_raddr_i[11:0])
clint_data_o = clint_data_i; `CSR_CYCLE: begin
end else begin clint_data_o = cycle[31:0];
case (clint_raddr_i[11:0]) end
`CSR_CYCLE: begin `CSR_CYCLEH: begin
clint_data_o = cycle[31:0]; clint_data_o = cycle[63:32];
end end
`CSR_CYCLEH: begin `CSR_MTVEC: begin
clint_data_o = cycle[63:32]; clint_data_o = mtvec;
end end
`CSR_MTVEC: begin `CSR_MCAUSE: begin
clint_data_o = mtvec; clint_data_o = mcause;
end end
`CSR_MCAUSE: begin `CSR_MEPC: begin
clint_data_o = mcause; clint_data_o = mepc;
end end
`CSR_MEPC: begin `CSR_MIE: begin
clint_data_o = mepc; clint_data_o = mie;
end end
`CSR_MIE: begin `CSR_MSTATUS: begin
clint_data_o = mie; clint_data_o = mstatus;
end end
`CSR_MSTATUS: begin `CSR_MSCRATCH: begin
clint_data_o = mstatus; clint_data_o = mscratch;
end end
`CSR_MSCRATCH: begin default: begin
clint_data_o = mscratch; clint_data_o = `ZeroWord;
end end
default: begin endcase
clint_data_o = `ZeroWord;
end
endcase
end
end end
end end

34
rtl/core/ctrl.v
View File

@ -46,28 +46,22 @@ module ctrl(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin jump_addr_o = jump_addr_i;
hold_flag_o = `Hold_None; jump_flag_o = jump_flag_i;
jump_flag_o = `JumpDisable; // 默认不暂停
jump_addr_o = `ZeroWord; hold_flag_o = `Hold_None;
// 按优先级处理不同模块的请求
if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o = `Hold_Id;
end else if (hold_flag_rib_i == `HoldEnable) begin
// 暂停PC，即取指地址不变
hold_flag_o = `Hold_Pc;
end else if (jtag_halt_flag_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o = `Hold_Id;
end else begin end else begin
jump_addr_o = jump_addr_i;
jump_flag_o = jump_flag_i;
// 默认不暂停
hold_flag_o = `Hold_None; hold_flag_o = `Hold_None;
// 按优先级处理不同模块的请求
if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o = `Hold_Id;
end else if (hold_flag_rib_i == `HoldEnable) begin
// 暂停PC，即取指地址不变
hold_flag_o = `Hold_Pc;
end else if (jtag_halt_flag_i == `HoldEnable) begin
// 暂停整条流水线
hold_flag_o = `Hold_Id;
end else begin
hold_flag_o = `Hold_None;
end
end end
end end

1250
rtl/core/ex.v
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File diff suppressed because it is too large Load Diff

399
rtl/core/id.v
View File

@ -69,253 +69,234 @@ module id(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin inst_o = inst_i;
reg1_raddr_o = `ZeroReg; inst_addr_o = inst_addr_i;
reg2_raddr_o = `ZeroReg; reg1_rdata_o = reg1_rdata_i;
csr_raddr_o = `ZeroWord; reg2_rdata_o = reg2_rdata_i;
inst_o = `INST_NOP; csr_rdata_o = csr_rdata_i;
inst_addr_o = `ZeroWord; csr_raddr_o = `ZeroWord;
reg1_rdata_o = `ZeroWord; csr_waddr_o = `ZeroWord;
reg2_rdata_o = `ZeroWord; csr_we_o = `WriteDisable;
csr_rdata_o = `ZeroWord; op1_o = `ZeroWord;
reg_we_o = `WriteDisable; op2_o = `ZeroWord;
csr_we_o = `WriteDisable; op1_jump_o = `ZeroWord;
reg_waddr_o = `ZeroReg; op2_jump_o = `ZeroWord;
csr_waddr_o = `ZeroWord;
op1_o = `ZeroWord;
op2_o = `ZeroWord;
op1_jump_o = `ZeroWord;
op2_jump_o = `ZeroWord;
end else begin
inst_o = inst_i;
inst_addr_o = inst_addr_i;
reg1_rdata_o = reg1_rdata_i;
reg2_rdata_o = reg2_rdata_i;
csr_rdata_o = csr_rdata_i;
csr_raddr_o = `ZeroWord;
csr_waddr_o = `ZeroWord;
csr_we_o = `WriteDisable;
op1_o = `ZeroWord;
op2_o = `ZeroWord;
op1_jump_o = `ZeroWord;
op2_jump_o = `ZeroWord;
case (opcode) case (opcode)
`INST_TYPE_I: begin `INST_TYPE_I: begin
case (funct3) case (funct3)
`INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin `INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin
reg_we_o = `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o = rd; reg_waddr_o = rd;
reg1_raddr_o = rs1; reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg;
op1_o = reg1_rdata_i; op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:20]}; op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end end
default: begin default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3)
`INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end else if (funct7 == 7'b0000001) begin
case (funct3)
`INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
end
`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
reg_we_o = `WriteDisable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
op1_jump_o = inst_addr_i;
op2_jump_o = 32'h4;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end else begin
reg_we_o = `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
end endcase
`INST_TYPE_L: begin end
`INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3) case (funct3)
`INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin `INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o = rd; reg_waddr_o = rd;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_S: begin
case (funct3)
`INST_SB, `INST_SW, `INST_SH: begin
reg1_raddr_o = rs1; reg1_raddr_o = rs1;
reg2_raddr_o = rs2; reg2_raddr_o = rs2;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
op1_o = reg1_rdata_i; op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; op2_o = reg2_rdata_i;
end end
default: begin default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end end
endcase endcase
end end else if (funct7 == 7'b0000001) begin
`INST_TYPE_B: begin
case (funct3) case (funct3)
`INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin `INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1; reg1_raddr_o = rs1;
reg2_raddr_o = rs2; reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
end
`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
reg_we_o = `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg; reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i; op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i; op2_o = reg2_rdata_i;
op1_jump_o = inst_addr_i; op1_jump_o = inst_addr_i;
op2_jump_o = {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; op2_jump_o = 32'h4;
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_JAL: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = inst_addr_i;
op2_jump_o = {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
end
`INST_JALR: begin
reg_we_o = `WriteEnable;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_waddr_o = rd;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = reg1_rdata_i;
op2_jump_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
`INST_LUI: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = {inst_i[31:12], 12'b0};
op2_o = `ZeroWord;
end
`INST_AUIPC: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = {inst_i[31:12], 12'b0};
end
`INST_NOP_OP: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
`INST_FENCE: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_jump_o = inst_addr_i;
op2_jump_o = 32'h4;
end
`INST_CSR: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
csr_raddr_o = {20'h0, inst_i[31:20]};
csr_waddr_o = {20'h0, inst_i[31:20]};
case (funct3)
`INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end
`INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end end
default: begin default: begin
reg_we_o = `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg;
csr_we_o = `WriteDisable;
end end
endcase endcase
end end else begin
default: begin
reg_we_o = `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
endcase end
end `INST_TYPE_L: begin
case (funct3)
`INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_S: begin
case (funct3)
`INST_SB, `INST_SW, `INST_SH: begin
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_B: begin
case (funct3)
`INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
op1_jump_o = inst_addr_i;
op2_jump_o = {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_JAL: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = inst_addr_i;
op2_jump_o = {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
end
`INST_JALR: begin
reg_we_o = `WriteEnable;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_waddr_o = rd;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = reg1_rdata_i;
op2_jump_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
`INST_LUI: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = {inst_i[31:12], 12'b0};
op2_o = `ZeroWord;
end
`INST_AUIPC: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = {inst_i[31:12], 12'b0};
end
`INST_NOP_OP: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
`INST_FENCE: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_jump_o = inst_addr_i;
op2_jump_o = 32'h4;
end
`INST_CSR: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
csr_raddr_o = {20'h0, inst_i[31:20]};
csr_waddr_o = {20'h0, inst_i[31:20]};
case (funct3)
`INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end
`INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
csr_we_o = `WriteDisable;
end
endcase
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end end
endmodule endmodule

127
rtl/core/id_ex.v
View File

@ -38,69 +38,74 @@ module id_ex(
input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志 input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
output reg[`MemAddrBus] op1_o, output wire[`MemAddrBus] op1_o,
output reg[`MemAddrBus] op2_o, output wire[`MemAddrBus] op2_o,
output reg[`MemAddrBus] op1_jump_o, output wire[`MemAddrBus] op1_jump_o,
output reg[`MemAddrBus] op2_jump_o, output wire[`MemAddrBus] op2_jump_o,
output reg[`InstBus] inst_o, // 指令内容 output wire[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o, // 指令地址 output wire[`InstAddrBus] inst_addr_o, // 指令地址
output reg reg_we_o, // 写通用寄存器标志 output wire reg_we_o, // 写通用寄存器标志
output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址 output wire[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
output reg[`RegBus] reg1_rdata_o, // 通用寄存器1读数据 output wire[`RegBus] reg1_rdata_o, // 通用寄存器1读数据
output reg[`RegBus] reg2_rdata_o, // 通用寄存器2读数据 output wire[`RegBus] reg2_rdata_o, // 通用寄存器2读数据
output reg csr_we_o, // 写CSR寄存器标志 output wire csr_we_o, // 写CSR寄存器标志
output reg[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址 output wire[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址
output reg[`RegBus] csr_rdata_o // CSR寄存器读数据 output wire[`RegBus] csr_rdata_o // CSR寄存器读数据
); );
always @ (posedge clk) begin wire hold_en = (hold_flag_i >= `Hold_Id);
if (rst == `RstEnable) begin
inst_o <= `INST_NOP; wire[`InstBus] inst;
inst_addr_o <= `ZeroWord; gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst);
reg_we_o <= `WriteDisable; assign inst_o = inst;
reg_waddr_o <= `ZeroWord;
reg1_rdata_o <= `ZeroWord; wire[`InstAddrBus] inst_addr;
reg2_rdata_o <= `ZeroWord; gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr);
csr_we_o <= `WriteDisable; assign inst_addr_o = inst_addr;
csr_waddr_o <= `ZeroWord;
csr_rdata_o <= `ZeroWord; wire reg_we;
op1_o <= `ZeroWord; gen_pipe_dff #(1) reg_we_ff(clk, rst, hold_en, `WriteDisable, reg_we_i, reg_we);
op2_o <= `ZeroWord; assign reg_we_o = reg_we;
op1_jump_o <= `ZeroWord;
op2_jump_o <= `ZeroWord; wire[`RegAddrBus] reg_waddr;
end else begin gen_pipe_dff #(5) reg_waddr_ff(clk, rst, hold_en, `ZeroReg, reg_waddr_i, reg_waddr);
// 流水线暂停时传递默认值 assign reg_waddr_o = reg_waddr;
if (hold_flag_i >= `Hold_Id) begin
inst_o <= `INST_NOP; wire[`RegBus] reg1_rdata;
inst_addr_o <= inst_addr_i; gen_pipe_dff #(32) reg1_rdata_ff(clk, rst, hold_en, `ZeroWord, reg1_rdata_i, reg1_rdata);
reg_we_o <= `WriteDisable; assign reg1_rdata_o = reg1_rdata;
reg_waddr_o <= `ZeroWord;
reg1_rdata_o <= `ZeroWord; wire[`RegBus] reg2_rdata;
reg2_rdata_o <= `ZeroWord; gen_pipe_dff #(32) reg2_rdata_ff(clk, rst, hold_en, `ZeroWord, reg2_rdata_i, reg2_rdata);
csr_we_o <= `WriteDisable; assign reg2_rdata_o = reg2_rdata;
csr_waddr_o <= `ZeroWord;
csr_rdata_o <= `ZeroWord; wire csr_we;
op1_o <= `ZeroWord; gen_pipe_dff #(1) csr_we_ff(clk, rst, hold_en, `WriteDisable, csr_we_i, csr_we);
op2_o <= `ZeroWord; assign csr_we_o = csr_we;
op1_jump_o <= `ZeroWord;
op2_jump_o <= `ZeroWord; wire[`MemAddrBus] csr_waddr;
end else begin gen_pipe_dff #(32) csr_waddr_ff(clk, rst, hold_en, `ZeroWord, csr_waddr_i, csr_waddr);
inst_o <= inst_i; assign csr_waddr_o = csr_waddr;
inst_addr_o <= inst_addr_i;
reg_we_o <= reg_we_i; wire[`RegBus] csr_rdata;
reg_waddr_o <= reg_waddr_i; gen_pipe_dff #(32) csr_rdata_ff(clk, rst, hold_en, `ZeroWord, csr_rdata_i, csr_rdata);
reg1_rdata_o <= reg1_rdata_i; assign csr_rdata_o = csr_rdata;
reg2_rdata_o <= reg2_rdata_i;
csr_we_o <= csr_we_i; wire[`MemAddrBus] op1;
csr_waddr_o <= csr_waddr_i; gen_pipe_dff #(32) op1_ff(clk, rst, hold_en, `ZeroWord, op1_i, op1);
csr_rdata_o <= csr_rdata_i; assign op1_o = op1;
op1_o <= op1_i;
op2_o <= op2_i; wire[`MemAddrBus] op2;
op1_jump_o <= op1_jump_i; gen_pipe_dff #(32) op2_ff(clk, rst, hold_en, `ZeroWord, op2_i, op2);
op2_jump_o <= op2_jump_i; assign op2_o = op2;
end
end wire[`MemAddrBus] op1_jump;
end gen_pipe_dff #(32) op1_jump_ff(clk, rst, hold_en, `ZeroWord, op1_jump_i, op1_jump);
assign op1_jump_o = op1_jump;
wire[`MemAddrBus] op2_jump;
gen_pipe_dff #(32) op2_jump_ff(clk, rst, hold_en, `ZeroWord, op2_jump_i, op2_jump);
assign op2_jump_o = op2_jump;
endmodule endmodule

35
rtl/core/if_id.v
View File

@ -28,28 +28,25 @@ module if_id(
input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志 input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
input wire[`INT_BUS] int_flag_i, // 外设中断输入信号 input wire[`INT_BUS] int_flag_i, // 外设中断输入信号
output reg[`INT_BUS] int_flag_o, output wire[`INT_BUS] int_flag_o,
output reg[`InstBus] inst_o, // 指令内容 output wire[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o // 指令地址 output wire[`InstAddrBus] inst_addr_o // 指令地址
); );
always @ (posedge clk) begin wire hold_en = (hold_flag_i >= `Hold_If);
if (rst == `RstEnable) begin
inst_o <= `INST_NOP; wire[`InstBus] inst;
inst_addr_o <= `ZeroWord; gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst);
int_flag_o <= `INT_NONE; assign inst_o = inst;
// 流水线暂停时传递默认值
end else if (hold_flag_i >= `Hold_If) begin wire[`InstAddrBus] inst_addr;
inst_o <= `INST_NOP; gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr);
inst_addr_o <= inst_addr_i; assign inst_addr_o = inst_addr;
int_flag_o <= `INT_NONE;
end else begin wire[`INT_BUS] int_flag;
inst_o <= inst_i; gen_pipe_dff #(8) int_ff(clk, rst, hold_en, `INT_NONE, int_flag_i, int_flag);
inst_addr_o <= inst_addr_i; assign int_flag_o = int_flag;
int_flag_o <= int_flag_i;
end
end
endmodule endmodule

16
rtl/core/regs.v
View File

@ -55,9 +55,9 @@ module regs(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstDisable) begin if (rst == `RstDisable) begin
// 优先ex模块写操作 // 优先ex模块写操作
if ((we_i == `WriteEnable) && (waddr_i != `RegNumLog2'h0)) begin if ((we_i == `WriteEnable) && (waddr_i != `ZeroReg)) begin
regs[waddr_i] <= wdata_i; regs[waddr_i] <= wdata_i;
end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `RegNumLog2'h0)) begin end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `ZeroReg)) begin
regs[jtag_addr_i] <= jtag_data_i; regs[jtag_addr_i] <= jtag_data_i;
end end
end end
@ -65,9 +65,7 @@ module regs(
// 读寄存器1 // 读寄存器1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (raddr1_i == `ZeroReg) begin
rdata1_o = `ZeroWord;
end else if (raddr1_i == `RegNumLog2'h0) begin
rdata1_o = `ZeroWord; rdata1_o = `ZeroWord;
// 如果读地址等于写地址，并且正在写操作，则直接返回写数据 // 如果读地址等于写地址，并且正在写操作，则直接返回写数据
end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin
@ -79,9 +77,7 @@ module regs(
// 读寄存器2 // 读寄存器2
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (raddr2_i == `ZeroReg) begin
rdata2_o = `ZeroWord;
end else if (raddr2_i == `RegNumLog2'h0) begin
rdata2_o = `ZeroWord; rdata2_o = `ZeroWord;
// 如果读地址等于写地址，并且正在写操作，则直接返回写数据 // 如果读地址等于写地址，并且正在写操作，则直接返回写数据
end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin
@ -93,9 +89,7 @@ module regs(
// jtag读寄存器 // jtag读寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (jtag_addr_i == `ZeroReg) begin
jtag_data_o = `ZeroWord;
end else if (jtag_addr_i == `RegNumLog2'h0) begin
jtag_data_o = `ZeroWord; jtag_data_o = `ZeroWord;
end else begin end else begin
jtag_data_o = regs[jtag_addr_i]; jtag_data_o = regs[jtag_addr_i];

443
rtl/core/rib.v
View File

@ -93,7 +93,7 @@ module rib(
// 访问地址的最高4位决定要访问的是哪一个从设备 // 访问地址的最高4位决定要访问的是哪一个从设备
// 因此最高支持16个从设备 // 因此最多支持16个从设备
parameter [3:0]slave_0 = 4'b0000; parameter [3:0]slave_0 = 4'b0000;
parameter [3:0]slave_1 = 4'b0001; parameter [3:0]slave_1 = 4'b0001;
parameter [3:0]slave_2 = 4'b0010; parameter [3:0]slave_2 = 4'b0010;
@ -115,257 +115,226 @@ module rib(
// 仲裁逻辑 // 仲裁逻辑
// 固定优先级仲裁机制 // 固定优先级仲裁机制
// 优先级由高到低：主设备0，主设备2，主设备1 // 优先级由高到低：主设备3，主设备0，主设备2，主设备1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (req[3]) begin
grant = grant3;
hold_flag_o = `HoldEnable;
end else if (req[0]) begin
grant = grant0;
hold_flag_o = `HoldEnable;
end else if (req[2]) begin
grant = grant2;
hold_flag_o = `HoldEnable;
end else begin
grant = grant1; grant = grant1;
hold_flag_o = `HoldDisable; hold_flag_o = `HoldDisable;
end else begin
if (req[3]) begin
grant = grant3;
hold_flag_o = `HoldEnable;
end else if (req[0]) begin
grant = grant0;
hold_flag_o = `HoldEnable;
end else if (req[2]) begin
grant = grant2;
hold_flag_o = `HoldEnable;
end else begin
grant = grant1;
hold_flag_o = `HoldDisable;
end
end end
end end
// 根据仲裁结果，选择(访问)对应的从设备 // 根据仲裁结果，选择(访问)对应的从设备
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin m0_data_o = `ZeroWord;
m0_data_o = `ZeroWord; m1_data_o = `INST_NOP;
m1_data_o = `INST_NOP; m2_data_o = `ZeroWord;
m2_data_o = `ZeroWord; m3_data_o = `ZeroWord;
m3_data_o = `ZeroWord;
s0_addr_o = `ZeroWord; s0_addr_o = `ZeroWord;
s1_addr_o = `ZeroWord; s1_addr_o = `ZeroWord;
s2_addr_o = `ZeroWord; s2_addr_o = `ZeroWord;
s3_addr_o = `ZeroWord; s3_addr_o = `ZeroWord;
s4_addr_o = `ZeroWord; s4_addr_o = `ZeroWord;
s5_addr_o = `ZeroWord; s5_addr_o = `ZeroWord;
s0_data_o = `ZeroWord; s0_data_o = `ZeroWord;
s1_data_o = `ZeroWord; s1_data_o = `ZeroWord;
s2_data_o = `ZeroWord; s2_data_o = `ZeroWord;
s3_data_o = `ZeroWord; s3_data_o = `ZeroWord;
s4_data_o = `ZeroWord; s4_data_o = `ZeroWord;
s5_data_o = `ZeroWord; s5_data_o = `ZeroWord;
s0_we_o = `WriteDisable; s0_we_o = `WriteDisable;
s1_we_o = `WriteDisable; s1_we_o = `WriteDisable;
s2_we_o = `WriteDisable; s2_we_o = `WriteDisable;
s3_we_o = `WriteDisable; s3_we_o = `WriteDisable;
s4_we_o = `WriteDisable; s4_we_o = `WriteDisable;
s5_we_o = `WriteDisable; s5_we_o = `WriteDisable;
end else begin
m0_data_o = `ZeroWord;
m1_data_o = `INST_NOP;
m2_data_o = `ZeroWord;
m3_data_o = `ZeroWord;
s0_addr_o = `ZeroWord; case (grant)
s1_addr_o = `ZeroWord; grant0: begin
s2_addr_o = `ZeroWord; case (m0_addr_i[31:28])
s3_addr_o = `ZeroWord; slave_0: begin
s4_addr_o = `ZeroWord; s0_we_o = m0_we_i;
s5_addr_o = `ZeroWord; s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s0_data_o = `ZeroWord; s0_data_o = m0_data_i;
s1_data_o = `ZeroWord; m0_data_o = s0_data_i;
s2_data_o = `ZeroWord; end
s3_data_o = `ZeroWord; slave_1: begin
s4_data_o = `ZeroWord; s1_we_o = m0_we_i;
s5_data_o = `ZeroWord; s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s0_we_o = `WriteDisable; s1_data_o = m0_data_i;
s1_we_o = `WriteDisable; m0_data_o = s1_data_i;
s2_we_o = `WriteDisable; end
s3_we_o = `WriteDisable; slave_2: begin
s4_we_o = `WriteDisable; s2_we_o = m0_we_i;
s5_we_o = `WriteDisable; s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s2_data_o = m0_data_i;
m0_data_o = s2_data_i;
end
slave_3: begin
s3_we_o = m0_we_i;
s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s3_data_o = m0_data_i;
m0_data_o = s3_data_i;
end
slave_4: begin
s4_we_o = m0_we_i;
s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s4_data_o = m0_data_i;
m0_data_o = s4_data_i;
end
slave_5: begin
s5_we_o = m0_we_i;
s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s5_data_o = m0_data_i;
m0_data_o = s5_data_i;
end
default: begin
case (grant) end
grant0: begin endcase
case (m0_addr_i[31:28]) end
slave_0: begin grant1: begin
s0_we_o = m0_we_i; case (m1_addr_i[31:28])
s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_0: begin
s0_data_o = m0_data_i; s0_we_o = m1_we_i;
m0_data_o = s0_data_i; s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s0_data_o = m1_data_i;
slave_1: begin m1_data_o = s0_data_i;
s1_we_o = m0_we_i; end
s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_1: begin
s1_data_o = m0_data_i; s1_we_o = m1_we_i;
m0_data_o = s1_data_i; s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s1_data_o = m1_data_i;
slave_2: begin m1_data_o = s1_data_i;
s2_we_o = m0_we_i; end
s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_2: begin
s2_data_o = m0_data_i; s2_we_o = m1_we_i;
m0_data_o = s2_data_i; s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s2_data_o = m1_data_i;
slave_3: begin m1_data_o = s2_data_i;
s3_we_o = m0_we_i; end
s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_3: begin
s3_data_o = m0_data_i; s3_we_o = m1_we_i;
m0_data_o = s3_data_i; s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s3_data_o = m1_data_i;
slave_4: begin m1_data_o = s3_data_i;
s4_we_o = m0_we_i; end
s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_4: begin
s4_data_o = m0_data_i; s4_we_o = m1_we_i;
m0_data_o = s4_data_i; s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s4_data_o = m1_data_i;
slave_5: begin m1_data_o = s4_data_i;
s5_we_o = m0_we_i; end
s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; slave_5: begin
s5_data_o = m0_data_i; s5_we_o = m1_we_i;
m0_data_o = s5_data_i; s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
end s5_data_o = m1_data_i;
default: begin m1_data_o = s5_data_i;
end
default: begin
end end
endcase endcase
end end
grant1: begin grant2: begin
case (m1_addr_i[31:28]) case (m2_addr_i[31:28])
slave_0: begin slave_0: begin
s0_we_o = m1_we_i; s0_we_o = m2_we_i;
s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s0_data_o = m1_data_i; s0_data_o = m2_data_i;
m1_data_o = s0_data_i; m2_data_o = s0_data_i;
end end
slave_1: begin slave_1: begin
s1_we_o = m1_we_i; s1_we_o = m2_we_i;
s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s1_data_o = m1_data_i; s1_data_o = m2_data_i;
m1_data_o = s1_data_i; m2_data_o = s1_data_i;
end end
slave_2: begin slave_2: begin
s2_we_o = m1_we_i; s2_we_o = m2_we_i;
s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s2_data_o = m1_data_i; s2_data_o = m2_data_i;
m1_data_o = s2_data_i; m2_data_o = s2_data_i;
end end
slave_3: begin slave_3: begin
s3_we_o = m1_we_i; s3_we_o = m2_we_i;
s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s3_data_o = m1_data_i; s3_data_o = m2_data_i;
m1_data_o = s3_data_i; m2_data_o = s3_data_i;
end end
slave_4: begin slave_4: begin
s4_we_o = m1_we_i; s4_we_o = m2_we_i;
s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s4_data_o = m1_data_i; s4_data_o = m2_data_i;
m1_data_o = s4_data_i; m2_data_o = s4_data_i;
end end
slave_5: begin slave_5: begin
s5_we_o = m1_we_i; s5_we_o = m2_we_i;
s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s5_data_o = m1_data_i; s5_data_o = m2_data_i;
m1_data_o = s5_data_i; m2_data_o = s5_data_i;
end end
default: begin default: begin
end end
endcase endcase
end end
grant2: begin grant3: begin
case (m2_addr_i[31:28]) case (m3_addr_i[31:28])
slave_0: begin slave_0: begin
s0_we_o = m2_we_i; s0_we_o = m3_we_i;
s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s0_data_o = m2_data_i; s0_data_o = m3_data_i;
m2_data_o = s0_data_i; m3_data_o = s0_data_i;
end end
slave_1: begin slave_1: begin
s1_we_o = m2_we_i; s1_we_o = m3_we_i;
s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s1_data_o = m2_data_i; s1_data_o = m3_data_i;
m2_data_o = s1_data_i; m3_data_o = s1_data_i;
end end
slave_2: begin slave_2: begin
s2_we_o = m2_we_i; s2_we_o = m3_we_i;
s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s2_data_o = m2_data_i; s2_data_o = m3_data_i;
m2_data_o = s2_data_i; m3_data_o = s2_data_i;
end end
slave_3: begin slave_3: begin
s3_we_o = m2_we_i; s3_we_o = m3_we_i;
s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s3_data_o = m2_data_i; s3_data_o = m3_data_i;
m2_data_o = s3_data_i; m3_data_o = s3_data_i;
end end
slave_4: begin slave_4: begin
s4_we_o = m2_we_i; s4_we_o = m3_we_i;
s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s4_data_o = m2_data_i; s4_data_o = m3_data_i;
m2_data_o = s4_data_i; m3_data_o = s4_data_i;
end end
slave_5: begin slave_5: begin
s5_we_o = m2_we_i; s5_we_o = m3_we_i;
s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s5_data_o = m2_data_i; s5_data_o = m3_data_i;
m2_data_o = s5_data_i; m3_data_o = s5_data_i;
end end
default: begin default: begin
end end
endcase endcase
end end
grant3: begin default: begin
case (m3_addr_i[31:28])
slave_0: begin
s0_we_o = m3_we_i;
s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s0_data_o = m3_data_i;
m3_data_o = s0_data_i;
end
slave_1: begin
s1_we_o = m3_we_i;
s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s1_data_o = m3_data_i;
m3_data_o = s1_data_i;
end
slave_2: begin
s2_we_o = m3_we_i;
s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s2_data_o = m3_data_i;
m3_data_o = s2_data_i;
end
slave_3: begin
s3_we_o = m3_we_i;
s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s3_data_o = m3_data_i;
m3_data_o = s3_data_i;
end
slave_4: begin
s4_we_o = m3_we_i;
s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s4_data_o = m3_data_i;
m3_data_o = s4_data_i;
end
slave_5: begin
s5_we_o = m3_we_i;
s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
s5_data_o = m3_data_i;
m3_data_o = s5_data_i;
end
default: begin
end end
endcase endcase
end
default: begin
end
endcase
end
end end
endmodule endmodule

180
rtl/debug/uart_debug.v
View File

@ -58,22 +58,22 @@ module uart_debug(
// 状态 // 状态
localparam S_IDLE = 1; localparam S_IDLE = 14'h0001;
localparam S_INIT_UART_BAUD = 2; localparam S_INIT_UART_BAUD = 14'h0002;
localparam S_CLEAR_UART_RX_OVER_FLAG = 3; localparam S_CLEAR_UART_RX_OVER_FLAG = 14'h0004;
localparam S_WAIT_BYTE = 4; localparam S_WAIT_BYTE = 14'h0008;
localparam S_WAIT_BYTE2 = 5; localparam S_WAIT_BYTE2 = 14'h0010;
localparam S_GET_BYTE = 6; localparam S_GET_BYTE = 14'h0020;
localparam S_REC_FIRST_PACKET = 7; localparam S_REC_FIRST_PACKET = 14'h0040;
localparam S_REC_REMAIN_PACKET = 8; localparam S_REC_REMAIN_PACKET = 14'h0080;
localparam S_SEND_ACK = 9; localparam S_SEND_ACK = 14'h0100;
localparam S_SEND_NAK = 10; localparam S_SEND_NAK = 14'h0200;
localparam S_CRC_START = 11; localparam S_CRC_START = 14'h0400;
localparam S_CRC_CALC = 12; localparam S_CRC_CALC = 14'h0800;
localparam S_CRC_END = 13; localparam S_CRC_END = 14'h1000;
localparam S_WRITE_MEM = 14; localparam S_WRITE_MEM = 14'h2000;
reg[3:0] state; reg[13:0] state;
// 存放串口接收到的数据 // 存放串口接收到的数据
reg[7:0] rx_data[0:131]; reg[7:0] rx_data[0:131];
@ -83,7 +83,10 @@ module uart_debug(
reg[31:0] fw_file_size; reg[31:0] fw_file_size;
reg[31:0] write_mem_addr; reg[31:0] write_mem_addr;
reg[31:0] write_mem_data; reg[31:0] write_mem_data;
reg[7:0] write_mem_byte_index; reg[7:0] write_mem_byte_index0;
reg[7:0] write_mem_byte_index1;
reg[7:0] write_mem_byte_index2;
reg[7:0] write_mem_byte_index3;
reg[15:0] crc_result; reg[15:0] crc_result;
reg[3:0] crc_bit_index; reg[3:0] crc_bit_index;
@ -177,7 +180,7 @@ module uart_debug(
end end
end end
S_WRITE_MEM: begin S_WRITE_MEM: begin
if (write_mem_byte_index == (need_to_rec_bytes + 2)) begin if (write_mem_byte_index0 == (need_to_rec_bytes + 2)) begin
state <= S_SEND_ACK; state <= S_SEND_ACK;
end else begin end else begin
mem_addr_o <= write_mem_addr; mem_addr_o <= write_mem_addr;
@ -262,25 +265,107 @@ module uart_debug(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_addr <= 32'h0; write_mem_addr <= 32'h0;
write_mem_data <= 32'h0;
write_mem_byte_index <= 8'h0;
end else begin end else begin
case (state) case (state)
S_REC_FIRST_PACKET: begin S_REC_FIRST_PACKET: begin
write_mem_addr <= `ROM_START_ADDR; write_mem_addr <= `ROM_START_ADDR;
write_mem_data <= 32'h0;
write_mem_byte_index <= 8'h0;
end end
S_CRC_END: begin S_CRC_END: begin
write_mem_data <= {rx_data[4], rx_data[3], rx_data[2], rx_data[1]};
write_mem_byte_index <= 8'h5;
if (write_mem_addr > 0) if (write_mem_addr > 0)
write_mem_addr <= write_mem_addr - 4; write_mem_addr <= write_mem_addr - 4;
end end
S_WRITE_MEM: begin S_WRITE_MEM: begin
write_mem_addr <= write_mem_addr + 4; write_mem_addr <= write_mem_addr + 4;
write_mem_data <= {rx_data[write_mem_byte_index + 3], rx_data[write_mem_byte_index + 2], rx_data[write_mem_byte_index + 1], rx_data[write_mem_byte_index]}; end
write_mem_byte_index <= write_mem_byte_index + 4; endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_data <= 32'h0;
end else begin
case (state)
S_REC_FIRST_PACKET: begin
write_mem_data <= 32'h0;
end
S_CRC_END: begin
write_mem_data <= {rx_data[4], rx_data[3], rx_data[2], rx_data[1]};
end
S_WRITE_MEM: begin
write_mem_data <= {rx_data[write_mem_byte_index3], rx_data[write_mem_byte_index2], rx_data[write_mem_byte_index1], rx_data[write_mem_byte_index0]};
end
endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_byte_index0 <= 8'h0;
end else begin
case (state)
S_REC_FIRST_PACKET: begin
write_mem_byte_index0 <= 8'h0;
end
S_CRC_END: begin
write_mem_byte_index0 <= 8'h5;
end
S_WRITE_MEM: begin
write_mem_byte_index0 <= write_mem_byte_index0 + 4;
end
endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_byte_index1 <= 8'h0;
end else begin
case (state)
S_REC_FIRST_PACKET: begin
write_mem_byte_index1 <= 8'h0;
end
S_CRC_END: begin
write_mem_byte_index1 <= 8'h6;
end
S_WRITE_MEM: begin
write_mem_byte_index1 <= write_mem_byte_index1 + 4;
end
endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_byte_index2 <= 8'h0;
end else begin
case (state)
S_REC_FIRST_PACKET: begin
write_mem_byte_index2 <= 8'h0;
end
S_CRC_END: begin
write_mem_byte_index2 <= 8'h7;
end
S_WRITE_MEM: begin
write_mem_byte_index2 <= write_mem_byte_index2 + 4;
end
endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
write_mem_byte_index3 <= 8'h0;
end else begin
case (state)
S_REC_FIRST_PACKET: begin
write_mem_byte_index3 <= 8'h0;
end
S_CRC_END: begin
write_mem_byte_index3 <= 8'h8;
end
S_WRITE_MEM: begin
write_mem_byte_index3 <= write_mem_byte_index3 + 4;
end end
endcase endcase
end end
@ -290,30 +375,21 @@ module uart_debug(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin if (rst == 1'b0 || debug_en_i == 1'b0) begin
crc_result <= 16'h0; crc_result <= 16'h0;
crc_bit_index <= 4'h0;
crc_byte_index <= 8'h0;
end else begin end else begin
case (state) case (state)
S_CRC_START: begin S_CRC_START: begin
crc_result <= 16'hffff; crc_result <= 16'hffff;
crc_bit_index <= 4'h0;
crc_byte_index <= 8'h1;
end end
S_CRC_CALC: begin S_CRC_CALC: begin
if (crc_bit_index == 4'h0) begin if (crc_bit_index == 4'h0) begin
crc_result <= crc_result ^ rx_data[crc_byte_index]; crc_result <= crc_result ^ rx_data[crc_byte_index];
crc_byte_index <= crc_byte_index + 1'b1;
crc_bit_index <= crc_bit_index + 1'b1;
end else begin end else begin
if (crc_bit_index < 4'h9) begin if (crc_bit_index < 4'h9) begin
crc_bit_index <= crc_bit_index + 1'b1;
if (crc_result[0] == 1'b1) begin if (crc_result[0] == 1'b1) begin
crc_result <= {1'b0, crc_result[15:1]} ^ 16'ha001; crc_result <= {1'b0, crc_result[15:1]} ^ 16'ha001;
end else begin end else begin
crc_result <= {1'b0, crc_result[15:1]}; crc_result <= {1'b0, crc_result[15:1]};
end end
end else begin
crc_bit_index <= 4'h0;
end end
end end
end end
@ -321,4 +397,40 @@ module uart_debug(
end end
end end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
crc_bit_index <= 4'h0;
end else begin
case (state)
S_CRC_START: begin
crc_bit_index <= 4'h0;
end
S_CRC_CALC: begin
if (crc_bit_index < 4'h9) begin
crc_bit_index <= crc_bit_index + 1'b1;
end else begin
crc_bit_index <= 4'h0;
end
end
endcase
end
end
always @ (posedge clk) begin
if (rst == 1'b0 || debug_en_i == 1'b0) begin
crc_byte_index <= 8'h0;
end else begin
case (state)
S_CRC_START: begin
crc_byte_index <= 8'h1;
end
S_CRC_CALC: begin
if (crc_bit_index == 4'h0) begin
crc_byte_index <= crc_byte_index + 1'b1;
end
end
endcase
end
end
endmodule endmodule