diff --git a/rtl/core/csr_reg.v b/rtl/core/csr_reg.v index 7f0f614..611b23d 100644 --- a/rtl/core/csr_reg.v +++ b/rtl/core/csr_reg.v @@ -47,7 +47,6 @@ module csr_reg( ); - reg[`DoubleRegBus] cycle; reg[`RegBus] mtvec; reg[`RegBus] mcause; @@ -56,14 +55,12 @@ module csr_reg( reg[`RegBus] mstatus; reg[`RegBus] mscratch; - assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False; assign clint_csr_mtvec = mtvec; assign clint_csr_mepc = mepc; assign clint_csr_mstatus = mstatus; - // cycle counter // 复位撤销后就一直计数 always @ (posedge clk) begin @@ -142,84 +139,76 @@ module csr_reg( // read reg // ex模块读CSR寄存器 always @ (*) begin - if (rst == `RstEnable) begin - data_o = `ZeroWord; + if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin + data_o = data_i; end else begin - if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin - data_o = data_i; - end else begin - case (raddr_i[11:0]) - `CSR_CYCLE: begin - data_o = cycle[31:0]; - end - `CSR_CYCLEH: begin - data_o = cycle[63:32]; - end - `CSR_MTVEC: begin - data_o = mtvec; - end - `CSR_MCAUSE: begin - data_o = mcause; - end - `CSR_MEPC: begin - data_o = mepc; - end - `CSR_MIE: begin - data_o = mie; - end - `CSR_MSTATUS: begin - data_o = mstatus; - end - `CSR_MSCRATCH: begin - data_o = mscratch; - end - default: begin - data_o = `ZeroWord; - end - endcase - end + case (raddr_i[11:0]) + `CSR_CYCLE: begin + data_o = cycle[31:0]; + end + `CSR_CYCLEH: begin + data_o = cycle[63:32]; + end + `CSR_MTVEC: begin + data_o = mtvec; + end + `CSR_MCAUSE: begin + data_o = mcause; + end + `CSR_MEPC: begin + data_o = mepc; + end + `CSR_MIE: begin + data_o = mie; + end + `CSR_MSTATUS: begin + data_o = mstatus; + end + `CSR_MSCRATCH: begin + data_o = mscratch; + end + default: begin + data_o = `ZeroWord; + end + endcase end end // read reg // clint模块读CSR寄存器 always @ (*) begin - if (rst == `RstEnable) begin - clint_data_o = `ZeroWord; + if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin + clint_data_o = clint_data_i; end else begin - if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin - clint_data_o = clint_data_i; - end else begin - case (clint_raddr_i[11:0]) - `CSR_CYCLE: begin - clint_data_o = cycle[31:0]; - end - `CSR_CYCLEH: begin - clint_data_o = cycle[63:32]; - end - `CSR_MTVEC: begin - clint_data_o = mtvec; - end - `CSR_MCAUSE: begin - clint_data_o = mcause; - end - `CSR_MEPC: begin - clint_data_o = mepc; - end - `CSR_MIE: begin - clint_data_o = mie; - end - `CSR_MSTATUS: begin - clint_data_o = mstatus; - end - `CSR_MSCRATCH: begin - clint_data_o = mscratch; - end - default: begin - clint_data_o = `ZeroWord; - end - endcase - end + case (clint_raddr_i[11:0]) + `CSR_CYCLE: begin + clint_data_o = cycle[31:0]; + end + `CSR_CYCLEH: begin + clint_data_o = cycle[63:32]; + end + `CSR_MTVEC: begin + clint_data_o = mtvec; + end + `CSR_MCAUSE: begin + clint_data_o = mcause; + end + `CSR_MEPC: begin + clint_data_o = mepc; + end + `CSR_MIE: begin + clint_data_o = mie; + end + `CSR_MSTATUS: begin + clint_data_o = mstatus; + end + `CSR_MSCRATCH: begin + clint_data_o = mscratch; + end + default: begin + clint_data_o = `ZeroWord; + end + endcase end end diff --git a/rtl/core/ctrl.v b/rtl/core/ctrl.v index 4abdc49..f884a4c 100644 --- a/rtl/core/ctrl.v +++ b/rtl/core/ctrl.v @@ -46,28 +46,22 @@ module ctrl( always @ (*) begin - if (rst == `RstEnable) begin - hold_flag_o = `Hold_None; - jump_flag_o = `JumpDisable; - jump_addr_o = `ZeroWord; + jump_addr_o = jump_addr_i; + jump_flag_o = jump_flag_i; + // 默认不暂停 + hold_flag_o = `Hold_None; + // 按优先级处理不同模块的请求 + if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin + // 暂停整条流水线 + hold_flag_o = `Hold_Id; + end else if (hold_flag_rib_i == `HoldEnable) begin + // 暂停PC，即取指地址不变 + hold_flag_o = `Hold_Pc; + end else if (jtag_halt_flag_i == `HoldEnable) begin + // 暂停整条流水线 + hold_flag_o = `Hold_Id; end else begin - jump_addr_o = jump_addr_i; - jump_flag_o = jump_flag_i; - // 默认不暂停 hold_flag_o = `Hold_None; - // 按优先级处理不同模块的请求 - if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin - // 暂停整条流水线 - hold_flag_o = `Hold_Id; - end else if (hold_flag_rib_i == `HoldEnable) begin - // 暂停PC，即取指地址不变 - hold_flag_o = `Hold_Pc; - end else if (jtag_halt_flag_i == `HoldEnable) begin - // 暂停整条流水线 - hold_flag_o = `Hold_Id; - end else begin - hold_flag_o = `Hold_None; - end end end diff --git a/rtl/core/ex.v b/rtl/core/ex.v index f3c7d91..c02f8be 100644 --- a/rtl/core/ex.v +++ b/rtl/core/ex.v @@ -170,94 +170,75 @@ module ex( // 处理乘法指令 always @ (*) begin - if (rst == `RstEnable) begin - mul_op1 = `ZeroWord; - mul_op2 = `ZeroWord; + if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin + case (funct3) + `INST_MUL, `INST_MULHU: begin + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; + end + `INST_MULHSU: begin + mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i; + mul_op2 = reg2_rdata_i; + end + `INST_MULH: begin + mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i; + mul_op2 = (reg2_rdata_i[31] == 1'b1)? (reg2_data_invert): reg2_rdata_i; + end + default: begin + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; + end + endcase end else begin - if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin - case (funct3) - `INST_MUL, `INST_MULHU: begin - mul_op1 = reg1_rdata_i; - mul_op2 = reg2_rdata_i; - end - `INST_MULHSU: begin - mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i; - mul_op2 = reg2_rdata_i; - end - `INST_MULH: begin - mul_op1 = (reg1_rdata_i[31] == 1'b1)? (reg1_data_invert): reg1_rdata_i; - mul_op2 = (reg2_rdata_i[31] == 1'b1)? (reg2_data_invert): reg2_rdata_i; - end - default: begin - mul_op1 = reg1_rdata_i; - mul_op2 = reg2_rdata_i; - end - endcase - end else begin - mul_op1 = reg1_rdata_i; - mul_op2 = reg2_rdata_i; - end + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; end end // 处理除法指令 always @ (*) begin - if (rst == `RstEnable) begin - div_dividend_o = `ZeroWord; - div_divisor_o = `ZeroWord; - div_op_o = 3'b0; - div_reg_waddr_o = `ZeroWord; - div_waddr = `ZeroWord; - div_hold_flag = `HoldDisable; + div_dividend_o = reg1_rdata_i; + div_divisor_o = reg2_rdata_i; + div_op_o = funct3; + div_reg_waddr_o = reg_waddr_i; + if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin div_we = `WriteDisable; div_wdata = `ZeroWord; - div_start = `DivStop; + div_waddr = `ZeroWord; + case (funct3) + `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin + div_start = `DivStart; + div_jump_flag = `JumpEnable; + div_hold_flag = `HoldEnable; + div_jump_addr = op1_jump_add_op2_jump_res; + end + default: begin + div_start = `DivStop; + div_jump_flag = `JumpDisable; + div_hold_flag = `HoldDisable; + div_jump_addr = `ZeroWord; + end + endcase + end else begin div_jump_flag = `JumpDisable; div_jump_addr = `ZeroWord; - end else begin - div_dividend_o = reg1_rdata_i; - div_divisor_o = reg2_rdata_i; - div_op_o = funct3; - div_reg_waddr_o = reg_waddr_i; - if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin + if (div_busy_i == `True) begin + div_start = `DivStart; div_we = `WriteDisable; div_wdata = `ZeroWord; div_waddr = `ZeroWord; - case (funct3) - `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin - div_start = `DivStart; - div_jump_flag = `JumpEnable; - div_hold_flag = `HoldEnable; - div_jump_addr = op1_jump_add_op2_jump_res; - end - default: begin - div_start = `DivStop; - div_jump_flag = `JumpDisable; - div_hold_flag = `HoldDisable; - div_jump_addr = `ZeroWord; - end - endcase + div_hold_flag = `HoldEnable; end else begin - div_jump_flag = `JumpDisable; - div_jump_addr = `ZeroWord; - if (div_busy_i == `True) begin - div_start = `DivStart; + div_start = `DivStop; + div_hold_flag = `HoldDisable; + if (div_ready_i == `DivResultReady) begin + div_wdata = div_result_i; + div_waddr = div_reg_waddr_i; + div_we = `WriteEnable; + end else begin div_we = `WriteDisable; div_wdata = `ZeroWord; div_waddr = `ZeroWord; - div_hold_flag = `HoldEnable; - end else begin - div_start = `DivStop; - div_hold_flag = `HoldDisable; - if (div_ready_i == `DivResultReady) begin - div_wdata = div_result_i; - div_waddr = div_reg_waddr_i; - div_we = `WriteEnable; - end else begin - div_we = `WriteDisable; - div_wdata = `ZeroWord; - div_waddr = `ZeroWord; - end end end end @@ -265,297 +246,99 @@ module ex( // 执行 always @ (*) begin - if (rst == `RstEnable) begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - mem_req = `RIB_NREQ; - reg_wdata = `ZeroWord; - reg_we = `WriteDisable; - reg_waddr = `ZeroReg; - csr_wdata_o = `ZeroWord; - end else begin - reg_we = reg_we_i; - reg_waddr = reg_waddr_i; - mem_req = `RIB_NREQ; - csr_wdata_o = `ZeroWord; + reg_we = reg_we_i; + reg_waddr = reg_waddr_i; + mem_req = `RIB_NREQ; + csr_wdata_o = `ZeroWord; - case (opcode) - `INST_TYPE_I: begin - case (funct3) - `INST_ADDI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_add_op2_res; + case (opcode) + `INST_TYPE_I: begin + case (funct3) + `INST_ADDI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_add_op2_res; + end + `INST_SLTI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1; + end + `INST_SLTIU: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1; + end + `INST_XORI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i ^ op2_i; + end + `INST_ORI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i | op2_i; + end + `INST_ANDI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i & op2_i; + end + `INST_SLLI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i << inst_i[24:20]; + end + `INST_SRI: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + if (inst_i[30] == 1'b1) begin + reg_wdata = (sri_shift & sri_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sri_shift_mask)); + end else begin + reg_wdata = reg1_rdata_i >> inst_i[24:20]; end - `INST_SLTI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1; - end - `INST_SLTIU: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1; - end - `INST_XORI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i ^ op2_i; - end - `INST_ORI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i | op2_i; - end - `INST_ANDI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i & op2_i; - end - `INST_SLLI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = reg1_rdata_i << inst_i[24:20]; - end - `INST_SRI: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - if (inst_i[30] == 1'b1) begin - reg_wdata = (sri_shift & sri_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sri_shift_mask)); - end else begin - reg_wdata = reg1_rdata_i >> inst_i[24:20]; - end - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end - `INST_TYPE_R_M: begin - if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin - case (funct3) - `INST_ADD_SUB: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - if (inst_i[30] == 1'b0) begin - reg_wdata = op1_add_op2_res; - end else begin - reg_wdata = op1_i - op2_i; - end - end - `INST_SLL: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i << op2_i[4:0]; - end - `INST_SLT: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1; - end - `INST_SLTU: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1; - end - `INST_XOR: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i ^ op2_i; - end - `INST_SR: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - if (inst_i[30] == 1'b1) begin - reg_wdata = (sr_shift & sr_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sr_shift_mask)); - end else begin - reg_wdata = reg1_rdata_i >> reg2_rdata_i[4:0]; - end - end - `INST_OR: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i | op2_i; - end - `INST_AND: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = op1_i & op2_i; - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end else if (funct7 == 7'b0000001) begin - case (funct3) - `INST_MUL: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = mul_temp[31:0]; - end - `INST_MULHU: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = mul_temp[63:32]; - end - `INST_MULH: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - case ({reg1_rdata_i[31], reg2_rdata_i[31]}) - 2'b00: begin - reg_wdata = mul_temp[63:32]; - end - 2'b11: begin - reg_wdata = mul_temp[63:32]; - end - 2'b10: begin - reg_wdata = mul_temp_invert[63:32]; - end - default: begin - reg_wdata = mul_temp_invert[63:32]; - end - endcase - end - `INST_MULHSU: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - if (reg1_rdata_i[31] == 1'b1) begin - reg_wdata = mul_temp_invert[63:32]; - end else begin - reg_wdata = mul_temp[63:32]; - end - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end else begin + end + default: begin jump_flag = `JumpDisable; hold_flag = `HoldDisable; jump_addr = `ZeroWord; @@ -565,96 +348,167 @@ module ex( mem_we = `WriteDisable; reg_wdata = `ZeroWord; end - end - `INST_TYPE_L: begin + endcase + end + `INST_TYPE_R_M: begin + if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin case (funct3) - `INST_LB: begin + `INST_ADD_SUB: begin jump_flag = `JumpDisable; hold_flag = `HoldDisable; jump_addr = `ZeroWord; mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; mem_waddr_o = `ZeroWord; mem_we = `WriteDisable; - mem_req = `RIB_REQ; - mem_raddr_o = op1_add_op2_res; - case (mem_raddr_index) - 2'b00: begin - reg_wdata = {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; - end - 2'b01: begin - reg_wdata = {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]}; - end - 2'b10: begin - reg_wdata = {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]}; - end - default: begin - reg_wdata = {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]}; - end - endcase - end - `INST_LH: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - mem_req = `RIB_REQ; - mem_raddr_o = op1_add_op2_res; - if (mem_raddr_index == 2'b0) begin - reg_wdata = {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; + if (inst_i[30] == 1'b0) begin + reg_wdata = op1_add_op2_res; end else begin - reg_wdata = {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]}; + reg_wdata = op1_i - op2_i; end end - `INST_LW: begin + `INST_SLL: begin jump_flag = `JumpDisable; hold_flag = `HoldDisable; jump_addr = `ZeroWord; mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; mem_waddr_o = `ZeroWord; mem_we = `WriteDisable; - mem_req = `RIB_REQ; - mem_raddr_o = op1_add_op2_res; - reg_wdata = mem_rdata_i; + reg_wdata = op1_i << op2_i[4:0]; end - `INST_LBU: begin + `INST_SLT: begin jump_flag = `JumpDisable; hold_flag = `HoldDisable; jump_addr = `ZeroWord; mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; mem_waddr_o = `ZeroWord; mem_we = `WriteDisable; - mem_req = `RIB_REQ; - mem_raddr_o = op1_add_op2_res; - case (mem_raddr_index) + reg_wdata = {32{(~op1_ge_op2_signed)}} & 32'h1; + end + `INST_SLTU: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = {32{(~op1_ge_op2_unsigned)}} & 32'h1; + end + `INST_XOR: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i ^ op2_i; + end + `INST_SR: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + if (inst_i[30] == 1'b1) begin + reg_wdata = (sr_shift & sr_shift_mask) | ({32{reg1_rdata_i[31]}} & (~sr_shift_mask)); + end else begin + reg_wdata = reg1_rdata_i >> reg2_rdata_i[4:0]; + end + end + `INST_OR: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i | op2_i; + end + `INST_AND: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = op1_i & op2_i; + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase + end else if (funct7 == 7'b0000001) begin + case (funct3) + `INST_MUL: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = mul_temp[31:0]; + end + `INST_MULHU: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = mul_temp[63:32]; + end + `INST_MULH: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) 2'b00: begin - reg_wdata = {24'h0, mem_rdata_i[7:0]}; + reg_wdata = mul_temp[63:32]; end - 2'b01: begin - reg_wdata = {24'h0, mem_rdata_i[15:8]}; + 2'b11: begin + reg_wdata = mul_temp[63:32]; end 2'b10: begin - reg_wdata = {24'h0, mem_rdata_i[23:16]}; + reg_wdata = mul_temp_invert[63:32]; end default: begin - reg_wdata = {24'h0, mem_rdata_i[31:24]}; + reg_wdata = mul_temp_invert[63:32]; end endcase end - `INST_LHU: begin + `INST_MULHSU: begin jump_flag = `JumpDisable; hold_flag = `HoldDisable; jump_addr = `ZeroWord; mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; mem_waddr_o = `ZeroWord; mem_we = `WriteDisable; - mem_req = `RIB_REQ; - mem_raddr_o = op1_add_op2_res; - if (mem_raddr_index == 2'b0) begin - reg_wdata = {16'h0, mem_rdata_i[15:0]}; + if (reg1_rdata_i[31] == 1'b1) begin + reg_wdata = mul_temp_invert[63:32]; end else begin - reg_wdata = {16'h0, mem_rdata_i[31:16]}; + reg_wdata = mul_temp[63:32]; end end default: begin @@ -668,242 +522,354 @@ module ex( reg_wdata = `ZeroWord; end endcase + end else begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end - `INST_TYPE_S: begin - case (funct3) - `INST_SB: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - reg_wdata = `ZeroWord; - mem_we = `WriteEnable; - mem_req = `RIB_REQ; - mem_waddr_o = op1_add_op2_res; - mem_raddr_o = op1_add_op2_res; - case (mem_waddr_index) - 2'b00: begin - mem_wdata_o = {mem_rdata_i[31:8], reg2_rdata_i[7:0]}; - end - 2'b01: begin - mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]}; - end - 2'b10: begin - mem_wdata_o = {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]}; - end - default: begin - mem_wdata_o = {reg2_rdata_i[7:0], mem_rdata_i[23:0]}; - end - endcase - end - `INST_SH: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - reg_wdata = `ZeroWord; - mem_we = `WriteEnable; - mem_req = `RIB_REQ; - mem_waddr_o = op1_add_op2_res; - mem_raddr_o = op1_add_op2_res; - if (mem_waddr_index == 2'b00) begin - mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[15:0]}; - end else begin - mem_wdata_o = {reg2_rdata_i[15:0], mem_rdata_i[15:0]}; + end + `INST_TYPE_L: begin + case (funct3) + `INST_LB: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_REQ; + mem_raddr_o = op1_add_op2_res; + case (mem_raddr_index) + 2'b00: begin + reg_wdata = {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; end + 2'b01: begin + reg_wdata = {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]}; + end + 2'b10: begin + reg_wdata = {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]}; + end + default: begin + reg_wdata = {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]}; + end + endcase + end + `INST_LH: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_REQ; + mem_raddr_o = op1_add_op2_res; + if (mem_raddr_index == 2'b0) begin + reg_wdata = {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; + end else begin + reg_wdata = {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]}; end - `INST_SW: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - reg_wdata = `ZeroWord; - mem_we = `WriteEnable; - mem_req = `RIB_REQ; - mem_waddr_o = op1_add_op2_res; - mem_raddr_o = op1_add_op2_res; - mem_wdata_o = reg2_rdata_i; + end + `INST_LW: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_REQ; + mem_raddr_o = op1_add_op2_res; + reg_wdata = mem_rdata_i; + end + `INST_LBU: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_REQ; + mem_raddr_o = op1_add_op2_res; + case (mem_raddr_index) + 2'b00: begin + reg_wdata = {24'h0, mem_rdata_i[7:0]}; + end + 2'b01: begin + reg_wdata = {24'h0, mem_rdata_i[15:8]}; + end + 2'b10: begin + reg_wdata = {24'h0, mem_rdata_i[23:16]}; + end + default: begin + reg_wdata = {24'h0, mem_rdata_i[31:24]}; + end + endcase + end + `INST_LHU: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_REQ; + mem_raddr_o = op1_add_op2_res; + if (mem_raddr_index == 2'b0) begin + reg_wdata = {16'h0, mem_rdata_i[15:0]}; + end else begin + reg_wdata = {16'h0, mem_rdata_i[31:16]}; end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase + end + `INST_TYPE_S: begin + case (funct3) + `INST_SB: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = op1_add_op2_res; + mem_raddr_o = op1_add_op2_res; + case (mem_waddr_index) + 2'b00: begin + mem_wdata_o = {mem_rdata_i[31:8], reg2_rdata_i[7:0]}; + end + 2'b01: begin + mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]}; + end + 2'b10: begin + mem_wdata_o = {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]}; + end + default: begin + mem_wdata_o = {reg2_rdata_i[7:0], mem_rdata_i[23:0]}; + end + endcase + end + `INST_SH: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = op1_add_op2_res; + mem_raddr_o = op1_add_op2_res; + if (mem_waddr_index == 2'b00) begin + mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[15:0]}; + end else begin + mem_wdata_o = {reg2_rdata_i[15:0], mem_rdata_i[15:0]}; end - endcase - end - `INST_TYPE_B: begin - case (funct3) - `INST_BEQ: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = op1_eq_op2 & `JumpEnable; - jump_addr = {32{op1_eq_op2}} & op1_jump_add_op2_jump_res; - end - `INST_BNE: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = (~op1_eq_op2) & `JumpEnable; - jump_addr = {32{(~op1_eq_op2)}} & op1_jump_add_op2_jump_res; - end - `INST_BLT: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = (~op1_ge_op2_signed) & `JumpEnable; - jump_addr = {32{(~op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res; - end - `INST_BGE: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = (op1_ge_op2_signed) & `JumpEnable; - jump_addr = {32{(op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res; - end - `INST_BLTU: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = (~op1_ge_op2_unsigned) & `JumpEnable; - jump_addr = {32{(~op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res; - end - `INST_BGEU: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = (op1_ge_op2_unsigned) & `JumpEnable; - jump_addr = {32{(op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res; - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end - `INST_JAL, `INST_JALR: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - jump_flag = `JumpEnable; - jump_addr = op1_jump_add_op2_jump_res; - reg_wdata = op1_add_op2_res; - end - `INST_LUI, `INST_AUIPC: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - jump_addr = `ZeroWord; - jump_flag = `JumpDisable; - reg_wdata = op1_add_op2_res; - end - `INST_NOP_OP: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - `INST_FENCE: begin - hold_flag = `HoldDisable; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - jump_flag = `JumpEnable; - jump_addr = op1_jump_add_op2_jump_res; - end - `INST_CSR: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - case (funct3) - `INST_CSRRW: begin - csr_wdata_o = reg1_rdata_i; - reg_wdata = csr_rdata_i; - end - `INST_CSRRS: begin - csr_wdata_o = reg1_rdata_i | csr_rdata_i; - reg_wdata = csr_rdata_i; - end - `INST_CSRRC: begin - csr_wdata_o = csr_rdata_i & (~reg1_rdata_i); - reg_wdata = csr_rdata_i; - end - `INST_CSRRWI: begin - csr_wdata_o = {27'h0, uimm}; - reg_wdata = csr_rdata_i; - end - `INST_CSRRSI: begin - csr_wdata_o = {27'h0, uimm} | csr_rdata_i; - reg_wdata = csr_rdata_i; - end - `INST_CSRRCI: begin - csr_wdata_o = (~{27'h0, uimm}) & csr_rdata_i; - reg_wdata = csr_rdata_i; - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end - default: begin - jump_flag = `JumpDisable; - hold_flag = `HoldDisable; - jump_addr = `ZeroWord; - mem_wdata_o = `ZeroWord; - mem_raddr_o = `ZeroWord; - mem_waddr_o = `ZeroWord; - mem_we = `WriteDisable; - reg_wdata = `ZeroWord; - end - endcase - end + end + `INST_SW: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = op1_add_op2_res; + mem_raddr_o = op1_add_op2_res; + mem_wdata_o = reg2_rdata_i; + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase + end + `INST_TYPE_B: begin + case (funct3) + `INST_BEQ: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = op1_eq_op2 & `JumpEnable; + jump_addr = {32{op1_eq_op2}} & op1_jump_add_op2_jump_res; + end + `INST_BNE: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = (~op1_eq_op2) & `JumpEnable; + jump_addr = {32{(~op1_eq_op2)}} & op1_jump_add_op2_jump_res; + end + `INST_BLT: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = (~op1_ge_op2_signed) & `JumpEnable; + jump_addr = {32{(~op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res; + end + `INST_BGE: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = (op1_ge_op2_signed) & `JumpEnable; + jump_addr = {32{(op1_ge_op2_signed)}} & op1_jump_add_op2_jump_res; + end + `INST_BLTU: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = (~op1_ge_op2_unsigned) & `JumpEnable; + jump_addr = {32{(~op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res; + end + `INST_BGEU: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = (op1_ge_op2_unsigned) & `JumpEnable; + jump_addr = {32{(op1_ge_op2_unsigned)}} & op1_jump_add_op2_jump_res; + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase + end + `INST_JAL, `INST_JALR: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_flag = `JumpEnable; + jump_addr = op1_jump_add_op2_jump_res; + reg_wdata = op1_add_op2_res; + end + `INST_LUI, `INST_AUIPC: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_addr = `ZeroWord; + jump_flag = `JumpDisable; + reg_wdata = op1_add_op2_res; + end + `INST_NOP_OP: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + `INST_FENCE: begin + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = `JumpEnable; + jump_addr = op1_jump_add_op2_jump_res; + end + `INST_CSR: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case (funct3) + `INST_CSRRW: begin + csr_wdata_o = reg1_rdata_i; + reg_wdata = csr_rdata_i; + end + `INST_CSRRS: begin + csr_wdata_o = reg1_rdata_i | csr_rdata_i; + reg_wdata = csr_rdata_i; + end + `INST_CSRRC: begin + csr_wdata_o = csr_rdata_i & (~reg1_rdata_i); + reg_wdata = csr_rdata_i; + end + `INST_CSRRWI: begin + csr_wdata_o = {27'h0, uimm}; + reg_wdata = csr_rdata_i; + end + `INST_CSRRSI: begin + csr_wdata_o = {27'h0, uimm} | csr_rdata_i; + reg_wdata = csr_rdata_i; + end + `INST_CSRRCI: begin + csr_wdata_o = (~{27'h0, uimm}) & csr_rdata_i; + reg_wdata = csr_rdata_i; + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase + end + default: begin + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + end + endcase end endmodule diff --git a/rtl/core/id.v b/rtl/core/id.v index 6e5f00d..84f879a 100644 --- a/rtl/core/id.v +++ b/rtl/core/id.v @@ -69,253 +69,234 @@ module id( always @ (*) begin - if (rst == `RstEnable) begin - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - csr_raddr_o = `ZeroWord; - inst_o = `INST_NOP; - inst_addr_o = `ZeroWord; - reg1_rdata_o = `ZeroWord; - reg2_rdata_o = `ZeroWord; - csr_rdata_o = `ZeroWord; - reg_we_o = `WriteDisable; - csr_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - csr_waddr_o = `ZeroWord; - op1_o = `ZeroWord; - op2_o = `ZeroWord; - op1_jump_o = `ZeroWord; - op2_jump_o = `ZeroWord; - end else begin - inst_o = inst_i; - inst_addr_o = inst_addr_i; - reg1_rdata_o = reg1_rdata_i; - reg2_rdata_o = reg2_rdata_i; - csr_rdata_o = csr_rdata_i; - csr_raddr_o = `ZeroWord; - csr_waddr_o = `ZeroWord; - csr_we_o = `WriteDisable; - op1_o = `ZeroWord; - op2_o = `ZeroWord; - op1_jump_o = `ZeroWord; - op2_jump_o = `ZeroWord; + inst_o = inst_i; + inst_addr_o = inst_addr_i; + reg1_rdata_o = reg1_rdata_i; + reg2_rdata_o = reg2_rdata_i; + csr_rdata_o = csr_rdata_i; + csr_raddr_o = `ZeroWord; + csr_waddr_o = `ZeroWord; + csr_we_o = `WriteDisable; + op1_o = `ZeroWord; + op2_o = `ZeroWord; + op1_jump_o = `ZeroWord; + op2_jump_o = `ZeroWord; - case (opcode) - `INST_TYPE_I: begin - case (funct3) - `INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = rs1; - reg2_raddr_o = `ZeroReg; - op1_o = reg1_rdata_i; - op2_o = {{20{inst_i[31]}}, inst_i[31:20]}; - end - default: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - end - endcase - end - `INST_TYPE_R_M: begin - if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin - case (funct3) - `INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = rs1; - reg2_raddr_o = rs2; - op1_o = reg1_rdata_i; - op2_o = reg2_rdata_i; - end - default: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - end - endcase - end else if (funct7 == 7'b0000001) begin - case (funct3) - `INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = rs1; - reg2_raddr_o = rs2; - op1_o = reg1_rdata_i; - op2_o = reg2_rdata_i; - end - `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin - reg_we_o = `WriteDisable; - reg_waddr_o = rd; - reg1_raddr_o = rs1; - reg2_raddr_o = rs2; - op1_o = reg1_rdata_i; - op2_o = reg2_rdata_i; - op1_jump_o = inst_addr_i; - op2_jump_o = 32'h4; - end - default: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - end - endcase - end else begin + case (opcode) + `INST_TYPE_I: begin + case (funct3) + `INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + op1_o = reg1_rdata_i; + op2_o = {{20{inst_i[31]}}, inst_i[31:20]}; + end + default: begin reg_we_o = `WriteDisable; reg_waddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg; end - end - `INST_TYPE_L: begin + endcase + end + `INST_TYPE_R_M: begin + if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin case (funct3) - `INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin - reg1_raddr_o = rs1; - reg2_raddr_o = `ZeroReg; + `INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin reg_we_o = `WriteEnable; reg_waddr_o = rd; - op1_o = reg1_rdata_i; - op2_o = {{20{inst_i[31]}}, inst_i[31:20]}; - end - default: begin - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - end - endcase - end - `INST_TYPE_S: begin - case (funct3) - `INST_SB, `INST_SW, `INST_SH: begin reg1_raddr_o = rs1; reg2_raddr_o = rs2; - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; op1_o = reg1_rdata_i; - op2_o = {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + op2_o = reg2_rdata_i; end default: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg; - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; end endcase - end - `INST_TYPE_B: begin + end else if (funct7 == 7'b0000001) begin case (funct3) - `INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin + `INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; reg1_raddr_o = rs1; reg2_raddr_o = rs2; + op1_o = reg1_rdata_i; + op2_o = reg2_rdata_i; + end + `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; op1_o = reg1_rdata_i; op2_o = reg2_rdata_i; op1_jump_o = inst_addr_i; - op2_jump_o = {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; - end - default: begin - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - end - endcase - end - `INST_JAL: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - op1_o = inst_addr_i; - op2_o = 32'h4; - op1_jump_o = inst_addr_i; - op2_jump_o = {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; - end - `INST_JALR: begin - reg_we_o = `WriteEnable; - reg1_raddr_o = rs1; - reg2_raddr_o = `ZeroReg; - reg_waddr_o = rd; - op1_o = inst_addr_i; - op2_o = 32'h4; - op1_jump_o = reg1_rdata_i; - op2_jump_o = {{20{inst_i[31]}}, inst_i[31:20]}; - end - `INST_LUI: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - op1_o = {inst_i[31:12], 12'b0}; - op2_o = `ZeroWord; - end - `INST_AUIPC: begin - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - op1_o = inst_addr_i; - op2_o = {inst_i[31:12], 12'b0}; - end - `INST_NOP_OP: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - end - `INST_FENCE: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - op1_jump_o = inst_addr_i; - op2_jump_o = 32'h4; - end - `INST_CSR: begin - reg_we_o = `WriteDisable; - reg_waddr_o = `ZeroReg; - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - csr_raddr_o = {20'h0, inst_i[31:20]}; - csr_waddr_o = {20'h0, inst_i[31:20]}; - case (funct3) - `INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin - reg1_raddr_o = rs1; - reg2_raddr_o = `ZeroReg; - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - csr_we_o = `WriteEnable; - end - `INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin - reg1_raddr_o = `ZeroReg; - reg2_raddr_o = `ZeroReg; - reg_we_o = `WriteEnable; - reg_waddr_o = rd; - csr_we_o = `WriteEnable; + op2_jump_o = 32'h4; end default: begin reg_we_o = `WriteDisable; reg_waddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg; - csr_we_o = `WriteDisable; end endcase - end - default: begin + end else begin reg_we_o = `WriteDisable; reg_waddr_o = `ZeroReg; reg1_raddr_o = `ZeroReg; reg2_raddr_o = `ZeroReg; end - endcase - end + end + `INST_TYPE_L: begin + case (funct3) + `INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + op1_o = reg1_rdata_i; + op2_o = {{20{inst_i[31]}}, inst_i[31:20]}; + end + default: begin + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + end + endcase + end + `INST_TYPE_S: begin + case (funct3) + `INST_SB, `INST_SW, `INST_SH: begin + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + op1_o = reg1_rdata_i; + op2_o = {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + end + default: begin + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + end + endcase + end + `INST_TYPE_B: begin + case (funct3) + `INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + op1_o = reg1_rdata_i; + op2_o = reg2_rdata_i; + op1_jump_o = inst_addr_i; + op2_jump_o = {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + default: begin + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + end + endcase + end + `INST_JAL: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + op1_o = inst_addr_i; + op2_o = 32'h4; + op1_jump_o = inst_addr_i; + op2_jump_o = {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; + end + `INST_JALR: begin + reg_we_o = `WriteEnable; + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_waddr_o = rd; + op1_o = inst_addr_i; + op2_o = 32'h4; + op1_jump_o = reg1_rdata_i; + op2_jump_o = {{20{inst_i[31]}}, inst_i[31:20]}; + end + `INST_LUI: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + op1_o = {inst_i[31:12], 12'b0}; + op2_o = `ZeroWord; + end + `INST_AUIPC: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + op1_o = inst_addr_i; + op2_o = {inst_i[31:12], 12'b0}; + end + `INST_NOP_OP: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + end + `INST_FENCE: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + op1_jump_o = inst_addr_i; + op2_jump_o = 32'h4; + end + `INST_CSR: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + csr_raddr_o = {20'h0, inst_i[31:20]}; + csr_waddr_o = {20'h0, inst_i[31:20]}; + case (funct3) + `INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + csr_we_o = `WriteEnable; + end + `INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + csr_we_o = `WriteEnable; + end + default: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + csr_we_o = `WriteDisable; + end + endcase + end + default: begin + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + end + endcase end endmodule diff --git a/rtl/core/id_ex.v b/rtl/core/id_ex.v index 5651b17..fa45fb6 100644 --- a/rtl/core/id_ex.v +++ b/rtl/core/id_ex.v @@ -38,69 +38,74 @@ module id_ex( input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志 - output reg[`MemAddrBus] op1_o, - output reg[`MemAddrBus] op2_o, - output reg[`MemAddrBus] op1_jump_o, - output reg[`MemAddrBus] op2_jump_o, - output reg[`InstBus] inst_o, // 指令内容 - output reg[`InstAddrBus] inst_addr_o, // 指令地址 - output reg reg_we_o, // 写通用寄存器标志 - output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址 - output reg[`RegBus] reg1_rdata_o, // 通用寄存器1读数据 - output reg[`RegBus] reg2_rdata_o, // 通用寄存器2读数据 - output reg csr_we_o, // 写CSR寄存器标志 - output reg[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址 - output reg[`RegBus] csr_rdata_o // CSR寄存器读数据 + output wire[`MemAddrBus] op1_o, + output wire[`MemAddrBus] op2_o, + output wire[`MemAddrBus] op1_jump_o, + output wire[`MemAddrBus] op2_jump_o, + output wire[`InstBus] inst_o, // 指令内容 + output wire[`InstAddrBus] inst_addr_o, // 指令地址 + output wire reg_we_o, // 写通用寄存器标志 + output wire[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址 + output wire[`RegBus] reg1_rdata_o, // 通用寄存器1读数据 + output wire[`RegBus] reg2_rdata_o, // 通用寄存器2读数据 + output wire csr_we_o, // 写CSR寄存器标志 + output wire[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址 + output wire[`RegBus] csr_rdata_o // CSR寄存器读数据 ); - always @ (posedge clk) begin - if (rst == `RstEnable) begin - inst_o <= `INST_NOP; - inst_addr_o <= `ZeroWord; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroWord; - reg1_rdata_o <= `ZeroWord; - reg2_rdata_o <= `ZeroWord; - csr_we_o <= `WriteDisable; - csr_waddr_o <= `ZeroWord; - csr_rdata_o <= `ZeroWord; - op1_o <= `ZeroWord; - op2_o <= `ZeroWord; - op1_jump_o <= `ZeroWord; - op2_jump_o <= `ZeroWord; - end else begin - // 流水线暂停时传递默认值 - if (hold_flag_i >= `Hold_Id) begin - inst_o <= `INST_NOP; - inst_addr_o <= inst_addr_i; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroWord; - reg1_rdata_o <= `ZeroWord; - reg2_rdata_o <= `ZeroWord; - csr_we_o <= `WriteDisable; - csr_waddr_o <= `ZeroWord; - csr_rdata_o <= `ZeroWord; - op1_o <= `ZeroWord; - op2_o <= `ZeroWord; - op1_jump_o <= `ZeroWord; - op2_jump_o <= `ZeroWord; - end else begin - inst_o <= inst_i; - inst_addr_o <= inst_addr_i; - reg_we_o <= reg_we_i; - reg_waddr_o <= reg_waddr_i; - reg1_rdata_o <= reg1_rdata_i; - reg2_rdata_o <= reg2_rdata_i; - csr_we_o <= csr_we_i; - csr_waddr_o <= csr_waddr_i; - csr_rdata_o <= csr_rdata_i; - op1_o <= op1_i; - op2_o <= op2_i; - op1_jump_o <= op1_jump_i; - op2_jump_o <= op2_jump_i; - end - end - end + wire hold_en = (hold_flag_i >= `Hold_Id); + + wire[`InstBus] inst; + gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst); + assign inst_o = inst; + + wire[`InstAddrBus] inst_addr; + gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr); + assign inst_addr_o = inst_addr; + + wire reg_we; + gen_pipe_dff #(1) reg_we_ff(clk, rst, hold_en, `WriteDisable, reg_we_i, reg_we); + assign reg_we_o = reg_we; + + wire[`RegAddrBus] reg_waddr; + gen_pipe_dff #(5) reg_waddr_ff(clk, rst, hold_en, `ZeroReg, reg_waddr_i, reg_waddr); + assign reg_waddr_o = reg_waddr; + + wire[`RegBus] reg1_rdata; + gen_pipe_dff #(32) reg1_rdata_ff(clk, rst, hold_en, `ZeroWord, reg1_rdata_i, reg1_rdata); + assign reg1_rdata_o = reg1_rdata; + + wire[`RegBus] reg2_rdata; + gen_pipe_dff #(32) reg2_rdata_ff(clk, rst, hold_en, `ZeroWord, reg2_rdata_i, reg2_rdata); + assign reg2_rdata_o = reg2_rdata; + + wire csr_we; + gen_pipe_dff #(1) csr_we_ff(clk, rst, hold_en, `WriteDisable, csr_we_i, csr_we); + assign csr_we_o = csr_we; + + wire[`MemAddrBus] csr_waddr; + gen_pipe_dff #(32) csr_waddr_ff(clk, rst, hold_en, `ZeroWord, csr_waddr_i, csr_waddr); + assign csr_waddr_o = csr_waddr; + + wire[`RegBus] csr_rdata; + gen_pipe_dff #(32) csr_rdata_ff(clk, rst, hold_en, `ZeroWord, csr_rdata_i, csr_rdata); + assign csr_rdata_o = csr_rdata; + + wire[`MemAddrBus] op1; + gen_pipe_dff #(32) op1_ff(clk, rst, hold_en, `ZeroWord, op1_i, op1); + assign op1_o = op1; + + wire[`MemAddrBus] op2; + gen_pipe_dff #(32) op2_ff(clk, rst, hold_en, `ZeroWord, op2_i, op2); + assign op2_o = op2; + + wire[`MemAddrBus] op1_jump; + gen_pipe_dff #(32) op1_jump_ff(clk, rst, hold_en, `ZeroWord, op1_jump_i, op1_jump); + assign op1_jump_o = op1_jump; + + wire[`MemAddrBus] op2_jump; + gen_pipe_dff #(32) op2_jump_ff(clk, rst, hold_en, `ZeroWord, op2_jump_i, op2_jump); + assign op2_jump_o = op2_jump; endmodule diff --git a/rtl/core/if_id.v b/rtl/core/if_id.v index 2cf4601..238f7b1 100644 --- a/rtl/core/if_id.v +++ b/rtl/core/if_id.v @@ -28,28 +28,25 @@ module if_id( input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志 input wire[`INT_BUS] int_flag_i, // 外设中断输入信号 - output reg[`INT_BUS] int_flag_o, + output wire[`INT_BUS] int_flag_o, - output reg[`InstBus] inst_o, // 指令内容 - output reg[`InstAddrBus] inst_addr_o // 指令地址 + output wire[`InstBus] inst_o, // 指令内容 + output wire[`InstAddrBus] inst_addr_o // 指令地址 ); - always @ (posedge clk) begin - if (rst == `RstEnable) begin - inst_o <= `INST_NOP; - inst_addr_o <= `ZeroWord; - int_flag_o <= `INT_NONE; - // 流水线暂停时传递默认值 - end else if (hold_flag_i >= `Hold_If) begin - inst_o <= `INST_NOP; - inst_addr_o <= inst_addr_i; - int_flag_o <= `INT_NONE; - end else begin - inst_o <= inst_i; - inst_addr_o <= inst_addr_i; - int_flag_o <= int_flag_i; - end - end + wire hold_en = (hold_flag_i >= `Hold_If); + + wire[`InstBus] inst; + gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst); + assign inst_o = inst; + + wire[`InstAddrBus] inst_addr; + gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr); + assign inst_addr_o = inst_addr; + + wire[`INT_BUS] int_flag; + gen_pipe_dff #(8) int_ff(clk, rst, hold_en, `INT_NONE, int_flag_i, int_flag); + assign int_flag_o = int_flag; endmodule diff --git a/rtl/core/regs.v b/rtl/core/regs.v index f3a550c..dd486a1 100644 --- a/rtl/core/regs.v +++ b/rtl/core/regs.v @@ -55,9 +55,9 @@ module regs( always @ (posedge clk) begin if (rst == `RstDisable) begin // 优先ex模块写操作 - if ((we_i == `WriteEnable) && (waddr_i != `RegNumLog2'h0)) begin + if ((we_i == `WriteEnable) && (waddr_i != `ZeroReg)) begin regs[waddr_i] <= wdata_i; - end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `RegNumLog2'h0)) begin + end else if ((jtag_we_i == `WriteEnable) && (jtag_addr_i != `ZeroReg)) begin regs[jtag_addr_i] <= jtag_data_i; end end @@ -65,9 +65,7 @@ module regs( // 读寄存器1 always @ (*) begin - if (rst == `RstEnable) begin - rdata1_o = `ZeroWord; - end else if (raddr1_i == `RegNumLog2'h0) begin + if (raddr1_i == `ZeroReg) begin rdata1_o = `ZeroWord; // 如果读地址等于写地址，并且正在写操作，则直接返回写数据 end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin @@ -79,9 +77,7 @@ module regs( // 读寄存器2 always @ (*) begin - if (rst == `RstEnable) begin - rdata2_o = `ZeroWord; - end else if (raddr2_i == `RegNumLog2'h0) begin + if (raddr2_i == `ZeroReg) begin rdata2_o = `ZeroWord; // 如果读地址等于写地址，并且正在写操作，则直接返回写数据 end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin @@ -93,9 +89,7 @@ module regs( // jtag读寄存器 always @ (*) begin - if (rst == `RstEnable) begin - jtag_data_o = `ZeroWord; - end else if (jtag_addr_i == `RegNumLog2'h0) begin + if (jtag_addr_i == `ZeroReg) begin jtag_data_o = `ZeroWord; end else begin jtag_data_o = regs[jtag_addr_i]; diff --git a/rtl/core/rib.v b/rtl/core/rib.v index 95d1746..de53809 100644 --- a/rtl/core/rib.v +++ b/rtl/core/rib.v @@ -93,7 +93,7 @@ module rib( // 访问地址的最高4位决定要访问的是哪一个从设备 - // 因此最高支持16个从设备 + // 因此最多支持16个从设备 parameter [3:0]slave_0 = 4'b0000; parameter [3:0]slave_1 = 4'b0001; parameter [3:0]slave_2 = 4'b0010; @@ -115,257 +115,226 @@ module rib( // 仲裁逻辑 // 固定优先级仲裁机制 - // 优先级由高到低：主设备0，主设备2，主设备1 + // 优先级由高到低：主设备3，主设备0，主设备2，主设备1 always @ (*) begin - if (rst == `RstEnable) begin + if (req[3]) begin + grant = grant3; + hold_flag_o = `HoldEnable; + end else if (req[0]) begin + grant = grant0; + hold_flag_o = `HoldEnable; + end else if (req[2]) begin + grant = grant2; + hold_flag_o = `HoldEnable; + end else begin grant = grant1; hold_flag_o = `HoldDisable; - end else begin - if (req[3]) begin - grant = grant3; - hold_flag_o = `HoldEnable; - end else if (req[0]) begin - grant = grant0; - hold_flag_o = `HoldEnable; - end else if (req[2]) begin - grant = grant2; - hold_flag_o = `HoldEnable; - end else begin - grant = grant1; - hold_flag_o = `HoldDisable; - end end end // 根据仲裁结果，选择(访问)对应的从设备 always @ (*) begin - if (rst == `RstEnable) begin - m0_data_o = `ZeroWord; - m1_data_o = `INST_NOP; - m2_data_o = `ZeroWord; - m3_data_o = `ZeroWord; + m0_data_o = `ZeroWord; + m1_data_o = `INST_NOP; + m2_data_o = `ZeroWord; + m3_data_o = `ZeroWord; - s0_addr_o = `ZeroWord; - s1_addr_o = `ZeroWord; - s2_addr_o = `ZeroWord; - s3_addr_o = `ZeroWord; - s4_addr_o = `ZeroWord; - s5_addr_o = `ZeroWord; - s0_data_o = `ZeroWord; - s1_data_o = `ZeroWord; - s2_data_o = `ZeroWord; - s3_data_o = `ZeroWord; - s4_data_o = `ZeroWord; - s5_data_o = `ZeroWord; - s0_we_o = `WriteDisable; - s1_we_o = `WriteDisable; - s2_we_o = `WriteDisable; - s3_we_o = `WriteDisable; - s4_we_o = `WriteDisable; - s5_we_o = `WriteDisable; - end else begin - m0_data_o = `ZeroWord; - m1_data_o = `INST_NOP; - m2_data_o = `ZeroWord; - m3_data_o = `ZeroWord; + s0_addr_o = `ZeroWord; + s1_addr_o = `ZeroWord; + s2_addr_o = `ZeroWord; + s3_addr_o = `ZeroWord; + s4_addr_o = `ZeroWord; + s5_addr_o = `ZeroWord; + s0_data_o = `ZeroWord; + s1_data_o = `ZeroWord; + s2_data_o = `ZeroWord; + s3_data_o = `ZeroWord; + s4_data_o = `ZeroWord; + s5_data_o = `ZeroWord; + s0_we_o = `WriteDisable; + s1_we_o = `WriteDisable; + s2_we_o = `WriteDisable; + s3_we_o = `WriteDisable; + s4_we_o = `WriteDisable; + s5_we_o = `WriteDisable; - s0_addr_o = `ZeroWord; - s1_addr_o = `ZeroWord; - s2_addr_o = `ZeroWord; - s3_addr_o = `ZeroWord; - s4_addr_o = `ZeroWord; - s5_addr_o = `ZeroWord; - s0_data_o = `ZeroWord; - s1_data_o = `ZeroWord; - s2_data_o = `ZeroWord; - s3_data_o = `ZeroWord; - s4_data_o = `ZeroWord; - s5_data_o = `ZeroWord; - s0_we_o = `WriteDisable; - s1_we_o = `WriteDisable; - s2_we_o = `WriteDisable; - s3_we_o = `WriteDisable; - s4_we_o = `WriteDisable; - s5_we_o = `WriteDisable; + case (grant) + grant0: begin + case (m0_addr_i[31:28]) + slave_0: begin + s0_we_o = m0_we_i; + s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s0_data_o = m0_data_i; + m0_data_o = s0_data_i; + end + slave_1: begin + s1_we_o = m0_we_i; + s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s1_data_o = m0_data_i; + m0_data_o = s1_data_i; + end + slave_2: begin + s2_we_o = m0_we_i; + s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s2_data_o = m0_data_i; + m0_data_o = s2_data_i; + end + slave_3: begin + s3_we_o = m0_we_i; + s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s3_data_o = m0_data_i; + m0_data_o = s3_data_i; + end + slave_4: begin + s4_we_o = m0_we_i; + s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s4_data_o = m0_data_i; + m0_data_o = s4_data_i; + end + slave_5: begin + s5_we_o = m0_we_i; + s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s5_data_o = m0_data_i; + m0_data_o = s5_data_i; + end + default: begin - case (grant) - grant0: begin - case (m0_addr_i[31:28]) - slave_0: begin - s0_we_o = m0_we_i; - s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s0_data_o = m0_data_i; - m0_data_o = s0_data_i; - end - slave_1: begin - s1_we_o = m0_we_i; - s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s1_data_o = m0_data_i; - m0_data_o = s1_data_i; - end - slave_2: begin - s2_we_o = m0_we_i; - s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s2_data_o = m0_data_i; - m0_data_o = s2_data_i; - end - slave_3: begin - s3_we_o = m0_we_i; - s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s3_data_o = m0_data_i; - m0_data_o = s3_data_i; - end - slave_4: begin - s4_we_o = m0_we_i; - s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s4_data_o = m0_data_i; - m0_data_o = s4_data_i; - end - slave_5: begin - s5_we_o = m0_we_i; - s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; - s5_data_o = m0_data_i; - m0_data_o = s5_data_i; - end - default: begin + end + endcase + end + grant1: begin + case (m1_addr_i[31:28]) + slave_0: begin + s0_we_o = m1_we_i; + s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s0_data_o = m1_data_i; + m1_data_o = s0_data_i; + end + slave_1: begin + s1_we_o = m1_we_i; + s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s1_data_o = m1_data_i; + m1_data_o = s1_data_i; + end + slave_2: begin + s2_we_o = m1_we_i; + s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s2_data_o = m1_data_i; + m1_data_o = s2_data_i; + end + slave_3: begin + s3_we_o = m1_we_i; + s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s3_data_o = m1_data_i; + m1_data_o = s3_data_i; + end + slave_4: begin + s4_we_o = m1_we_i; + s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s4_data_o = m1_data_i; + m1_data_o = s4_data_i; + end + slave_5: begin + s5_we_o = m1_we_i; + s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s5_data_o = m1_data_i; + m1_data_o = s5_data_i; + end + default: begin - end - endcase - end - grant1: begin - case (m1_addr_i[31:28]) - slave_0: begin - s0_we_o = m1_we_i; - s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s0_data_o = m1_data_i; - m1_data_o = s0_data_i; - end - slave_1: begin - s1_we_o = m1_we_i; - s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s1_data_o = m1_data_i; - m1_data_o = s1_data_i; - end - slave_2: begin - s2_we_o = m1_we_i; - s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s2_data_o = m1_data_i; - m1_data_o = s2_data_i; - end - slave_3: begin - s3_we_o = m1_we_i; - s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s3_data_o = m1_data_i; - m1_data_o = s3_data_i; - end - slave_4: begin - s4_we_o = m1_we_i; - s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s4_data_o = m1_data_i; - m1_data_o = s4_data_i; - end - slave_5: begin - s5_we_o = m1_we_i; - s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; - s5_data_o = m1_data_i; - m1_data_o = s5_data_i; - end - default: begin + end + endcase + end + grant2: begin + case (m2_addr_i[31:28]) + slave_0: begin + s0_we_o = m2_we_i; + s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s0_data_o = m2_data_i; + m2_data_o = s0_data_i; + end + slave_1: begin + s1_we_o = m2_we_i; + s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s1_data_o = m2_data_i; + m2_data_o = s1_data_i; + end + slave_2: begin + s2_we_o = m2_we_i; + s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s2_data_o = m2_data_i; + m2_data_o = s2_data_i; + end + slave_3: begin + s3_we_o = m2_we_i; + s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s3_data_o = m2_data_i; + m2_data_o = s3_data_i; + end + slave_4: begin + s4_we_o = m2_we_i; + s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s4_data_o = m2_data_i; + m2_data_o = s4_data_i; + end + slave_5: begin + s5_we_o = m2_we_i; + s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s5_data_o = m2_data_i; + m2_data_o = s5_data_i; + end + default: begin - end - endcase - end - grant2: begin - case (m2_addr_i[31:28]) - slave_0: begin - s0_we_o = m2_we_i; - s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s0_data_o = m2_data_i; - m2_data_o = s0_data_i; - end - slave_1: begin - s1_we_o = m2_we_i; - s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s1_data_o = m2_data_i; - m2_data_o = s1_data_i; - end - slave_2: begin - s2_we_o = m2_we_i; - s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s2_data_o = m2_data_i; - m2_data_o = s2_data_i; - end - slave_3: begin - s3_we_o = m2_we_i; - s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s3_data_o = m2_data_i; - m2_data_o = s3_data_i; - end - slave_4: begin - s4_we_o = m2_we_i; - s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s4_data_o = m2_data_i; - m2_data_o = s4_data_i; - end - slave_5: begin - s5_we_o = m2_we_i; - s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; - s5_data_o = m2_data_i; - m2_data_o = s5_data_i; - end - default: begin + end + endcase + end + grant3: begin + case (m3_addr_i[31:28]) + slave_0: begin + s0_we_o = m3_we_i; + s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s0_data_o = m3_data_i; + m3_data_o = s0_data_i; + end + slave_1: begin + s1_we_o = m3_we_i; + s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s1_data_o = m3_data_i; + m3_data_o = s1_data_i; + end + slave_2: begin + s2_we_o = m3_we_i; + s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s2_data_o = m3_data_i; + m3_data_o = s2_data_i; + end + slave_3: begin + s3_we_o = m3_we_i; + s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s3_data_o = m3_data_i; + m3_data_o = s3_data_i; + end + slave_4: begin + s4_we_o = m3_we_i; + s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s4_data_o = m3_data_i; + m3_data_o = s4_data_i; + end + slave_5: begin + s5_we_o = m3_we_i; + s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; + s5_data_o = m3_data_i; + m3_data_o = s5_data_i; + end + default: begin - end - endcase - end - grant3: begin - case (m3_addr_i[31:28]) - slave_0: begin - s0_we_o = m3_we_i; - s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s0_data_o = m3_data_i; - m3_data_o = s0_data_i; - end - slave_1: begin - s1_we_o = m3_we_i; - s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s1_data_o = m3_data_i; - m3_data_o = s1_data_i; - end - slave_2: begin - s2_we_o = m3_we_i; - s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s2_data_o = m3_data_i; - m3_data_o = s2_data_i; - end - slave_3: begin - s3_we_o = m3_we_i; - s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s3_data_o = m3_data_i; - m3_data_o = s3_data_i; - end - slave_4: begin - s4_we_o = m3_we_i; - s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s4_data_o = m3_data_i; - m3_data_o = s4_data_i; - end - slave_5: begin - s5_we_o = m3_we_i; - s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}}; - s5_data_o = m3_data_i; - m3_data_o = s5_data_i; - end - default: begin + end + endcase + end + default: begin - end - endcase - end - default: begin - - end - endcase - end + end + endcase end endmodule diff --git a/rtl/debug/uart_debug.v b/rtl/debug/uart_debug.v index 803a95d..b55cd58 100644 --- a/rtl/debug/uart_debug.v +++ b/rtl/debug/uart_debug.v @@ -58,22 +58,22 @@ module uart_debug( // 状态 - localparam S_IDLE = 1; - localparam S_INIT_UART_BAUD = 2; - localparam S_CLEAR_UART_RX_OVER_FLAG = 3; - localparam S_WAIT_BYTE = 4; - localparam S_WAIT_BYTE2 = 5; - localparam S_GET_BYTE = 6; - localparam S_REC_FIRST_PACKET = 7; - localparam S_REC_REMAIN_PACKET = 8; - localparam S_SEND_ACK = 9; - localparam S_SEND_NAK = 10; - localparam S_CRC_START = 11; - localparam S_CRC_CALC = 12; - localparam S_CRC_END = 13; - localparam S_WRITE_MEM = 14; + localparam S_IDLE = 14'h0001; + localparam S_INIT_UART_BAUD = 14'h0002; + localparam S_CLEAR_UART_RX_OVER_FLAG = 14'h0004; + localparam S_WAIT_BYTE = 14'h0008; + localparam S_WAIT_BYTE2 = 14'h0010; + localparam S_GET_BYTE = 14'h0020; + localparam S_REC_FIRST_PACKET = 14'h0040; + localparam S_REC_REMAIN_PACKET = 14'h0080; + localparam S_SEND_ACK = 14'h0100; + localparam S_SEND_NAK = 14'h0200; + localparam S_CRC_START = 14'h0400; + localparam S_CRC_CALC = 14'h0800; + localparam S_CRC_END = 14'h1000; + localparam S_WRITE_MEM = 14'h2000; - reg[3:0] state; + reg[13:0] state; // 存放串口接收到的数据 reg[7:0] rx_data[0:131]; @@ -83,7 +83,10 @@ module uart_debug( reg[31:0] fw_file_size; reg[31:0] write_mem_addr; reg[31:0] write_mem_data; - reg[7:0] write_mem_byte_index; + reg[7:0] write_mem_byte_index0; + reg[7:0] write_mem_byte_index1; + reg[7:0] write_mem_byte_index2; + reg[7:0] write_mem_byte_index3; reg[15:0] crc_result; reg[3:0] crc_bit_index; @@ -177,7 +180,7 @@ module uart_debug( end end S_WRITE_MEM: begin - if (write_mem_byte_index == (need_to_rec_bytes + 2)) begin + if (write_mem_byte_index0 == (need_to_rec_bytes + 2)) begin state <= S_SEND_ACK; end else begin mem_addr_o <= write_mem_addr; @@ -262,25 +265,107 @@ module uart_debug( always @ (posedge clk) begin if (rst == 1'b0 || debug_en_i == 1'b0) begin write_mem_addr <= 32'h0; - write_mem_data <= 32'h0; - write_mem_byte_index <= 8'h0; end else begin case (state) S_REC_FIRST_PACKET: begin write_mem_addr <= `ROM_START_ADDR; - write_mem_data <= 32'h0; - write_mem_byte_index <= 8'h0; end S_CRC_END: begin - write_mem_data <= {rx_data[4], rx_data[3], rx_data[2], rx_data[1]}; - write_mem_byte_index <= 8'h5; if (write_mem_addr > 0) write_mem_addr <= write_mem_addr - 4; end S_WRITE_MEM: begin write_mem_addr <= write_mem_addr + 4; - write_mem_data <= {rx_data[write_mem_byte_index + 3], rx_data[write_mem_byte_index + 2], rx_data[write_mem_byte_index + 1], rx_data[write_mem_byte_index]}; - write_mem_byte_index <= write_mem_byte_index + 4; + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + write_mem_data <= 32'h0; + end else begin + case (state) + S_REC_FIRST_PACKET: begin + write_mem_data <= 32'h0; + end + S_CRC_END: begin + write_mem_data <= {rx_data[4], rx_data[3], rx_data[2], rx_data[1]}; + end + S_WRITE_MEM: begin + write_mem_data <= {rx_data[write_mem_byte_index3], rx_data[write_mem_byte_index2], rx_data[write_mem_byte_index1], rx_data[write_mem_byte_index0]}; + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + write_mem_byte_index0 <= 8'h0; + end else begin + case (state) + S_REC_FIRST_PACKET: begin + write_mem_byte_index0 <= 8'h0; + end + S_CRC_END: begin + write_mem_byte_index0 <= 8'h5; + end + S_WRITE_MEM: begin + write_mem_byte_index0 <= write_mem_byte_index0 + 4; + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + write_mem_byte_index1 <= 8'h0; + end else begin + case (state) + S_REC_FIRST_PACKET: begin + write_mem_byte_index1 <= 8'h0; + end + S_CRC_END: begin + write_mem_byte_index1 <= 8'h6; + end + S_WRITE_MEM: begin + write_mem_byte_index1 <= write_mem_byte_index1 + 4; + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + write_mem_byte_index2 <= 8'h0; + end else begin + case (state) + S_REC_FIRST_PACKET: begin + write_mem_byte_index2 <= 8'h0; + end + S_CRC_END: begin + write_mem_byte_index2 <= 8'h7; + end + S_WRITE_MEM: begin + write_mem_byte_index2 <= write_mem_byte_index2 + 4; + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + write_mem_byte_index3 <= 8'h0; + end else begin + case (state) + S_REC_FIRST_PACKET: begin + write_mem_byte_index3 <= 8'h0; + end + S_CRC_END: begin + write_mem_byte_index3 <= 8'h8; + end + S_WRITE_MEM: begin + write_mem_byte_index3 <= write_mem_byte_index3 + 4; end endcase end @@ -290,30 +375,21 @@ module uart_debug( always @ (posedge clk) begin if (rst == 1'b0 || debug_en_i == 1'b0) begin crc_result <= 16'h0; - crc_bit_index <= 4'h0; - crc_byte_index <= 8'h0; end else begin case (state) S_CRC_START: begin crc_result <= 16'hffff; - crc_bit_index <= 4'h0; - crc_byte_index <= 8'h1; end S_CRC_CALC: begin if (crc_bit_index == 4'h0) begin crc_result <= crc_result ^ rx_data[crc_byte_index]; - crc_byte_index <= crc_byte_index + 1'b1; - crc_bit_index <= crc_bit_index + 1'b1; end else begin if (crc_bit_index < 4'h9) begin - crc_bit_index <= crc_bit_index + 1'b1; if (crc_result[0] == 1'b1) begin crc_result <= {1'b0, crc_result[15:1]} ^ 16'ha001; end else begin crc_result <= {1'b0, crc_result[15:1]}; end - end else begin - crc_bit_index <= 4'h0; end end end @@ -321,4 +397,40 @@ module uart_debug( end end + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + crc_bit_index <= 4'h0; + end else begin + case (state) + S_CRC_START: begin + crc_bit_index <= 4'h0; + end + S_CRC_CALC: begin + if (crc_bit_index < 4'h9) begin + crc_bit_index <= crc_bit_index + 1'b1; + end else begin + crc_bit_index <= 4'h0; + end + end + endcase + end + end + + always @ (posedge clk) begin + if (rst == 1'b0 || debug_en_i == 1'b0) begin + crc_byte_index <= 8'h0; + end else begin + case (state) + S_CRC_START: begin + crc_byte_index <= 8'h1; + end + S_CRC_CALC: begin + if (crc_bit_index == 4'h0) begin + crc_byte_index <= crc_byte_index + 1'b1; + end + end + endcase + end + end + endmodule