rtl: fix interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/1/head
parent
233bb1fb23
commit
b39062a4ea
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@ -31,6 +31,10 @@ module clint(
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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// from ex
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input wire jump_flag_i,
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input wire[`InstAddrBus] jump_addr_i,
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// from ctrl
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// from ctrl
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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@ -124,19 +128,23 @@ module clint(
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// 定时器中断
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// 定时器中断
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cause <= 32'h80000004;
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cause <= 32'h80000004;
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csr_state <= S_CSR_MEPC;
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csr_state <= S_CSR_MEPC;
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if (jump_flag_i == `JumpEnable) begin
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inst_addr <= jump_addr_i;
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end else begin
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inst_addr <= inst_addr_i;
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inst_addr <= inst_addr_i;
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end
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// 中断返回
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// 中断返回
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end else if (int_state == S_INT_MRET) begin
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end else if (int_state == S_INT_MRET) begin
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csr_state <= S_CSR_MSTATUS_MRET;
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csr_state <= S_CSR_MSTATUS_MRET;
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end
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end
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end
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end
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S_CSR_MEPC: begin
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S_CSR_MEPC: begin
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csr_state <= S_CSR_MCAUSE;
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end
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S_CSR_MCAUSE: begin
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csr_state <= S_CSR_MSTATUS;
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csr_state <= S_CSR_MSTATUS;
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end
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end
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S_CSR_MSTATUS: begin
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S_CSR_MSTATUS: begin
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csr_state <= S_CSR_MCAUSE;
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end
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S_CSR_MCAUSE: begin
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csr_state <= S_CSR_IDLE;
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csr_state <= S_CSR_IDLE;
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end
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end
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S_CSR_MSTATUS_MRET: begin
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S_CSR_MSTATUS_MRET: begin
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@ -196,8 +204,8 @@ module clint(
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int_assert_o <= `INT_DEASSERT;
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int_assert_o <= `INT_DEASSERT;
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int_addr_o <= `ZeroWord;
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int_addr_o <= `ZeroWord;
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end else begin
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end else begin
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// 发出中断进入信号.写完mstatus寄存器才能发
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// 发出中断进入信号.写完mcause寄存器才能发
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if (csr_state == S_CSR_MSTATUS) begin
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if (csr_state == S_CSR_MCAUSE) begin
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int_assert_o <= `INT_ASSERT;
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int_assert_o <= `INT_ASSERT;
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int_addr_o <= csr_mtvec;
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int_addr_o <= csr_mtvec;
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// 发出中断返回信号
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// 发出中断返回信号
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@ -27,6 +27,9 @@ module if_id(
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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input wire[`INT_BUS] int_flag_i, // 外设中断输入信号
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output reg[`INT_BUS] int_flag_o,
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output reg[`InstBus] inst_o, // 指令内容
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output reg[`InstBus] inst_o, // 指令内容
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output reg[`InstAddrBus] inst_addr_o // 指令地址
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output reg[`InstAddrBus] inst_addr_o // 指令地址
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@ -36,13 +39,16 @@ module if_id(
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if (rst == `RstEnable) begin
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if (rst == `RstEnable) begin
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inst_o <= `INST_NOP;
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inst_o <= `INST_NOP;
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inst_addr_o <= `ZeroWord;
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inst_addr_o <= `ZeroWord;
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int_flag_o <= `INT_NONE;
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// 流水线暂停时传递默认值
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// 流水线暂停时传递默认值
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end else if (hold_flag_i >= `Hold_If) begin
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end else if (hold_flag_i >= `Hold_If) begin
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inst_o <= `INST_NOP;
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inst_o <= `INST_NOP;
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inst_addr_o <= inst_addr_i;
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inst_addr_o <= inst_addr_i;
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int_flag_o <= `INT_NONE;
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end else begin
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end else begin
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inst_o <= inst_i;
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inst_o <= inst_i;
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inst_addr_o <= inst_addr_i;
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inst_addr_o <= inst_addr_i;
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int_flag_o <= int_flag_i;
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end
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end
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end
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end
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@ -50,6 +50,7 @@ module tinyriscv(
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// if_id模块输出信号
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// if_id模块输出信号
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wire[`InstBus] if_inst_o;
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wire[`InstBus] if_inst_o;
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wire[`InstAddrBus] if_inst_addr_o;
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wire[`InstAddrBus] if_inst_addr_o;
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wire[`INT_BUS] if_int_flag_o;
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// id模块输出信号
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// id模块输出信号
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wire[`RegAddrBus] id_reg1_raddr_o;
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wire[`RegAddrBus] id_reg1_raddr_o;
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@ -208,6 +209,8 @@ module tinyriscv(
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.rst(rst),
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.rst(rst),
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.inst_i(rib_pc_data_i),
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.inst_i(rib_pc_data_i),
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.inst_addr_i(pc_pc_o),
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.inst_addr_i(pc_pc_o),
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.int_flag_i(int_i),
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.int_flag_o(if_int_flag_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.inst_o(if_inst_o),
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.inst_o(if_inst_o),
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.inst_addr_o(if_inst_addr_o)
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.inst_addr_o(if_inst_addr_o)
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@ -323,9 +326,11 @@ module tinyriscv(
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clint u_clint(
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clint u_clint(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.int_flag_i(int_i),
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.int_flag_i(if_int_flag_o),
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.inst_i(id_inst_o),
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.inst_i(id_inst_o),
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.inst_addr_i(id_inst_addr_o),
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.inst_addr_i(id_inst_addr_o),
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.jump_flag_i(ex_jump_flag_o),
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.jump_addr_i(ex_jump_addr_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.data_i(csr_clint_data_o),
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.data_i(csr_clint_data_o),
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.csr_mtvec(csr_clint_csr_mtvec),
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.csr_mtvec(csr_clint_csr_mtvec),
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