diff --git a/rtl/core/clint.v b/rtl/core/clint.v
index 757f8fc..628edae 100644
--- a/rtl/core/clint.v
+++ b/rtl/core/clint.v
@@ -31,6 +31,10 @@ module clint(
     input wire[`InstBus] inst_i,             // 指令内容
     input wire[`InstAddrBus] inst_addr_i,    // 指令地址
 
+    // from ex
+    input wire jump_flag_i,
+    input wire[`InstAddrBus] jump_addr_i,
+
     // from ctrl
     input wire[`Hold_Flag_Bus] hold_flag_i,  // 流水线暂停标志
 
@@ -124,19 +128,23 @@ module clint(
                         // 定时器中断
                         cause <= 32'h80000004;
                         csr_state <= S_CSR_MEPC;
-                        inst_addr <= inst_addr_i;
+                        if (jump_flag_i == `JumpEnable) begin
+                            inst_addr <= jump_addr_i;
+                        end else begin
+                            inst_addr <= inst_addr_i;
+                        end
                     // 中断返回
                     end else if (int_state == S_INT_MRET) begin
                         csr_state <= S_CSR_MSTATUS_MRET;
                     end
                 end
                 S_CSR_MEPC: begin
-                    csr_state <= S_CSR_MCAUSE;
-                end
-                S_CSR_MCAUSE: begin
                     csr_state <= S_CSR_MSTATUS;
                 end
                 S_CSR_MSTATUS: begin
+                    csr_state <= S_CSR_MCAUSE;
+                end
+                S_CSR_MCAUSE: begin
                     csr_state <= S_CSR_IDLE;
                 end
                 S_CSR_MSTATUS_MRET: begin
@@ -196,8 +204,8 @@ module clint(
             int_assert_o <= `INT_DEASSERT;
             int_addr_o <= `ZeroWord;
         end else begin
-            // 发出中断进入信号.写完mstatus寄存器才能发
-            if (csr_state == S_CSR_MSTATUS) begin
+            // 发出中断进入信号.写完mcause寄存器才能发
+            if (csr_state == S_CSR_MCAUSE) begin
                 int_assert_o <= `INT_ASSERT;
                 int_addr_o <= csr_mtvec;
             // 发出中断返回信号
diff --git a/rtl/core/if_id.v b/rtl/core/if_id.v
index f23f1c4..2cf4601 100644
--- a/rtl/core/if_id.v
+++ b/rtl/core/if_id.v
@@ -27,6 +27,9 @@ module if_id(
 
     input wire[`Hold_Flag_Bus] hold_flag_i, // 娴佹按绾挎殏鍋滄爣蹇�
 
+    input wire[`INT_BUS] int_flag_i,        // 澶栬涓柇杈撳叆淇″彿
+    output reg[`INT_BUS] int_flag_o,
+
     output reg[`InstBus] inst_o,            // 鎸囦护鍐呭
     output reg[`InstAddrBus] inst_addr_o    // 鎸囦护鍦板潃
 
@@ -36,13 +39,16 @@ module if_id(
         if (rst == `RstEnable) begin
             inst_o <= `INST_NOP;
             inst_addr_o <= `ZeroWord;
+            int_flag_o <= `INT_NONE;
         // 娴佹按绾挎殏鍋滄椂浼犻�掗粯璁ゅ��
         end else if (hold_flag_i >= `Hold_If) begin
             inst_o <= `INST_NOP;
             inst_addr_o <= inst_addr_i;
+            int_flag_o <= `INT_NONE;
         end else begin
             inst_o <= inst_i;
             inst_addr_o <= inst_addr_i;
+            int_flag_o <= int_flag_i;
         end
     end
 
diff --git a/rtl/core/tinyriscv.v b/rtl/core/tinyriscv.v
index 0d98dde..21f7573 100644
--- a/rtl/core/tinyriscv.v
+++ b/rtl/core/tinyriscv.v
@@ -50,6 +50,7 @@ module tinyriscv(
     // if_id妯″潡杈撳嚭淇″彿
 	wire[`InstBus] if_inst_o;
     wire[`InstAddrBus] if_inst_addr_o;
+    wire[`INT_BUS] if_int_flag_o;
 
     // id妯″潡杈撳嚭淇″彿
     wire[`RegAddrBus] id_reg1_raddr_o;
@@ -208,6 +209,8 @@ module tinyriscv(
         .rst(rst),
         .inst_i(rib_pc_data_i),
         .inst_addr_i(pc_pc_o),
+        .int_flag_i(int_i),
+        .int_flag_o(if_int_flag_o),
         .hold_flag_i(ctrl_hold_flag_o),
         .inst_o(if_inst_o),
         .inst_addr_o(if_inst_addr_o)
@@ -323,9 +326,11 @@ module tinyriscv(
     clint u_clint(
         .clk(clk),
         .rst(rst),
-        .int_flag_i(int_i),
+        .int_flag_i(if_int_flag_o),
         .inst_i(id_inst_o),
         .inst_addr_i(id_inst_addr_o),
+        .jump_flag_i(ex_jump_flag_o),
+        .jump_addr_i(ex_jump_addr_o),
         .hold_flag_i(ctrl_hold_flag_o),
         .data_i(csr_clint_data_o),
         .csr_mtvec(csr_clint_csr_mtvec),