zcy
/
tinyriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

optimize div 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-18 11:23:46 +08:00
parent 2638240d0b
commit b29781a8de
1 changed files with 22 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
rtl/core/ex.v
View File

@ -141,19 +141,28 @@ module ex(
mul_op2 <= `ZeroWord;
end else begin
if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin
if ((funct3 == `INST_MUL) || (funct3 == `INST_MULHU)) begin
mul_op1 <= reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end else if (funct3 == `INST_MULHSU) begin
mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end else if (funct3 == `INST_MULH) begin
mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
mul_op2 <= (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i;
end else begin
case (funct3)
`INST_MUL: begin
mul_op1 <= reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end
`INST_MULHU: begin
mul_op1 <= reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end
`INST_MULHSU: begin
mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end
`INST_MULH: begin
mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
mul_op2 <= (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i;
end
default: begin
mul_op1 <= reg1_rdata_i;
mul_op2 <= reg2_rdata_i;
end
endcase
end else begin
mul_op1 <= reg1_rdata_i;
mul_op2 <= reg2_rdata_i;