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sim: compliance_test: add utils modules 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-10-06 21:00:04 +08:00
parent 4876225f60
commit b15a130862
1 changed files with 5 additions and 0 deletions
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5
sim/compliance_test/compliance_test.py
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@ -42,6 +42,11 @@ iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v') iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v')
# ..rtl\utils
iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_rx.v')
iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_tx.v')
iverilog_cmd.append(r'..\..\rtl\utils\gen_buf.v')
iverilog_cmd.append(r'..\..\rtl\utils\gen_dff.v')
# ..\rtl\soc # ..\rtl\soc
iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v') iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')