From b15a1308620d952ec0efe31146ddc352a010f8a8 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Tue, 6 Oct 2020 21:00:04 +0800 Subject: [PATCH] sim: compliance_test: add utils modules Signed-off-by: liangkangnan --- sim/compliance_test/compliance_test.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sim/compliance_test/compliance_test.py b/sim/compliance_test/compliance_test.py index d8ce2c3..ad7cfa5 100644 --- a/sim/compliance_test/compliance_test.py +++ b/sim/compliance_test/compliance_test.py @@ -42,6 +42,11 @@ iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v') iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v') +# ..rtl\utils +iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_rx.v') +iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_tx.v') +iverilog_cmd.append(r'..\..\rtl\utils\gen_buf.v') +iverilog_cmd.append(r'..\..\rtl\utils\gen_dff.v') # ..\rtl\soc iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')