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rtl:timer: update interrupt assert 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-07-12 22:33:15 +08:00
parent 6f5fe893cb
commit b0c4d1fa4d
1 changed files with 10 additions and 17 deletions
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25
rtl/perips/timer.v
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@ -29,7 +29,7 @@ module timer(
input wire req_i,
output reg[31:0] data_o,
output reg int_sig_o,
output wire int_sig_o,
output reg ack_o
);
@ -53,28 +53,20 @@ module timer(
reg[31:0] timer_value;
assign int_sig_o = ((timer_ctrl[2] == 1'b1) && (timer_ctrl[1] == 1'b1))? `INT_ASSERT: `INT_DEASSERT;
// counter
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_count <= `ZeroWord;
end else begin
if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin
if (timer_ctrl[0] == 1'b1) begin
timer_count <= timer_count + 1'b1;
end else begin
if (timer_count >= timer_value) begin
timer_count <= `ZeroWord;
end
end
end
// int signal
always @ (posedge clk) begin
if (rst == `RstEnable) begin
int_sig_o <= `INT_DEASSERT;
end else begin
if (timer_count >= timer_value && timer_value > 32'h0) begin
int_sig_o <= `INT_ASSERT;
end else if (we_i == `WriteEnable && addr_i[3:0] == REG_CTRL && timer_ctrl[2] == 1'b1) begin
int_sig_o <= `INT_DEASSERT;
timer_count <= `ZeroWord;
end
end
end
@ -88,15 +80,16 @@ module timer(
if (we_i == `WriteEnable) begin
case (addr_i[3:0])
REG_CTRL: begin
timer_ctrl <= data_i;
timer_ctrl <= {data_i[31:3], (timer_ctrl[2] & (~data_i[2])), data_i[1:0]};
end
REG_VALUE: begin
timer_value <= data_i;
end
endcase
end else begin
if (timer_count >= timer_value && timer_value > 32'h0) begin
if ((timer_ctrl[0] == 1'b1) && (timer_count >= timer_value)) begin
timer_ctrl[0] <= 1'b0;
timer_ctrl[2] <= 1'b1;
end
end
end