From b0c4d1fa4d03ab83393df6bc2ef6d3592f8d9596 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sun, 12 Jul 2020 22:33:15 +0800
Subject: [PATCH] rtl:timer: update interrupt assert

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl/perips/timer.v | 27 ++++++++++-----------------
 1 file changed, 10 insertions(+), 17 deletions(-)

diff --git a/rtl/perips/timer.v b/rtl/perips/timer.v
index 1025938..a81c28a 100644
--- a/rtl/perips/timer.v
+++ b/rtl/perips/timer.v
@@ -29,7 +29,7 @@ module timer(
     input wire req_i,
 
     output reg[31:0] data_o,
-    output reg int_sig_o,
+    output wire int_sig_o,
     output reg ack_o
 
     );
@@ -53,32 +53,24 @@ module timer(
     reg[31:0] timer_value;
 
 
+    assign int_sig_o = ((timer_ctrl[2] == 1'b1) && (timer_ctrl[1] == 1'b1))? `INT_ASSERT: `INT_DEASSERT;
+
     // counter
     always @ (posedge clk) begin
         if (rst == `RstEnable) begin
             timer_count <= `ZeroWord;
         end else begin
-            if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin
+            if (timer_ctrl[0] == 1'b1) begin
                 timer_count <= timer_count + 1'b1;
+                if (timer_count >= timer_value) begin
+                    timer_count <= `ZeroWord;
+                end
             end else begin
                 timer_count <= `ZeroWord;
             end
         end
     end
 
-    // int signal
-    always @ (posedge clk) begin
-        if (rst == `RstEnable) begin
-            int_sig_o <= `INT_DEASSERT;
-        end else begin
-            if (timer_count >= timer_value && timer_value > 32'h0) begin
-                int_sig_o <= `INT_ASSERT;
-            end else if (we_i == `WriteEnable && addr_i[3:0] == REG_CTRL && timer_ctrl[2] == 1'b1) begin
-                int_sig_o <= `INT_DEASSERT;
-            end
-        end
-    end
-
     // write regs
     always @ (posedge clk) begin
         if (rst == `RstEnable) begin
@@ -88,15 +80,16 @@ module timer(
             if (we_i == `WriteEnable) begin
                 case (addr_i[3:0])
                     REG_CTRL: begin
-                        timer_ctrl <= data_i;
+                        timer_ctrl <= {data_i[31:3], (timer_ctrl[2] & (~data_i[2])), data_i[1:0]};
                     end
                     REG_VALUE: begin
                         timer_value <= data_i;
                     end
                 endcase
             end else begin
-                if (timer_count >= timer_value && timer_value > 32'h0) begin
+                if ((timer_ctrl[0] == 1'b1) && (timer_count >= timer_value)) begin
                     timer_ctrl[0] <= 1'b0;
+                    timer_ctrl[2] <= 1'b1;
                 end
             end
         end