rtl:timer: update interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/1/head
parent
6f5fe893cb
commit
b0c4d1fa4d
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@ -29,7 +29,7 @@ module timer(
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input wire req_i,
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output reg[31:0] data_o,
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output reg int_sig_o,
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output wire int_sig_o,
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output reg ack_o
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);
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@ -53,32 +53,24 @@ module timer(
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reg[31:0] timer_value;
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assign int_sig_o = ((timer_ctrl[2] == 1'b1) && (timer_ctrl[1] == 1'b1))? `INT_ASSERT: `INT_DEASSERT;
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// counter
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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timer_count <= `ZeroWord;
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end else begin
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if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin
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if (timer_ctrl[0] == 1'b1) begin
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timer_count <= timer_count + 1'b1;
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if (timer_count >= timer_value) begin
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timer_count <= `ZeroWord;
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end
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end else begin
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timer_count <= `ZeroWord;
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end
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end
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end
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// int signal
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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int_sig_o <= `INT_DEASSERT;
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end else begin
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if (timer_count >= timer_value && timer_value > 32'h0) begin
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int_sig_o <= `INT_ASSERT;
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end else if (we_i == `WriteEnable && addr_i[3:0] == REG_CTRL && timer_ctrl[2] == 1'b1) begin
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int_sig_o <= `INT_DEASSERT;
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end
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end
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end
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// write regs
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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@ -88,15 +80,16 @@ module timer(
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if (we_i == `WriteEnable) begin
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case (addr_i[3:0])
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REG_CTRL: begin
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timer_ctrl <= data_i;
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timer_ctrl <= {data_i[31:3], (timer_ctrl[2] & (~data_i[2])), data_i[1:0]};
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end
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REG_VALUE: begin
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timer_value <= data_i;
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end
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endcase
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end else begin
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if (timer_count >= timer_value && timer_value > 32'h0) begin
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if ((timer_ctrl[0] == 1'b1) && (timer_count >= timer_value)) begin
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timer_ctrl[0] <= 1'b0;
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timer_ctrl[2] <= 1'b1;
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end
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end
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end
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