From 9ac1b31965ed5dd28bf72f0ba6b02267a8689598 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Tue, 13 Apr 2021 14:12:47 +0800
Subject: [PATCH] rtl: add reset module

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl.flist                            |  2 +-
 rtl/core/{rst_ctrl.sv => rst_gen.sv} | 38 ++++++++--------------------
 rtl/top/tinyriscv_soc_top.sv         | 24 ++++++++++++++----
 sim/tb_top_verilator.sv              |  2 +-
 4 files changed, 32 insertions(+), 34 deletions(-)
 rename rtl/core/{rst_ctrl.sv => rst_gen.sv} (55%)

diff --git a/rtl.flist b/rtl.flist
index e65425e..41c1b07 100644
--- a/rtl.flist
+++ b/rtl.flist
@@ -18,7 +18,7 @@
 ../rtl/core/ifu.sv
 ../rtl/core/ifu_idu.sv
 ../rtl/core/pipe_ctrl.sv
-../rtl/core/rst_ctrl.sv
+../rtl/core/rst_gen.sv
 ../rtl/core/tinyriscv_core.sv
 ../rtl/core/tracer.sv
 
diff --git a/rtl/core/rst_ctrl.sv b/rtl/core/rst_gen.sv
similarity index 55%
rename from rtl/core/rst_ctrl.sv
rename to rtl/core/rst_gen.sv
index 3124bdd..a3ea82d 100644
--- a/rtl/core/rst_ctrl.sv
+++ b/rtl/core/rst_gen.sv
@@ -17,43 +17,27 @@
 `include "defines.sv"
 
 // 复位控制模块
-module rst_ctrl(
+module rst_gen #(
+    parameter RESET_FIFO_DEPTH = 5
+    )(
 
     input wire clk,
+    input wire rst_ni,
 
-    input wire rst_ext_i,
-    input wire rst_jtag_i,
-
-    output wire core_rst_n_o,
-    output wire jtag_rst_n_o
+    output wire rst_no
 
     );
 
-    wire ext_rst_r;
+    reg[RESET_FIFO_DEPTH-1:0] synch_regs_q;
 
-    gen_ticks_sync #(
-        .DP(2),
-        .DW(1)
-    ) ext_rst_sync(
-        .rst_n(rst_ext_i),
-        .clk(clk),
-        .din(1'b1),
-        .dout(ext_rst_r)
-    );
-
-    reg[`JTAG_RESET_FF_LEVELS-1:0] jtag_rst_r;
-
-    always @ (posedge clk) begin
-        if (!rst_ext_i) begin
-            jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b1}};
-        end if (rst_jtag_i) begin
-            jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b0}};
+    always @ (posedge clk or negedge rst_ni) begin
+        if (~rst_ni) begin
+            synch_regs_q <= 0;
         end else begin
-            jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {jtag_rst_r[`JTAG_RESET_FF_LEVELS-2:0], 1'b1};
+            synch_regs_q <= {synch_regs_q[RESET_FIFO_DEPTH-2:0], 1'b1};
         end
     end
 
-    assign core_rst_n_o = ext_rst_r & jtag_rst_r[`JTAG_RESET_FF_LEVELS-1];
-    assign jtag_rst_n_o = ext_rst_r;
+    assign rst_no = synch_regs_q[RESET_FIFO_DEPTH-1];
 
 endmodule
diff --git a/rtl/top/tinyriscv_soc_top.sv b/rtl/top/tinyriscv_soc_top.sv
index becab2b..3ac9644 100644
--- a/rtl/top/tinyriscv_soc_top.sv
+++ b/rtl/top/tinyriscv_soc_top.sv
@@ -20,7 +20,7 @@
 module tinyriscv_soc_top(
 
     input wire clk,
-    input wire rst_ext_i,
+    input wire rst_ext_ni,
 
     output wire halted_ind,  // jtag是否已经halt住CPU信号
 
@@ -69,13 +69,17 @@ module tinyriscv_soc_top(
     wire [31:0]    slave_addr_mask  [SLAVES];
     wire [31:0]    slave_addr_base  [SLAVES];
 
+    wire ndmreset;
+    wire ndmreset_n;
+
+    assign ndmreset = 1'b0;
 
     tinyriscv_core #(
         .DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + 16'h800),
         .DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + 16'h808)
     ) u_tinyriscv_core (
         .clk(clk),
-        .rst_n(rst_ext_i),
+        .rst_n(ndmreset_n),
 
         .instr_req_o(master_req[CoreI]),
         .instr_gnt_i(master_gnt[CoreI]),
@@ -111,7 +115,7 @@ module tinyriscv_soc_top(
         .DP(`ROM_DEPTH)
     ) u_rom(
         .clk(clk),
-        .rst_n(rst_ext_i),
+        .rst_n(ndmreset_n),
         .addr_i(slave_addr[Rom]),
         .data_i(slave_wdata[Rom]),
         .sel_i(slave_be[Rom]),
@@ -126,7 +130,7 @@ module tinyriscv_soc_top(
         .DP(`RAM_DEPTH)
     ) u_ram(
         .clk(clk),
-        .rst_n(rst_ext_i),
+        .rst_n(ndmreset_n),
         .addr_i(slave_addr[Ram]),
         .data_i(slave_wdata[Ram]),
         .sel_i(slave_be[Ram]),
@@ -139,7 +143,7 @@ module tinyriscv_soc_top(
         .SLAVES(SLAVES)
     ) bus (
         .clk_i(clk),
-        .rst_ni(rst_ext_i),
+        .rst_ni(ndmreset_n),
         .master_req_i(master_req),
         .master_gnt_o(master_gnt),
         .master_rvalid_o(master_rvalid),
@@ -160,4 +164,14 @@ module tinyriscv_soc_top(
         .slave_rdata_i(slave_rdata)
     );
 
+
+    rst_gen #(
+        .RESET_FIFO_DEPTH(5)
+    ) u_rst (
+        .clk(clk),
+        .rst_ni(rst_ext_ni & (~ndmreset)),
+        .rst_no(ndmreset_n)
+    );
+
+
 endmodule
diff --git a/sim/tb_top_verilator.sv b/sim/tb_top_verilator.sv
index 0761e51..01f9d11 100644
--- a/sim/tb_top_verilator.sv
+++ b/sim/tb_top_verilator.sv
@@ -68,7 +68,7 @@ module tb_top_verilator #(
 
     tinyriscv_soc_top u_tinyriscv_soc_top(
         .clk(clk_i),
-        .rst_ext_i(rst_ni)
+        .rst_ext_ni(rst_ni)
     );
 
 endmodule // tb_top_verilator