temp commit

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-03-31 18:00:19 +08:00
parent c070f0b49d
commit 9943d02600
19 changed files with 2704 additions and 2668 deletions

View File

@ -60,7 +60,12 @@ module exu(
output wire jump_flag_o, // 是否跳转标志 output wire jump_flag_o, // 是否跳转标志
output wire[31:0] jump_addr_o, // 跳转目的地址 output wire[31:0] jump_addr_o, // 跳转目的地址
//
output wire inst_valid_o,
// from idu_exu // from idu_exu
input wire inst_valid_i,
input wire[31:0] inst_i,
input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i, input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i,
input wire[31:0] dec_imm_i, input wire[31:0] dec_imm_i,
input wire[31:0] dec_pc_i, input wire[31:0] dec_pc_i,
@ -375,4 +380,6 @@ module exu(
assign mem_we_o = mem_mem_we_o; assign mem_we_o = mem_mem_we_o;
assign mem_wdata_o = mem_wdata; assign mem_wdata_o = mem_wdata;
assign inst_valid_o = hold_flag_o? 1'b0: inst_valid_i;
endmodule endmodule

View File

@ -26,6 +26,7 @@ module idu_exu(
input wire flush_i, // 流水线冲刷 input wire flush_i, // 流水线冲刷
input wire[31:0] inst_i, input wire[31:0] inst_i,
input wire inst_valid_i,
input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i, input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i,
input wire[31:0] dec_imm_i, input wire[31:0] dec_imm_i,
input wire[31:0] dec_pc_i, input wire[31:0] dec_pc_i,
@ -35,6 +36,7 @@ module idu_exu(
input wire rd_we_i, input wire rd_we_i,
output wire[31:0] inst_o, output wire[31:0] inst_o,
output wire inst_valid_o,
output wire[`DECINFO_WIDTH-1:0] dec_info_bus_o, output wire[`DECINFO_WIDTH-1:0] dec_info_bus_o,
output wire[31:0] dec_imm_o, output wire[31:0] dec_imm_o,
output wire[31:0] dec_pc_o, output wire[31:0] dec_pc_o,
@ -87,4 +89,9 @@ module idu_exu(
gen_en_dff #(32) inst_ff(clk, rst_n, en, i_inst, inst); gen_en_dff #(32) inst_ff(clk, rst_n, en, i_inst, inst);
assign inst_o = inst; assign inst_o = inst;
wire i_inst_valid = flush_i? 1'b0: inst_valid_i;
wire inst_valid;
gen_en_dff #(1) inst_valid_ff(clk, rst_n, 1'b1, i_inst_valid, inst_valid);
assign inst_valid_o = inst_valid;
endmodule endmodule

View File

@ -116,6 +116,7 @@ module ifu(
assign ibus_addr_o = pc; assign ibus_addr_o = pc;
assign pc_o = pc_r; assign pc_o = pc_r;
wire inst_valid = ifu_rsp_hsked & (~flush_i) & (~bus_switched); wire inst_valid = ifu_rsp_hsked & (~flush_i) & (~bus_switched);
assign inst_valid_o = inst_valid;
assign inst_o = inst_valid? ibus_data_i: `INST_NOP; assign inst_o = inst_valid? ibus_data_i: `INST_NOP;
assign ibus_sel_o = 4'b1111; assign ibus_sel_o = 4'b1111;

View File

@ -28,6 +28,7 @@ module ifu_idu(
input wire flush_i, // 流水线冲刷 input wire flush_i, // 流水线冲刷
input wire inst_valid_i, input wire inst_valid_i,
output wire inst_valid_o,
output wire[31:0] inst_o, // 指令内容 output wire[31:0] inst_o, // 指令内容
output wire[31:0] inst_addr_o // 指令地址 output wire[31:0] inst_addr_o // 指令地址
@ -45,4 +46,9 @@ module ifu_idu(
gen_en_dff #(32) inst_addr_ff(clk, rst_n, en, i_inst_addr, inst_addr); gen_en_dff #(32) inst_addr_ff(clk, rst_n, en, i_inst_addr, inst_addr);
assign inst_addr_o = inst_addr; assign inst_addr_o = inst_addr;
wire i_inst_valid = flush_i? 1'b0: inst_valid_i;
wire inst_valid;
gen_en_dff #(1) inst_valid_ff(clk, rst_n, 1'b1, i_inst_valid, inst_valid);
assign inst_valid_o = inst_valid;
endmodule endmodule

View File

@ -56,6 +56,7 @@ module tinyriscv_core(
wire[31:0] if_inst_o; wire[31:0] if_inst_o;
wire[31:0] if_inst_addr_o; wire[31:0] if_inst_addr_o;
wire[`INT_WIDTH-1:0] if_int_flag_o; wire[`INT_WIDTH-1:0] if_int_flag_o;
wire if_inst_valid_o;
// idu模块输出信号 // idu模块输出信号
wire[31:0] id_inst_o; wire[31:0] id_inst_o;
@ -81,6 +82,7 @@ module tinyriscv_core(
wire[31:0] ie_rs2_rdata_o; wire[31:0] ie_rs2_rdata_o;
wire[4:0] ie_rd_waddr_o; wire[4:0] ie_rd_waddr_o;
wire ie_rd_we_o; wire ie_rd_we_o;
wire ie_inst_valid_o;
// exu模块输出信号 // exu模块输出信号
wire[31:0] ex_mem_wdata_o; wire[31:0] ex_mem_wdata_o;
@ -103,6 +105,7 @@ module tinyriscv_core(
wire ex_inst_ecall_o; wire ex_inst_ecall_o;
wire ex_inst_ebreak_o; wire ex_inst_ebreak_o;
wire ex_inst_mret_o; wire ex_inst_mret_o;
wire ex_inst_valid_o;
// gpr_reg模块输出信号 // gpr_reg模块输出信号
wire[31:0] regs_rdata1_o; wire[31:0] regs_rdata1_o;
@ -207,6 +210,7 @@ module tinyriscv_core(
.stall_i(ctrl_stall_o), .stall_i(ctrl_stall_o),
.flush_i(ctrl_flush_o), .flush_i(ctrl_flush_o),
.inst_valid_i(ifetch_inst_valid_o), .inst_valid_i(ifetch_inst_valid_o),
.inst_valid_o(if_inst_valid_o),
.inst_o(if_inst_o), .inst_o(if_inst_o),
.inst_addr_o(if_inst_addr_o) .inst_addr_o(if_inst_addr_o)
); );
@ -244,6 +248,8 @@ module tinyriscv_core(
.rs2_rdata_i(id_rs2_rdata_o), .rs2_rdata_i(id_rs2_rdata_o),
.rd_waddr_i(id_rd_waddr_o), .rd_waddr_i(id_rd_waddr_o),
.rd_we_i(id_rd_we_o), .rd_we_i(id_rd_we_o),
.inst_valid_i(if_inst_valid_o),
.inst_valid_o(ie_inst_valid_o),
.inst_o(ie_inst_o), .inst_o(ie_inst_o),
.dec_info_bus_o(ie_dec_info_bus_o), .dec_info_bus_o(ie_dec_info_bus_o),
.dec_imm_o(ie_dec_imm_o), .dec_imm_o(ie_dec_imm_o),
@ -286,6 +292,9 @@ module tinyriscv_core(
.csr_wdata_o(ex_csr_wdata_o), .csr_wdata_o(ex_csr_wdata_o),
.csr_we_o(ex_csr_we_o), .csr_we_o(ex_csr_we_o),
.csr_waddr_o(ex_csr_waddr_o), .csr_waddr_o(ex_csr_waddr_o),
.inst_valid_o(ex_inst_valid_o),
.inst_valid_i(ie_inst_valid_o),
.inst_i(ie_inst_o),
.dec_info_bus_i(ie_dec_info_bus_o), .dec_info_bus_i(ie_dec_info_bus_o),
.dec_imm_i(ie_dec_imm_o), .dec_imm_i(ie_dec_imm_o),
.dec_pc_i(ie_dec_pc_o), .dec_pc_i(ie_dec_pc_o),
@ -317,7 +326,11 @@ module tinyriscv_core(
`ifdef TRACE_ENABLED `ifdef TRACE_ENABLED
tracer u_tracer( tracer u_tracer(
.clk(clk),
.rst_n(rst_n),
.inst_i(ie_inst_o),
.pc_i(ie_dec_pc_o),
.inst_valid_i(ex_inst_valid_o)
); );
`endif `endif

View File

@ -584,12 +584,14 @@ module tracer(
$display("Writing execution trace to %s", file_name); $display("Writing execution trace to %s", file_name);
file_handle = $fopen(file_name, "w"); file_handle = $fopen(file_name, "w");
$fwrite(file_handle, "Time\tCycle\tPC\tInsn\tDecoded instruction\n"); $fwrite(file_handle, "\t\t\tTime\tCycle\tPC\tInsn\tDecoded instruction\n");
end end
function automatic void printbuffer_dumpline(); function automatic void printbuffer_dumpline();
$fwrite(file_handle, "%15t\t%d\t%h\t%s\t%s", $time, cycle, pc_i, inst_i, decoded_str); string insn_str = $sformatf("%h", inst_i);
$fwrite(file_handle, "%15t\t%d\t%h\t%s\t%s", $time, cycle, pc_i, insn_str, decoded_str);
$fwrite(file_handle, "\n"); $fwrite(file_handle, "\n");
endfunction endfunction