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add mul instruction 

Signed-off-by: Blue Liang <liangkangnan@163.com>
pull/1/head
Blue Liang 2020-01-02 16:12:13 +08:00
parent 67a001ea29
commit 97efd66e78
25 changed files with 2579 additions and 153 deletions
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9
rtl/defines.v
View File

@ -55,8 +55,9 @@
`define INST_SH 3'b001
`define INST_SW 3'b010
// R and M type inst
`define INST_TYPE_R_M 7'b0110011
// R type inst
`define INST_TYPE_R 7'b0110011
`define INST_ADD_SUB 3'b000
`define INST_SLL 3'b001
`define INST_SLT 3'b010
@ -65,6 +66,11 @@
`define INST_SR 3'b101
`define INST_OR 3'b110
`define INST_AND 3'b111
// M type inst
`define INST_MUL 3'b000
`define INST_MULH 3'b001
`define INST_MULHSU 3'b010
`define INST_MULHU 3'b011
// J type inst
`define INST_JAL 7'b1101111
@ -93,6 +99,7 @@
// common regs
`define RegAddrBus 4:0
`define RegBus 31:0
`define DoubleRegBus 63:0
`define RegWidth 32
`define RegNum 32 // reg count
`define RegNumLog2 5

181
rtl/ex.v
View File

@ -52,12 +52,28 @@ module ex (
wire[4:0] shift_bits;
reg[1:0] sram_raddr_index;
reg[1:0] sram_waddr_index;
wire[`DoubleRegBus] mul_temp;
wire[`DoubleRegBus] mulh_temp;
wire[`DoubleRegBus] mulh_temp_invert;
wire[`DoubleRegBus] mulhsu_temp;
wire[`DoubleRegBus] mulhsu_temp_invert;
wire[`RegBus] op1_mul;
wire[`RegBus] op2_mul;
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]};
assign shift_bits = inst_i[24:20];
assign mul_temp = reg1_rdata_i * reg2_rdata_i;
assign op1_mul = (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i;
assign op2_mul = (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i;
assign mulhsu_temp = op1_mul * reg2_rdata_i;
assign mulh_temp = op1_mul * op2_mul;
assign mulhsu_temp_invert = ~mulhsu_temp + 1;
assign mulh_temp_invert = ~mulh_temp + 1;
always @ (posedge clk) begin
if (rst == `RstEnable) begin
@ -143,81 +159,114 @@ module ex (
end
endcase
end
`INST_TYPE_R: begin
case (funct3)
`INST_ADD_SUB: begin
jump_flag_o <= `JumpDisable;
if (inst_i[30] == 1'b0) begin
reg_wdata_o <= reg1_rdata_i + reg2_rdata_i;
end else begin
reg_wdata_o <= reg1_rdata_i - reg2_rdata_i;
end
end
`INST_SLL: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i << reg2_rdata_i[4:0];
end
`INST_SLT: begin
jump_flag_o <= `JumpDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
`INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3)
`INST_ADD_SUB: begin
jump_flag_o <= `JumpDisable;
if (inst_i[30] == 1'b0) begin
reg_wdata_o <= reg1_rdata_i + reg2_rdata_i;
end else begin
reg_wdata_o <= 32'h00000000;
end
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
reg_wdata_o <= 32'h00000001;
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
reg_wdata_o <= 32'h00000000;
end else begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
reg_wdata_o <= reg1_rdata_i - reg2_rdata_i;
end
end
end
`INST_SLTU: begin
jump_flag_o <= `JumpDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin
`INST_SLL: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i << reg2_rdata_i[4:0];
end
`INST_SLT: begin
jump_flag_o <= `JumpDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
end
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
reg_wdata_o <= 32'h00000001;
end else begin
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
reg_wdata_o <= 32'h00000000;
end
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
reg_wdata_o <= 32'h00000000;
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
reg_wdata_o <= 32'h00000001;
end else begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
end
end
end
end
`INST_XOR: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i ^ reg2_rdata_i;
end
`INST_SR: begin
jump_flag_o <= `JumpDisable;
if (inst_i[30] == 1'b1) begin
reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
end else begin
reg_wdata_o <= reg1_rdata_i >> reg2_rdata_i[4:0];
`INST_SLTU: begin
jump_flag_o <= `JumpDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
end
end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
reg_wdata_o <= 32'h00000000;
end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
reg_wdata_o <= 32'h00000001;
end else begin
if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata_o <= 32'h00000001;
end else begin
reg_wdata_o <= 32'h00000000;
end
end
end
end
`INST_OR: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i | reg2_rdata_i;
end
`INST_AND: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i & reg2_rdata_i;
end
endcase
`INST_XOR: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i ^ reg2_rdata_i;
end
`INST_SR: begin
jump_flag_o <= `JumpDisable;
if (inst_i[30] == 1'b1) begin
reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
end else begin
reg_wdata_o <= reg1_rdata_i >> reg2_rdata_i[4:0];
end
end
`INST_OR: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i | reg2_rdata_i;
end
`INST_AND: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= reg1_rdata_i & reg2_rdata_i;
end
endcase
end else if (funct7 == 7'b0000001) begin
case (funct3)
`INST_MUL: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= mul_temp[31:0];
end
`INST_MULHU: begin
jump_flag_o <= `JumpDisable;
reg_wdata_o <= mul_temp[63:32];
end
`INST_MULH: begin
jump_flag_o <= `JumpDisable;
if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin
reg_wdata_o <= mulh_temp[63:32];
end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin
reg_wdata_o <= mulh_temp[63:32];
end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b0)) begin
reg_wdata_o <= mulh_temp_invert[63:32];
end else begin
reg_wdata_o <= mulh_temp_invert[63:32];
end
end
`INST_MULHSU: begin
jump_flag_o <= `JumpDisable;
if (reg1_rdata_i[31] == 1'b1) begin
reg_wdata_o <= mulhsu_temp_invert[63:32];
end else begin
reg_wdata_o <= mulhsu_temp[63:32];
end
end
endcase
end
end
`INST_TYPE_L: begin
case (funct3)

221
rtl/id.v
View File

@ -46,6 +46,7 @@ module id (
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
wire[4:0] rd = inst_i[11:7];
wire[4:0] rs1 = inst_i[19:15];
wire[4:0] rs2 = inst_i[24:20];
@ -141,92 +142,140 @@ module id (
end
endcase
end
`INST_TYPE_R: begin
case (funct3)
`INST_ADD_SUB: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLL: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLT: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLTU: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_XOR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_OR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_AND: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
default: begin
inst_valid_o <= `InstInvalid;
end
endcase
`INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3)
`INST_ADD_SUB: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLL: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLT: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SLTU: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_XOR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_SR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_OR: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_AND: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
default: begin
inst_valid_o <= `InstInvalid;
end
endcase
end else if (funct7 == 7'b0000001) begin
case (funct3)
`INST_MUL: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_MULHU: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_MULH: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
`INST_MULHSU: begin
inst_valid_o <= `InstValid;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_re_o <= `ReadEnable;
reg1_raddr_o <= rs1;
reg2_re_o <= `ReadEnable;
reg2_raddr_o <= rs2;
sram_we_o <= `WriteDisable;
end
default: begin
inst_valid_o <= `InstInvalid;
end
endcase
end
end
`INST_TYPE_L: begin
case (funct3)

2
tests/isa/Makefile
View File

@ -7,6 +7,7 @@ XLEN := 32
src_dir := .
include $(src_dir)/rv32ui/Makefrag
include $(src_dir)/rv32um/Makefrag
default: all
@ -49,6 +50,7 @@ tests += $$($(1)_tests)
endef
$(eval $(call compile_template,rv32ui,-march=rv32i -mabi=ilp32))
$(eval $(call compile_template,rv32um,-march=rv32im -mabi=ilp32))
tests_verilog = $(addsuffix .verilog, $(tests))

BIN
tests/isa/generated/rv32um-p-mul Normal file
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BIN
tests/isa/generated/rv32um-p-mul.bin Normal file
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410
tests/isa/generated/rv32um-p-mul.dump Normal file
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@ -0,0 +1,410 @@
generated/rv32um-p-mul: file format elf32-littleriscv
Disassembly of section .text.init:
00000000 <_start>:
0: 00000d13 li s10,0
4: 00000d93 li s11,0
00000008 <test_32>:
8: 000080b7 lui ra,0x8
c: e0008093 addi ra,ra,-512 # 7e00 <begin_signature+0x6e00>
10: b6db7137 lui sp,0xb6db7
14: db710113 addi sp,sp,-585 # b6db6db7 <begin_signature+0xb6db5db7>
18: 02208f33 mul t5,ra,sp
1c: 00001eb7 lui t4,0x1
20: 200e8e93 addi t4,t4,512 # 1200 <begin_signature+0x200>
24: 02000193 li gp,32
28: 4bdf1463 bne t5,t4,4d0 <fail>
0000002c <test_33>:
2c: 000080b7 lui ra,0x8
30: fc008093 addi ra,ra,-64 # 7fc0 <begin_signature+0x6fc0>
34: b6db7137 lui sp,0xb6db7
38: db710113 addi sp,sp,-585 # b6db6db7 <begin_signature+0xb6db5db7>
3c: 02208f33 mul t5,ra,sp
40: 00001eb7 lui t4,0x1
44: 240e8e93 addi t4,t4,576 # 1240 <begin_signature+0x240>
48: 02100193 li gp,33
4c: 49df1263 bne t5,t4,4d0 <fail>
00000050 <test_2>:
50: 00000093 li ra,0
54: 00000113 li sp,0
58: 02208f33 mul t5,ra,sp
5c: 00000e93 li t4,0
60: 00200193 li gp,2
64: 47df1663 bne t5,t4,4d0 <fail>
00000068 <test_3>:
68: 00100093 li ra,1
6c: 00100113 li sp,1
70: 02208f33 mul t5,ra,sp
74: 00100e93 li t4,1
78: 00300193 li gp,3
7c: 45df1a63 bne t5,t4,4d0 <fail>
00000080 <test_4>:
80: 00300093 li ra,3
84: 00700113 li sp,7
88: 02208f33 mul t5,ra,sp
8c: 01500e93 li t4,21
90: 00400193 li gp,4
94: 43df1e63 bne t5,t4,4d0 <fail>
00000098 <test_5>:
98: 00000093 li ra,0
9c: ffff8137 lui sp,0xffff8
a0: 02208f33 mul t5,ra,sp
a4: 00000e93 li t4,0
a8: 00500193 li gp,5
ac: 43df1263 bne t5,t4,4d0 <fail>
000000b0 <test_6>:
b0: 800000b7 lui ra,0x80000
b4: 00000113 li sp,0
b8: 02208f33 mul t5,ra,sp
bc: 00000e93 li t4,0
c0: 00600193 li gp,6
c4: 41df1663 bne t5,t4,4d0 <fail>
000000c8 <test_7>:
c8: 800000b7 lui ra,0x80000
cc: ffff8137 lui sp,0xffff8
d0: 02208f33 mul t5,ra,sp
d4: 00000e93 li t4,0
d8: 00700193 li gp,7
dc: 3fdf1a63 bne t5,t4,4d0 <fail>
000000e0 <test_30>:
e0: aaaab0b7 lui ra,0xaaaab
e4: aab08093 addi ra,ra,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
e8: 00030137 lui sp,0x30
ec: e7d10113 addi sp,sp,-387 # 2fe7d <begin_signature+0x2ee7d>
f0: 02208f33 mul t5,ra,sp
f4: 00010eb7 lui t4,0x10
f8: f7fe8e93 addi t4,t4,-129 # ff7f <begin_signature+0xef7f>
fc: 01e00193 li gp,30
100: 3ddf1863 bne t5,t4,4d0 <fail>
00000104 <test_31>:
104: 000300b7 lui ra,0x30
108: e7d08093 addi ra,ra,-387 # 2fe7d <begin_signature+0x2ee7d>
10c: aaaab137 lui sp,0xaaaab
110: aab10113 addi sp,sp,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
114: 02208f33 mul t5,ra,sp
118: 00010eb7 lui t4,0x10
11c: f7fe8e93 addi t4,t4,-129 # ff7f <begin_signature+0xef7f>
120: 01f00193 li gp,31
124: 3bdf1663 bne t5,t4,4d0 <fail>
00000128 <test_34>:
128: ff0000b7 lui ra,0xff000
12c: ff000137 lui sp,0xff000
130: 02208f33 mul t5,ra,sp
134: 00000e93 li t4,0
138: 02200193 li gp,34
13c: 39df1a63 bne t5,t4,4d0 <fail>
00000140 <test_35>:
140: fff00093 li ra,-1
144: fff00113 li sp,-1
148: 02208f33 mul t5,ra,sp
14c: 00100e93 li t4,1
150: 02300193 li gp,35
154: 37df1e63 bne t5,t4,4d0 <fail>
00000158 <test_36>:
158: fff00093 li ra,-1
15c: 00100113 li sp,1
160: 02208f33 mul t5,ra,sp
164: fff00e93 li t4,-1
168: 02400193 li gp,36
16c: 37df1263 bne t5,t4,4d0 <fail>
00000170 <test_37>:
170: 00100093 li ra,1
174: fff00113 li sp,-1
178: 02208f33 mul t5,ra,sp
17c: fff00e93 li t4,-1
180: 02500193 li gp,37
184: 35df1663 bne t5,t4,4d0 <fail>
00000188 <test_8>:
188: 00d00093 li ra,13
18c: 00b00113 li sp,11
190: 022080b3 mul ra,ra,sp
194: 08f00e93 li t4,143
198: 00800193 li gp,8
19c: 33d09a63 bne ra,t4,4d0 <fail>
000001a0 <test_9>:
1a0: 00e00093 li ra,14
1a4: 00b00113 li sp,11
1a8: 02208133 mul sp,ra,sp
1ac: 09a00e93 li t4,154
1b0: 00900193 li gp,9
1b4: 31d11e63 bne sp,t4,4d0 <fail>
000001b8 <test_10>:
1b8: 00d00093 li ra,13
1bc: 021080b3 mul ra,ra,ra
1c0: 0a900e93 li t4,169
1c4: 00a00193 li gp,10
1c8: 31d09463 bne ra,t4,4d0 <fail>
000001cc <test_11>:
1cc: 00000213 li tp,0
1d0: 00d00093 li ra,13
1d4: 00b00113 li sp,11
1d8: 02208f33 mul t5,ra,sp
1dc: 000f0313 mv t1,t5
1e0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1e4: 00200293 li t0,2
1e8: fe5214e3 bne tp,t0,1d0 <test_11+0x4>
1ec: 08f00e93 li t4,143
1f0: 00b00193 li gp,11
1f4: 2dd31e63 bne t1,t4,4d0 <fail>
000001f8 <test_12>:
1f8: 00000213 li tp,0
1fc: 00e00093 li ra,14
200: 00b00113 li sp,11
204: 02208f33 mul t5,ra,sp
208: 00000013 nop
20c: 000f0313 mv t1,t5
210: 00120213 addi tp,tp,1 # 1 <_start+0x1>
214: 00200293 li t0,2
218: fe5212e3 bne tp,t0,1fc <test_12+0x4>
21c: 09a00e93 li t4,154
220: 00c00193 li gp,12
224: 2bd31663 bne t1,t4,4d0 <fail>
00000228 <test_13>:
228: 00000213 li tp,0
22c: 00f00093 li ra,15
230: 00b00113 li sp,11
234: 02208f33 mul t5,ra,sp
238: 00000013 nop
23c: 00000013 nop
240: 000f0313 mv t1,t5
244: 00120213 addi tp,tp,1 # 1 <_start+0x1>
248: 00200293 li t0,2
24c: fe5210e3 bne tp,t0,22c <test_13+0x4>
250: 0a500e93 li t4,165
254: 00d00193 li gp,13
258: 27d31c63 bne t1,t4,4d0 <fail>
0000025c <test_14>:
25c: 00000213 li tp,0
260: 00d00093 li ra,13
264: 00b00113 li sp,11
268: 02208f33 mul t5,ra,sp
26c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
270: 00200293 li t0,2
274: fe5216e3 bne tp,t0,260 <test_14+0x4>
278: 08f00e93 li t4,143
27c: 00e00193 li gp,14
280: 25df1863 bne t5,t4,4d0 <fail>
00000284 <test_15>:
284: 00000213 li tp,0
288: 00e00093 li ra,14
28c: 00b00113 li sp,11
290: 00000013 nop
294: 02208f33 mul t5,ra,sp
298: 00120213 addi tp,tp,1 # 1 <_start+0x1>
29c: 00200293 li t0,2
2a0: fe5214e3 bne tp,t0,288 <test_15+0x4>
2a4: 09a00e93 li t4,154
2a8: 00f00193 li gp,15
2ac: 23df1263 bne t5,t4,4d0 <fail>
000002b0 <test_16>:
2b0: 00000213 li tp,0
2b4: 00f00093 li ra,15
2b8: 00b00113 li sp,11
2bc: 00000013 nop
2c0: 00000013 nop
2c4: 02208f33 mul t5,ra,sp
2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2cc: 00200293 li t0,2
2d0: fe5212e3 bne tp,t0,2b4 <test_16+0x4>
2d4: 0a500e93 li t4,165
2d8: 01000193 li gp,16
2dc: 1fdf1a63 bne t5,t4,4d0 <fail>
000002e0 <test_17>:
2e0: 00000213 li tp,0
2e4: 00d00093 li ra,13
2e8: 00000013 nop
2ec: 00b00113 li sp,11
2f0: 02208f33 mul t5,ra,sp
2f4: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2f8: 00200293 li t0,2
2fc: fe5214e3 bne tp,t0,2e4 <test_17+0x4>
300: 08f00e93 li t4,143
304: 01100193 li gp,17
308: 1ddf1463 bne t5,t4,4d0 <fail>
0000030c <test_18>:
30c: 00000213 li tp,0
310: 00e00093 li ra,14
314: 00000013 nop
318: 00b00113 li sp,11
31c: 00000013 nop
320: 02208f33 mul t5,ra,sp
324: 00120213 addi tp,tp,1 # 1 <_start+0x1>
328: 00200293 li t0,2
32c: fe5212e3 bne tp,t0,310 <test_18+0x4>
330: 09a00e93 li t4,154
334: 01200193 li gp,18
338: 19df1c63 bne t5,t4,4d0 <fail>
0000033c <test_19>:
33c: 00000213 li tp,0
340: 00f00093 li ra,15
344: 00000013 nop
348: 00000013 nop
34c: 00b00113 li sp,11
350: 02208f33 mul t5,ra,sp
354: 00120213 addi tp,tp,1 # 1 <_start+0x1>
358: 00200293 li t0,2
35c: fe5212e3 bne tp,t0,340 <test_19+0x4>
360: 0a500e93 li t4,165
364: 01300193 li gp,19
368: 17df1463 bne t5,t4,4d0 <fail>
0000036c <test_20>:
36c: 00000213 li tp,0
370: 00b00113 li sp,11
374: 00d00093 li ra,13
378: 02208f33 mul t5,ra,sp
37c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
380: 00200293 li t0,2
384: fe5216e3 bne tp,t0,370 <test_20+0x4>
388: 08f00e93 li t4,143
38c: 01400193 li gp,20
390: 15df1063 bne t5,t4,4d0 <fail>
00000394 <test_21>:
394: 00000213 li tp,0
398: 00b00113 li sp,11
39c: 00e00093 li ra,14
3a0: 00000013 nop
3a4: 02208f33 mul t5,ra,sp
3a8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3ac: 00200293 li t0,2
3b0: fe5214e3 bne tp,t0,398 <test_21+0x4>
3b4: 09a00e93 li t4,154
3b8: 01500193 li gp,21
3bc: 11df1a63 bne t5,t4,4d0 <fail>
000003c0 <test_22>:
3c0: 00000213 li tp,0
3c4: 00b00113 li sp,11
3c8: 00f00093 li ra,15
3cc: 00000013 nop
3d0: 00000013 nop
3d4: 02208f33 mul t5,ra,sp
3d8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3dc: 00200293 li t0,2
3e0: fe5212e3 bne tp,t0,3c4 <test_22+0x4>
3e4: 0a500e93 li t4,165
3e8: 01600193 li gp,22
3ec: 0fdf1263 bne t5,t4,4d0 <fail>
000003f0 <test_23>:
3f0: 00000213 li tp,0
3f4: 00b00113 li sp,11
3f8: 00000013 nop
3fc: 00d00093 li ra,13
400: 02208f33 mul t5,ra,sp
404: 00120213 addi tp,tp,1 # 1 <_start+0x1>
408: 00200293 li t0,2
40c: fe5214e3 bne tp,t0,3f4 <test_23+0x4>
410: 08f00e93 li t4,143
414: 01700193 li gp,23
418: 0bdf1c63 bne t5,t4,4d0 <fail>
0000041c <test_24>:
41c: 00000213 li tp,0
420: 00b00113 li sp,11
424: 00000013 nop
428: 00e00093 li ra,14
42c: 00000013 nop
430: 02208f33 mul t5,ra,sp
434: 00120213 addi tp,tp,1 # 1 <_start+0x1>
438: 00200293 li t0,2
43c: fe5212e3 bne tp,t0,420 <test_24+0x4>
440: 09a00e93 li t4,154
444: 01800193 li gp,24
448: 09df1463 bne t5,t4,4d0 <fail>
0000044c <test_25>:
44c: 00000213 li tp,0
450: 00b00113 li sp,11
454: 00000013 nop
458: 00000013 nop
45c: 00f00093 li ra,15
460: 02208f33 mul t5,ra,sp
464: 00120213 addi tp,tp,1 # 1 <_start+0x1>
468: 00200293 li t0,2
46c: fe5212e3 bne tp,t0,450 <test_25+0x4>
470: 0a500e93 li t4,165
474: 01900193 li gp,25
478: 05df1c63 bne t5,t4,4d0 <fail>
0000047c <test_26>:
47c: 01f00093 li ra,31
480: 02100133 mul sp,zero,ra
484: 00000e93 li t4,0
488: 01a00193 li gp,26
48c: 05d11263 bne sp,t4,4d0 <fail>
00000490 <test_27>:
490: 02000093 li ra,32
494: 02008133 mul sp,ra,zero
498: 00000e93 li t4,0
49c: 01b00193 li gp,27
4a0: 03d11863 bne sp,t4,4d0 <fail>
000004a4 <test_28>:
4a4: 020000b3 mul ra,zero,zero
4a8: 00000e93 li t4,0
4ac: 01c00193 li gp,28
4b0: 03d09063 bne ra,t4,4d0 <fail>
000004b4 <test_29>:
4b4: 02100093 li ra,33
4b8: 02200113 li sp,34
4bc: 02208033 mul zero,ra,sp
4c0: 00000e93 li t4,0
4c4: 01d00193 li gp,29
4c8: 01d01463 bne zero,t4,4d0 <fail>
4cc: 00301863 bne zero,gp,4dc <pass>
000004d0 <fail>:
4d0: 00100d13 li s10,1
4d4: 00000d93 li s11,0
000004d8 <loop_fail>:
4d8: 0000006f j 4d8 <loop_fail>
000004dc <pass>:
4dc: 00100d13 li s10,1
4e0: 00100d93 li s11,1
000004e4 <loop_pass>:
4e4: 0000006f j 4e4 <loop_pass>
...
Disassembly of section .tohost:
00000540 <tohost>:
...
00000580 <fromhost>:
...

88
tests/isa/generated/rv32um-p-mul.verilog Normal file
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@ -0,0 +1,88 @@
@00000000
13 0D 00 00 93 0D 00 00 B7 80 00 00 93 80 00 E0
37 71 DB B6 13 01 71 DB 33 8F 20 02 B7 1E 00 00
93 8E 0E 20 93 01 00 02 63 14 DF 4B B7 80 00 00
93 80 00 FC 37 71 DB B6 13 01 71 DB 33 8F 20 02
B7 1E 00 00 93 8E 0E 24 93 01 10 02 63 12 DF 49
93 00 00 00 13 01 00 00 33 8F 20 02 93 0E 00 00
93 01 20 00 63 16 DF 47 93 00 10 00 13 01 10 00
33 8F 20 02 93 0E 10 00 93 01 30 00 63 1A DF 45
93 00 30 00 13 01 70 00 33 8F 20 02 93 0E 50 01
93 01 40 00 63 1E DF 43 93 00 00 00 37 81 FF FF
33 8F 20 02 93 0E 00 00 93 01 50 00 63 12 DF 43
B7 00 00 80 13 01 00 00 33 8F 20 02 93 0E 00 00
93 01 60 00 63 16 DF 41 B7 00 00 80 37 81 FF FF
33 8F 20 02 93 0E 00 00 93 01 70 00 63 1A DF 3F
B7 B0 AA AA 93 80 B0 AA 37 01 03 00 13 01 D1 E7
33 8F 20 02 B7 0E 01 00 93 8E FE F7 93 01 E0 01
63 18 DF 3D B7 00 03 00 93 80 D0 E7 37 B1 AA AA
13 01 B1 AA 33 8F 20 02 B7 0E 01 00 93 8E FE F7
93 01 F0 01 63 16 DF 3B B7 00 00 FF 37 01 00 FF
33 8F 20 02 93 0E 00 00 93 01 20 02 63 1A DF 39
93 00 F0 FF 13 01 F0 FF 33 8F 20 02 93 0E 10 00
93 01 30 02 63 1E DF 37 93 00 F0 FF 13 01 10 00
33 8F 20 02 93 0E F0 FF 93 01 40 02 63 12 DF 37
93 00 10 00 13 01 F0 FF 33 8F 20 02 93 0E F0 FF
93 01 50 02 63 16 DF 35 93 00 D0 00 13 01 B0 00
B3 80 20 02 93 0E F0 08 93 01 80 00 63 9A D0 33
93 00 E0 00 13 01 B0 00 33 81 20 02 93 0E A0 09
93 01 90 00 63 1E D1 31 93 00 D0 00 B3 80 10 02
93 0E 90 0A 93 01 A0 00 63 94 D0 31 13 02 00 00
93 00 D0 00 13 01 B0 00 33 8F 20 02 13 03 0F 00
13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E F0 08
93 01 B0 00 63 1E D3 2D 13 02 00 00 93 00 E0 00
13 01 B0 00 33 8F 20 02 13 00 00 00 13 03 0F 00
13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E A0 09
93 01 C0 00 63 16 D3 2B 13 02 00 00 93 00 F0 00
13 01 B0 00 33 8F 20 02 13 00 00 00 13 00 00 00
13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE
93 0E 50 0A 93 01 D0 00 63 1C D3 27 13 02 00 00
93 00 D0 00 13 01 B0 00 33 8F 20 02 13 02 12 00
93 02 20 00 E3 16 52 FE 93 0E F0 08 93 01 E0 00
63 18 DF 25 13 02 00 00 93 00 E0 00 13 01 B0 00
13 00 00 00 33 8F 20 02 13 02 12 00 93 02 20 00
E3 14 52 FE 93 0E A0 09 93 01 F0 00 63 12 DF 23
13 02 00 00 93 00 F0 00 13 01 B0 00 13 00 00 00
13 00 00 00 33 8F 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE 93 0E 50 0A 93 01 00 01 63 1A DF 1F
13 02 00 00 93 00 D0 00 13 00 00 00 13 01 B0 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 14 52 FE
93 0E F0 08 93 01 10 01 63 14 DF 1D 13 02 00 00
93 00 E0 00 13 00 00 00 13 01 B0 00 13 00 00 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E A0 09 93 01 20 01 63 1C DF 19 13 02 00 00
93 00 F0 00 13 00 00 00 13 00 00 00 13 01 B0 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E 50 0A 93 01 30 01 63 14 DF 17 13 02 00 00
13 01 B0 00 93 00 D0 00 33 8F 20 02 13 02 12 00
93 02 20 00 E3 16 52 FE 93 0E F0 08 93 01 40 01
63 10 DF 15 13 02 00 00 13 01 B0 00 93 00 E0 00
13 00 00 00 33 8F 20 02 13 02 12 00 93 02 20 00
E3 14 52 FE 93 0E A0 09 93 01 50 01 63 1A DF 11
13 02 00 00 13 01 B0 00 93 00 F0 00 13 00 00 00
13 00 00 00 33 8F 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE 93 0E 50 0A 93 01 60 01 63 12 DF 0F
13 02 00 00 13 01 B0 00 13 00 00 00 93 00 D0 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 14 52 FE
93 0E F0 08 93 01 70 01 63 1C DF 0B 13 02 00 00
13 01 B0 00 13 00 00 00 93 00 E0 00 13 00 00 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E A0 09 93 01 80 01 63 14 DF 09 13 02 00 00
13 01 B0 00 13 00 00 00 13 00 00 00 93 00 F0 00
33 8F 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
93 0E 50 0A 93 01 90 01 63 1C DF 05 93 00 F0 01
33 01 10 02 93 0E 00 00 93 01 A0 01 63 12 D1 05
93 00 00 02 33 81 00 02 93 0E 00 00 93 01 B0 01
63 18 D1 03 B3 00 00 02 93 0E 00 00 93 01 C0 01
63 90 D0 03 93 00 10 02 13 01 20 02 33 80 20 02
93 0E 00 00 93 01 D0 01 63 14 D0 01 63 18 30 00
13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00
93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
@00000540
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

BIN
tests/isa/generated/rv32um-p-mulh Normal file
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BIN
tests/isa/generated/rv32um-p-mulh.bin Normal file
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406
tests/isa/generated/rv32um-p-mulh.dump Normal file
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generated/rv32um-p-mulh: file format elf32-littleriscv
Disassembly of section .text.init:
00000000 <_start>:
0: 00000d13 li s10,0
4: 00000d93 li s11,0
00000008 <test_2>:
8: 00000093 li ra,0
c: 00000113 li sp,0
10: 02209f33 mulh t5,ra,sp
14: 00000e93 li t4,0
18: 00200193 li gp,2
1c: 4bdf1a63 bne t5,t4,4d0 <fail>
00000020 <test_3>:
20: 00100093 li ra,1
24: 00100113 li sp,1
28: 02209f33 mulh t5,ra,sp
2c: 00000e93 li t4,0
30: 00300193 li gp,3
34: 49df1e63 bne t5,t4,4d0 <fail>
00000038 <test_4>:
38: 00300093 li ra,3
3c: 00700113 li sp,7
40: 02209f33 mulh t5,ra,sp
44: 00000e93 li t4,0
48: 00400193 li gp,4
4c: 49df1263 bne t5,t4,4d0 <fail>
00000050 <test_5>:
50: 00000093 li ra,0
54: ffff8137 lui sp,0xffff8
58: 02209f33 mulh t5,ra,sp
5c: 00000e93 li t4,0
60: 00500193 li gp,5
64: 47df1663 bne t5,t4,4d0 <fail>
00000068 <test_6>:
68: 800000b7 lui ra,0x80000
6c: 00000113 li sp,0
70: 02209f33 mulh t5,ra,sp
74: 00000e93 li t4,0
78: 00600193 li gp,6
7c: 45df1a63 bne t5,t4,4d0 <fail>
00000080 <test_7>:
80: 800000b7 lui ra,0x80000
84: 00000113 li sp,0
88: 02209f33 mulh t5,ra,sp
8c: 00000e93 li t4,0
90: 00700193 li gp,7
94: 43df1e63 bne t5,t4,4d0 <fail>
00000098 <test_30>:
98: aaaab0b7 lui ra,0xaaaab
9c: aab08093 addi ra,ra,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
a0: 00030137 lui sp,0x30
a4: e7d10113 addi sp,sp,-387 # 2fe7d <begin_signature+0x2ee7d>
a8: 02209f33 mulh t5,ra,sp
ac: ffff0eb7 lui t4,0xffff0
b0: 081e8e93 addi t4,t4,129 # ffff0081 <begin_signature+0xfffef081>
b4: 01e00193 li gp,30
b8: 41df1c63 bne t5,t4,4d0 <fail>
000000bc <test_31>:
bc: 000300b7 lui ra,0x30
c0: e7d08093 addi ra,ra,-387 # 2fe7d <begin_signature+0x2ee7d>
c4: aaaab137 lui sp,0xaaaab
c8: aab10113 addi sp,sp,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
cc: 02209f33 mulh t5,ra,sp
d0: ffff0eb7 lui t4,0xffff0
d4: 081e8e93 addi t4,t4,129 # ffff0081 <begin_signature+0xfffef081>
d8: 01f00193 li gp,31
dc: 3fdf1a63 bne t5,t4,4d0 <fail>
000000e0 <test_32>:
e0: ff0000b7 lui ra,0xff000
e4: ff000137 lui sp,0xff000
e8: 02209f33 mulh t5,ra,sp
ec: 00010eb7 lui t4,0x10
f0: 02000193 li gp,32
f4: 3ddf1e63 bne t5,t4,4d0 <fail>
000000f8 <test_33>:
f8: fff00093 li ra,-1
fc: fff00113 li sp,-1
100: 02209f33 mulh t5,ra,sp
104: 00000e93 li t4,0
108: 02100193 li gp,33
10c: 3ddf1263 bne t5,t4,4d0 <fail>
00000110 <test_34>:
110: fff00093 li ra,-1
114: 00100113 li sp,1
118: 02209f33 mulh t5,ra,sp
11c: fff00e93 li t4,-1
120: 02200193 li gp,34
124: 3bdf1663 bne t5,t4,4d0 <fail>
00000128 <test_35>:
128: 00100093 li ra,1
12c: fff00113 li sp,-1
130: 02209f33 mulh t5,ra,sp
134: fff00e93 li t4,-1
138: 02300193 li gp,35
13c: 39df1a63 bne t5,t4,4d0 <fail>
00000140 <test_8>:
140: 00d000b7 lui ra,0xd00
144: 00b00137 lui sp,0xb00
148: 022090b3 mulh ra,ra,sp
14c: 00009eb7 lui t4,0x9
150: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
154: 00800193 li gp,8
158: 37d09c63 bne ra,t4,4d0 <fail>
0000015c <test_9>:
15c: 00e000b7 lui ra,0xe00
160: 00b00137 lui sp,0xb00
164: 02209133 mulh sp,ra,sp
168: 0000aeb7 lui t4,0xa
16c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
170: 00900193 li gp,9
174: 35d11e63 bne sp,t4,4d0 <fail>
00000178 <test_10>:
178: 00d000b7 lui ra,0xd00
17c: 021090b3 mulh ra,ra,ra
180: 0000beb7 lui t4,0xb
184: 900e8e93 addi t4,t4,-1792 # a900 <begin_signature+0x9900>
188: 00a00193 li gp,10
18c: 35d09263 bne ra,t4,4d0 <fail>
00000190 <test_11>:
190: 00000213 li tp,0
194: 00d000b7 lui ra,0xd00
198: 00b00137 lui sp,0xb00
19c: 02209f33 mulh t5,ra,sp
1a0: 000f0313 mv t1,t5
1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1a8: 00200293 li t0,2
1ac: fe5214e3 bne tp,t0,194 <test_11+0x4>
1b0: 00009eb7 lui t4,0x9
1b4: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
1b8: 00b00193 li gp,11
1bc: 31d31a63 bne t1,t4,4d0 <fail>
000001c0 <test_12>:
1c0: 00000213 li tp,0
1c4: 00e000b7 lui ra,0xe00
1c8: 00b00137 lui sp,0xb00
1cc: 02209f33 mulh t5,ra,sp
1d0: 00000013 nop
1d4: 000f0313 mv t1,t5
1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1dc: 00200293 li t0,2
1e0: fe5212e3 bne tp,t0,1c4 <test_12+0x4>
1e4: 0000aeb7 lui t4,0xa
1e8: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
1ec: 00c00193 li gp,12
1f0: 2fd31063 bne t1,t4,4d0 <fail>
000001f4 <test_13>:
1f4: 00000213 li tp,0
1f8: 00f000b7 lui ra,0xf00
1fc: 00b00137 lui sp,0xb00
200: 02209f33 mulh t5,ra,sp
204: 00000013 nop
208: 00000013 nop
20c: 000f0313 mv t1,t5
210: 00120213 addi tp,tp,1 # 1 <_start+0x1>
214: 00200293 li t0,2
218: fe5210e3 bne tp,t0,1f8 <test_13+0x4>
21c: 0000aeb7 lui t4,0xa
220: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
224: 00d00193 li gp,13
228: 2bd31463 bne t1,t4,4d0 <fail>
0000022c <test_14>:
22c: 00000213 li tp,0
230: 00d000b7 lui ra,0xd00
234: 00b00137 lui sp,0xb00
238: 02209f33 mulh t5,ra,sp
23c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
240: 00200293 li t0,2
244: fe5216e3 bne tp,t0,230 <test_14+0x4>
248: 00009eb7 lui t4,0x9
24c: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
250: 00e00193 li gp,14
254: 27df1e63 bne t5,t4,4d0 <fail>
00000258 <test_15>:
258: 00000213 li tp,0
25c: 00e000b7 lui ra,0xe00
260: 00b00137 lui sp,0xb00
264: 00000013 nop
268: 02209f33 mulh t5,ra,sp
26c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
270: 00200293 li t0,2
274: fe5214e3 bne tp,t0,25c <test_15+0x4>
278: 0000aeb7 lui t4,0xa
27c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
280: 00f00193 li gp,15
284: 25df1663 bne t5,t4,4d0 <fail>
00000288 <test_16>:
288: 00000213 li tp,0
28c: 00f000b7 lui ra,0xf00
290: 00b00137 lui sp,0xb00
294: 00000013 nop
298: 00000013 nop
29c: 02209f33 mulh t5,ra,sp
2a0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2a4: 00200293 li t0,2
2a8: fe5212e3 bne tp,t0,28c <test_16+0x4>
2ac: 0000aeb7 lui t4,0xa
2b0: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
2b4: 01000193 li gp,16
2b8: 21df1c63 bne t5,t4,4d0 <fail>
000002bc <test_17>:
2bc: 00000213 li tp,0
2c0: 00d000b7 lui ra,0xd00
2c4: 00000013 nop
2c8: 00b00137 lui sp,0xb00
2cc: 02209f33 mulh t5,ra,sp
2d0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2d4: 00200293 li t0,2
2d8: fe5214e3 bne tp,t0,2c0 <test_17+0x4>
2dc: 00009eb7 lui t4,0x9
2e0: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
2e4: 01100193 li gp,17
2e8: 1fdf1463 bne t5,t4,4d0 <fail>
000002ec <test_18>:
2ec: 00000213 li tp,0
2f0: 00e000b7 lui ra,0xe00
2f4: 00000013 nop
2f8: 00b00137 lui sp,0xb00
2fc: 00000013 nop
300: 02209f33 mulh t5,ra,sp
304: 00120213 addi tp,tp,1 # 1 <_start+0x1>
308: 00200293 li t0,2
30c: fe5212e3 bne tp,t0,2f0 <test_18+0x4>
310: 0000aeb7 lui t4,0xa
314: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
318: 01200193 li gp,18
31c: 1bdf1a63 bne t5,t4,4d0 <fail>
00000320 <test_19>:
320: 00000213 li tp,0
324: 00f000b7 lui ra,0xf00
328: 00000013 nop
32c: 00000013 nop
330: 00b00137 lui sp,0xb00
334: 02209f33 mulh t5,ra,sp
338: 00120213 addi tp,tp,1 # 1 <_start+0x1>
33c: 00200293 li t0,2
340: fe5212e3 bne tp,t0,324 <test_19+0x4>
344: 0000aeb7 lui t4,0xa
348: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
34c: 01300193 li gp,19
350: 19df1063 bne t5,t4,4d0 <fail>
00000354 <test_20>:
354: 00000213 li tp,0
358: 00b00137 lui sp,0xb00
35c: 00d000b7 lui ra,0xd00
360: 02209f33 mulh t5,ra,sp
364: 00120213 addi tp,tp,1 # 1 <_start+0x1>
368: 00200293 li t0,2
36c: fe5216e3 bne tp,t0,358 <test_20+0x4>
370: 00009eb7 lui t4,0x9
374: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
378: 01400193 li gp,20
37c: 15df1a63 bne t5,t4,4d0 <fail>
00000380 <test_21>:
380: 00000213 li tp,0
384: 00b00137 lui sp,0xb00
388: 00e000b7 lui ra,0xe00
38c: 00000013 nop
390: 02209f33 mulh t5,ra,sp
394: 00120213 addi tp,tp,1 # 1 <_start+0x1>
398: 00200293 li t0,2
39c: fe5214e3 bne tp,t0,384 <test_21+0x4>
3a0: 0000aeb7 lui t4,0xa
3a4: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
3a8: 01500193 li gp,21
3ac: 13df1263 bne t5,t4,4d0 <fail>
000003b0 <test_22>:
3b0: 00000213 li tp,0
3b4: 00b00137 lui sp,0xb00
3b8: 00f000b7 lui ra,0xf00
3bc: 00000013 nop
3c0: 00000013 nop
3c4: 02209f33 mulh t5,ra,sp
3c8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3cc: 00200293 li t0,2
3d0: fe5212e3 bne tp,t0,3b4 <test_22+0x4>
3d4: 0000aeb7 lui t4,0xa
3d8: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
3dc: 01600193 li gp,22
3e0: 0fdf1863 bne t5,t4,4d0 <fail>
000003e4 <test_23>:
3e4: 00000213 li tp,0
3e8: 00b00137 lui sp,0xb00
3ec: 00000013 nop
3f0: 00d000b7 lui ra,0xd00
3f4: 02209f33 mulh t5,ra,sp
3f8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3fc: 00200293 li t0,2
400: fe5214e3 bne tp,t0,3e8 <test_23+0x4>
404: 00009eb7 lui t4,0x9
408: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
40c: 01700193 li gp,23
410: 0ddf1063 bne t5,t4,4d0 <fail>
00000414 <test_24>:
414: 00000213 li tp,0
418: 00b00137 lui sp,0xb00
41c: 00000013 nop
420: 00e000b7 lui ra,0xe00
424: 00000013 nop
428: 02209f33 mulh t5,ra,sp
42c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
430: 00200293 li t0,2
434: fe5212e3 bne tp,t0,418 <test_24+0x4>
438: 0000aeb7 lui t4,0xa
43c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
440: 01800193 li gp,24
444: 09df1663 bne t5,t4,4d0 <fail>
00000448 <test_25>:
448: 00000213 li tp,0
44c: 00b00137 lui sp,0xb00
450: 00000013 nop
454: 00000013 nop
458: 00f000b7 lui ra,0xf00
45c: 02209f33 mulh t5,ra,sp
460: 00120213 addi tp,tp,1 # 1 <_start+0x1>
464: 00200293 li t0,2
468: fe5212e3 bne tp,t0,44c <test_25+0x4>
46c: 0000aeb7 lui t4,0xa
470: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
474: 01900193 li gp,25
478: 05df1c63 bne t5,t4,4d0 <fail>
0000047c <test_26>:
47c: 7c0000b7 lui ra,0x7c000
480: 02101133 mulh sp,zero,ra
484: 00000e93 li t4,0
488: 01a00193 li gp,26
48c: 05d11263 bne sp,t4,4d0 <fail>
00000490 <test_27>:
490: 800000b7 lui ra,0x80000
494: 02009133 mulh sp,ra,zero
498: 00000e93 li t4,0
49c: 01b00193 li gp,27
4a0: 03d11863 bne sp,t4,4d0 <fail>
000004a4 <test_28>:
4a4: 020010b3 mulh ra,zero,zero
4a8: 00000e93 li t4,0
4ac: 01c00193 li gp,28
4b0: 03d09063 bne ra,t4,4d0 <fail>
000004b4 <test_29>:
4b4: 021000b7 lui ra,0x2100
4b8: 02200137 lui sp,0x2200
4bc: 02209033 mulh zero,ra,sp
4c0: 00000e93 li t4,0
4c4: 01d00193 li gp,29
4c8: 01d01463 bne zero,t4,4d0 <fail>
4cc: 00301863 bne zero,gp,4dc <pass>
000004d0 <fail>:
4d0: 00100d13 li s10,1
4d4: 00000d93 li s11,0
000004d8 <loop_fail>:
4d8: 0000006f j 4d8 <loop_fail>
000004dc <pass>:
4dc: 00100d13 li s10,1
4e0: 00100d93 li s11,1
000004e4 <loop_pass>:
4e4: 0000006f j 4e4 <loop_pass>
...
Disassembly of section .tohost:
00000540 <tohost>:
...
00000580 <fromhost>:
...

88
tests/isa/generated/rv32um-p-mulh.verilog Normal file
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@ -0,0 +1,88 @@
@00000000
13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00
33 9F 20 02 93 0E 00 00 93 01 20 00 63 1A DF 4B
93 00 10 00 13 01 10 00 33 9F 20 02 93 0E 00 00
93 01 30 00 63 1E DF 49 93 00 30 00 13 01 70 00
33 9F 20 02 93 0E 00 00 93 01 40 00 63 12 DF 49
93 00 00 00 37 81 FF FF 33 9F 20 02 93 0E 00 00
93 01 50 00 63 16 DF 47 B7 00 00 80 13 01 00 00
33 9F 20 02 93 0E 00 00 93 01 60 00 63 1A DF 45
B7 00 00 80 13 01 00 00 33 9F 20 02 93 0E 00 00
93 01 70 00 63 1E DF 43 B7 B0 AA AA 93 80 B0 AA
37 01 03 00 13 01 D1 E7 33 9F 20 02 B7 0E FF FF
93 8E 1E 08 93 01 E0 01 63 1C DF 41 B7 00 03 00
93 80 D0 E7 37 B1 AA AA 13 01 B1 AA 33 9F 20 02
B7 0E FF FF 93 8E 1E 08 93 01 F0 01 63 1A DF 3F
B7 00 00 FF 37 01 00 FF 33 9F 20 02 B7 0E 01 00
93 01 00 02 63 1E DF 3D 93 00 F0 FF 13 01 F0 FF
33 9F 20 02 93 0E 00 00 93 01 10 02 63 12 DF 3D
93 00 F0 FF 13 01 10 00 33 9F 20 02 93 0E F0 FF
93 01 20 02 63 16 DF 3B 93 00 10 00 13 01 F0 FF
33 9F 20 02 93 0E F0 FF 93 01 30 02 63 1A DF 39
B7 00 D0 00 37 01 B0 00 B3 90 20 02 B7 9E 00 00
93 8E 0E F0 93 01 80 00 63 9C D0 37 B7 00 E0 00
37 01 B0 00 33 91 20 02 B7 AE 00 00 93 8E 0E A0
93 01 90 00 63 1E D1 35 B7 00 D0 00 B3 90 10 02
B7 BE 00 00 93 8E 0E 90 93 01 A0 00 63 92 D0 35
13 02 00 00 B7 00 D0 00 37 01 B0 00 33 9F 20 02
13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 B0 00 63 1A D3 31
13 02 00 00 B7 00 E0 00 37 01 B0 00 33 9F 20 02
13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E A0 93 01 C0 00
63 10 D3 2F 13 02 00 00 B7 00 F0 00 37 01 B0 00
33 9F 20 02 13 00 00 00 13 00 00 00 13 03 0F 00
13 02 12 00 93 02 20 00 E3 10 52 FE B7 AE 00 00
93 8E 0E 50 93 01 D0 00 63 14 D3 2B 13 02 00 00
B7 00 D0 00 37 01 B0 00 33 9F 20 02 13 02 12 00
93 02 20 00 E3 16 52 FE B7 9E 00 00 93 8E 0E F0
93 01 E0 00 63 1E DF 27 13 02 00 00 B7 00 E0 00
37 01 B0 00 13 00 00 00 33 9F 20 02 13 02 12 00
93 02 20 00 E3 14 52 FE B7 AE 00 00 93 8E 0E A0
93 01 F0 00 63 16 DF 25 13 02 00 00 B7 00 F0 00
37 01 B0 00 13 00 00 00 13 00 00 00 33 9F 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 00 01 63 1C DF 21 13 02 00 00
B7 00 D0 00 13 00 00 00 37 01 B0 00 33 9F 20 02
13 02 12 00 93 02 20 00 E3 14 52 FE B7 9E 00 00
93 8E 0E F0 93 01 10 01 63 14 DF 1F 13 02 00 00
B7 00 E0 00 13 00 00 00 37 01 B0 00 13 00 00 00
33 9F 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 20 01 63 1A DF 1B
13 02 00 00 B7 00 F0 00 13 00 00 00 13 00 00 00
37 01 B0 00 33 9F 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 30 01
63 10 DF 19 13 02 00 00 37 01 B0 00 B7 00 D0 00
33 9F 20 02 13 02 12 00 93 02 20 00 E3 16 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 40 01 63 1A DF 15
13 02 00 00 37 01 B0 00 B7 00 E0 00 13 00 00 00
33 9F 20 02 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 50 01 63 12 DF 13
13 02 00 00 37 01 B0 00 B7 00 F0 00 13 00 00 00
13 00 00 00 33 9F 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 60 01
63 18 DF 0F 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 D0 00 33 9F 20 02 13 02 12 00 93 02 20 00
E3 14 52 FE B7 9E 00 00 93 8E 0E F0 93 01 70 01
63 10 DF 0D 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 E0 00 13 00 00 00 33 9F 20 02 13 02 12 00
93 02 20 00 E3 12 52 FE B7 AE 00 00 93 8E 0E A0
93 01 80 01 63 16 DF 09 13 02 00 00 37 01 B0 00
13 00 00 00 13 00 00 00 B7 00 F0 00 33 9F 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 90 01 63 1C DF 05 B7 00 00 7C
33 11 10 02 93 0E 00 00 93 01 A0 01 63 12 D1 05
B7 00 00 80 33 91 00 02 93 0E 00 00 93 01 B0 01
63 18 D1 03 B3 10 00 02 93 0E 00 00 93 01 C0 01
63 90 D0 03 B7 00 10 02 37 01 20 02 33 90 20 02
93 0E 00 00 93 01 D0 01 63 14 D0 01 63 18 30 00
13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00
93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
@00000540
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

BIN
tests/isa/generated/rv32um-p-mulhsu Normal file
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BIN
tests/isa/generated/rv32um-p-mulhsu.bin Normal file
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406
tests/isa/generated/rv32um-p-mulhsu.dump Normal file
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generated/rv32um-p-mulhsu: file format elf32-littleriscv
Disassembly of section .text.init:
00000000 <_start>:
0: 00000d13 li s10,0
4: 00000d93 li s11,0
00000008 <test_2>:
8: 00000093 li ra,0
c: 00000113 li sp,0
10: 0220af33 mulhsu t5,ra,sp
14: 00000e93 li t4,0
18: 00200193 li gp,2
1c: 4bdf1a63 bne t5,t4,4d0 <fail>
00000020 <test_3>:
20: 00100093 li ra,1
24: 00100113 li sp,1
28: 0220af33 mulhsu t5,ra,sp
2c: 00000e93 li t4,0
30: 00300193 li gp,3
34: 49df1e63 bne t5,t4,4d0 <fail>
00000038 <test_4>:
38: 00300093 li ra,3
3c: 00700113 li sp,7
40: 0220af33 mulhsu t5,ra,sp
44: 00000e93 li t4,0
48: 00400193 li gp,4
4c: 49df1263 bne t5,t4,4d0 <fail>
00000050 <test_5>:
50: 00000093 li ra,0
54: ffff8137 lui sp,0xffff8
58: 0220af33 mulhsu t5,ra,sp
5c: 00000e93 li t4,0
60: 00500193 li gp,5
64: 47df1663 bne t5,t4,4d0 <fail>
00000068 <test_6>:
68: 800000b7 lui ra,0x80000
6c: 00000113 li sp,0
70: 0220af33 mulhsu t5,ra,sp
74: 00000e93 li t4,0
78: 00600193 li gp,6
7c: 45df1a63 bne t5,t4,4d0 <fail>
00000080 <test_7>:
80: 800000b7 lui ra,0x80000
84: ffff8137 lui sp,0xffff8
88: 0220af33 mulhsu t5,ra,sp
8c: 80004eb7 lui t4,0x80004
90: 00700193 li gp,7
94: 43df1e63 bne t5,t4,4d0 <fail>
00000098 <test_30>:
98: aaaab0b7 lui ra,0xaaaab
9c: aab08093 addi ra,ra,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
a0: 00030137 lui sp,0x30
a4: e7d10113 addi sp,sp,-387 # 2fe7d <begin_signature+0x2ee7d>
a8: 0220af33 mulhsu t5,ra,sp
ac: ffff0eb7 lui t4,0xffff0
b0: 081e8e93 addi t4,t4,129 # ffff0081 <begin_signature+0xfffef081>
b4: 01e00193 li gp,30
b8: 41df1c63 bne t5,t4,4d0 <fail>
000000bc <test_31>:
bc: 000300b7 lui ra,0x30
c0: e7d08093 addi ra,ra,-387 # 2fe7d <begin_signature+0x2ee7d>
c4: aaaab137 lui sp,0xaaaab
c8: aab10113 addi sp,sp,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
cc: 0220af33 mulhsu t5,ra,sp
d0: 00020eb7 lui t4,0x20
d4: efee8e93 addi t4,t4,-258 # 1fefe <begin_signature+0x1eefe>
d8: 01f00193 li gp,31
dc: 3fdf1a63 bne t5,t4,4d0 <fail>
000000e0 <test_32>:
e0: ff0000b7 lui ra,0xff000
e4: ff000137 lui sp,0xff000
e8: 0220af33 mulhsu t5,ra,sp
ec: ff010eb7 lui t4,0xff010
f0: 02000193 li gp,32
f4: 3ddf1e63 bne t5,t4,4d0 <fail>
000000f8 <test_33>:
f8: fff00093 li ra,-1
fc: fff00113 li sp,-1
100: 0220af33 mulhsu t5,ra,sp
104: fff00e93 li t4,-1
108: 02100193 li gp,33
10c: 3ddf1263 bne t5,t4,4d0 <fail>
00000110 <test_34>:
110: fff00093 li ra,-1
114: 00100113 li sp,1
118: 0220af33 mulhsu t5,ra,sp
11c: fff00e93 li t4,-1
120: 02200193 li gp,34
124: 3bdf1663 bne t5,t4,4d0 <fail>
00000128 <test_35>:
128: 00100093 li ra,1
12c: fff00113 li sp,-1
130: 0220af33 mulhsu t5,ra,sp
134: 00000e93 li t4,0
138: 02300193 li gp,35
13c: 39df1a63 bne t5,t4,4d0 <fail>
00000140 <test_8>:
140: 00d000b7 lui ra,0xd00
144: 00b00137 lui sp,0xb00
148: 0220a0b3 mulhsu ra,ra,sp
14c: 00009eb7 lui t4,0x9
150: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
154: 00800193 li gp,8
158: 37d09c63 bne ra,t4,4d0 <fail>
0000015c <test_9>:
15c: 00e000b7 lui ra,0xe00
160: 00b00137 lui sp,0xb00
164: 0220a133 mulhsu sp,ra,sp
168: 0000aeb7 lui t4,0xa
16c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
170: 00900193 li gp,9
174: 35d11e63 bne sp,t4,4d0 <fail>
00000178 <test_10>:
178: 00d000b7 lui ra,0xd00
17c: 0210a0b3 mulhsu ra,ra,ra
180: 0000beb7 lui t4,0xb
184: 900e8e93 addi t4,t4,-1792 # a900 <begin_signature+0x9900>
188: 00a00193 li gp,10
18c: 35d09263 bne ra,t4,4d0 <fail>
00000190 <test_11>:
190: 00000213 li tp,0
194: 00d000b7 lui ra,0xd00
198: 00b00137 lui sp,0xb00
19c: 0220af33 mulhsu t5,ra,sp
1a0: 000f0313 mv t1,t5
1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1a8: 00200293 li t0,2
1ac: fe5214e3 bne tp,t0,194 <test_11+0x4>
1b0: 00009eb7 lui t4,0x9
1b4: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
1b8: 00b00193 li gp,11
1bc: 31d31a63 bne t1,t4,4d0 <fail>
000001c0 <test_12>:
1c0: 00000213 li tp,0
1c4: 00e000b7 lui ra,0xe00
1c8: 00b00137 lui sp,0xb00
1cc: 0220af33 mulhsu t5,ra,sp
1d0: 00000013 nop
1d4: 000f0313 mv t1,t5
1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1dc: 00200293 li t0,2
1e0: fe5212e3 bne tp,t0,1c4 <test_12+0x4>
1e4: 0000aeb7 lui t4,0xa
1e8: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
1ec: 00c00193 li gp,12
1f0: 2fd31063 bne t1,t4,4d0 <fail>
000001f4 <test_13>:
1f4: 00000213 li tp,0
1f8: 00f000b7 lui ra,0xf00
1fc: 00b00137 lui sp,0xb00
200: 0220af33 mulhsu t5,ra,sp
204: 00000013 nop
208: 00000013 nop
20c: 000f0313 mv t1,t5
210: 00120213 addi tp,tp,1 # 1 <_start+0x1>
214: 00200293 li t0,2
218: fe5210e3 bne tp,t0,1f8 <test_13+0x4>
21c: 0000aeb7 lui t4,0xa
220: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
224: 00d00193 li gp,13
228: 2bd31463 bne t1,t4,4d0 <fail>
0000022c <test_14>:
22c: 00000213 li tp,0
230: 00d000b7 lui ra,0xd00
234: 00b00137 lui sp,0xb00
238: 0220af33 mulhsu t5,ra,sp
23c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
240: 00200293 li t0,2
244: fe5216e3 bne tp,t0,230 <test_14+0x4>
248: 00009eb7 lui t4,0x9
24c: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
250: 00e00193 li gp,14
254: 27df1e63 bne t5,t4,4d0 <fail>
00000258 <test_15>:
258: 00000213 li tp,0
25c: 00e000b7 lui ra,0xe00
260: 00b00137 lui sp,0xb00
264: 00000013 nop
268: 0220af33 mulhsu t5,ra,sp
26c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
270: 00200293 li t0,2
274: fe5214e3 bne tp,t0,25c <test_15+0x4>
278: 0000aeb7 lui t4,0xa
27c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
280: 00f00193 li gp,15
284: 25df1663 bne t5,t4,4d0 <fail>
00000288 <test_16>:
288: 00000213 li tp,0
28c: 00f000b7 lui ra,0xf00
290: 00b00137 lui sp,0xb00
294: 00000013 nop
298: 00000013 nop
29c: 0220af33 mulhsu t5,ra,sp
2a0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2a4: 00200293 li t0,2
2a8: fe5212e3 bne tp,t0,28c <test_16+0x4>
2ac: 0000aeb7 lui t4,0xa
2b0: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
2b4: 01000193 li gp,16
2b8: 21df1c63 bne t5,t4,4d0 <fail>
000002bc <test_17>:
2bc: 00000213 li tp,0
2c0: 00d000b7 lui ra,0xd00
2c4: 00000013 nop
2c8: 00b00137 lui sp,0xb00
2cc: 0220af33 mulhsu t5,ra,sp
2d0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2d4: 00200293 li t0,2
2d8: fe5214e3 bne tp,t0,2c0 <test_17+0x4>
2dc: 00009eb7 lui t4,0x9
2e0: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
2e4: 01100193 li gp,17
2e8: 1fdf1463 bne t5,t4,4d0 <fail>
000002ec <test_18>:
2ec: 00000213 li tp,0
2f0: 00e000b7 lui ra,0xe00
2f4: 00000013 nop
2f8: 00b00137 lui sp,0xb00
2fc: 00000013 nop
300: 0220af33 mulhsu t5,ra,sp
304: 00120213 addi tp,tp,1 # 1 <_start+0x1>
308: 00200293 li t0,2
30c: fe5212e3 bne tp,t0,2f0 <test_18+0x4>
310: 0000aeb7 lui t4,0xa
314: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
318: 01200193 li gp,18
31c: 1bdf1a63 bne t5,t4,4d0 <fail>
00000320 <test_19>:
320: 00000213 li tp,0
324: 00f000b7 lui ra,0xf00
328: 00000013 nop
32c: 00000013 nop
330: 00b00137 lui sp,0xb00
334: 0220af33 mulhsu t5,ra,sp
338: 00120213 addi tp,tp,1 # 1 <_start+0x1>
33c: 00200293 li t0,2
340: fe5212e3 bne tp,t0,324 <test_19+0x4>
344: 0000aeb7 lui t4,0xa
348: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
34c: 01300193 li gp,19
350: 19df1063 bne t5,t4,4d0 <fail>
00000354 <test_20>:
354: 00000213 li tp,0
358: 00b00137 lui sp,0xb00
35c: 00d000b7 lui ra,0xd00
360: 0220af33 mulhsu t5,ra,sp
364: 00120213 addi tp,tp,1 # 1 <_start+0x1>
368: 00200293 li t0,2
36c: fe5216e3 bne tp,t0,358 <test_20+0x4>
370: 00009eb7 lui t4,0x9
374: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
378: 01400193 li gp,20
37c: 15df1a63 bne t5,t4,4d0 <fail>
00000380 <test_21>:
380: 00000213 li tp,0
384: 00b00137 lui sp,0xb00
388: 00e000b7 lui ra,0xe00
38c: 00000013 nop
390: 0220af33 mulhsu t5,ra,sp
394: 00120213 addi tp,tp,1 # 1 <_start+0x1>
398: 00200293 li t0,2
39c: fe5214e3 bne tp,t0,384 <test_21+0x4>
3a0: 0000aeb7 lui t4,0xa
3a4: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
3a8: 01500193 li gp,21
3ac: 13df1263 bne t5,t4,4d0 <fail>
000003b0 <test_22>:
3b0: 00000213 li tp,0
3b4: 00b00137 lui sp,0xb00
3b8: 00f000b7 lui ra,0xf00
3bc: 00000013 nop
3c0: 00000013 nop
3c4: 0220af33 mulhsu t5,ra,sp
3c8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3cc: 00200293 li t0,2
3d0: fe5212e3 bne tp,t0,3b4 <test_22+0x4>
3d4: 0000aeb7 lui t4,0xa
3d8: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
3dc: 01600193 li gp,22
3e0: 0fdf1863 bne t5,t4,4d0 <fail>
000003e4 <test_23>:
3e4: 00000213 li tp,0
3e8: 00b00137 lui sp,0xb00
3ec: 00000013 nop
3f0: 00d000b7 lui ra,0xd00
3f4: 0220af33 mulhsu t5,ra,sp
3f8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3fc: 00200293 li t0,2
400: fe5214e3 bne tp,t0,3e8 <test_23+0x4>
404: 00009eb7 lui t4,0x9
408: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
40c: 01700193 li gp,23
410: 0ddf1063 bne t5,t4,4d0 <fail>
00000414 <test_24>:
414: 00000213 li tp,0
418: 00b00137 lui sp,0xb00
41c: 00000013 nop
420: 00e000b7 lui ra,0xe00
424: 00000013 nop
428: 0220af33 mulhsu t5,ra,sp
42c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
430: 00200293 li t0,2
434: fe5212e3 bne tp,t0,418 <test_24+0x4>
438: 0000aeb7 lui t4,0xa
43c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
440: 01800193 li gp,24
444: 09df1663 bne t5,t4,4d0 <fail>
00000448 <test_25>:
448: 00000213 li tp,0
44c: 00b00137 lui sp,0xb00
450: 00000013 nop
454: 00000013 nop
458: 00f000b7 lui ra,0xf00
45c: 0220af33 mulhsu t5,ra,sp
460: 00120213 addi tp,tp,1 # 1 <_start+0x1>
464: 00200293 li t0,2
468: fe5212e3 bne tp,t0,44c <test_25+0x4>
46c: 0000aeb7 lui t4,0xa
470: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
474: 01900193 li gp,25
478: 05df1c63 bne t5,t4,4d0 <fail>
0000047c <test_26>:
47c: 7c0000b7 lui ra,0x7c000
480: 02102133 mulhsu sp,zero,ra
484: 00000e93 li t4,0
488: 01a00193 li gp,26
48c: 05d11263 bne sp,t4,4d0 <fail>
00000490 <test_27>:
490: 800000b7 lui ra,0x80000
494: 0200a133 mulhsu sp,ra,zero
498: 00000e93 li t4,0
49c: 01b00193 li gp,27
4a0: 03d11863 bne sp,t4,4d0 <fail>
000004a4 <test_28>:
4a4: 020020b3 mulhsu ra,zero,zero
4a8: 00000e93 li t4,0
4ac: 01c00193 li gp,28
4b0: 03d09063 bne ra,t4,4d0 <fail>
000004b4 <test_29>:
4b4: 021000b7 lui ra,0x2100
4b8: 02200137 lui sp,0x2200
4bc: 0220a033 mulhsu zero,ra,sp
4c0: 00000e93 li t4,0
4c4: 01d00193 li gp,29
4c8: 01d01463 bne zero,t4,4d0 <fail>
4cc: 00301863 bne zero,gp,4dc <pass>
000004d0 <fail>:
4d0: 00100d13 li s10,1
4d4: 00000d93 li s11,0
000004d8 <loop_fail>:
4d8: 0000006f j 4d8 <loop_fail>
000004dc <pass>:
4dc: 00100d13 li s10,1
4e0: 00100d93 li s11,1
000004e4 <loop_pass>:
4e4: 0000006f j 4e4 <loop_pass>
...
Disassembly of section .tohost:
00000540 <tohost>:
...
00000580 <fromhost>:
...

88
tests/isa/generated/rv32um-p-mulhsu.verilog Normal file
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@ -0,0 +1,88 @@
@00000000
13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00
33 AF 20 02 93 0E 00 00 93 01 20 00 63 1A DF 4B
93 00 10 00 13 01 10 00 33 AF 20 02 93 0E 00 00
93 01 30 00 63 1E DF 49 93 00 30 00 13 01 70 00
33 AF 20 02 93 0E 00 00 93 01 40 00 63 12 DF 49
93 00 00 00 37 81 FF FF 33 AF 20 02 93 0E 00 00
93 01 50 00 63 16 DF 47 B7 00 00 80 13 01 00 00
33 AF 20 02 93 0E 00 00 93 01 60 00 63 1A DF 45
B7 00 00 80 37 81 FF FF 33 AF 20 02 B7 4E 00 80
93 01 70 00 63 1E DF 43 B7 B0 AA AA 93 80 B0 AA
37 01 03 00 13 01 D1 E7 33 AF 20 02 B7 0E FF FF
93 8E 1E 08 93 01 E0 01 63 1C DF 41 B7 00 03 00
93 80 D0 E7 37 B1 AA AA 13 01 B1 AA 33 AF 20 02
B7 0E 02 00 93 8E EE EF 93 01 F0 01 63 1A DF 3F
B7 00 00 FF 37 01 00 FF 33 AF 20 02 B7 0E 01 FF
93 01 00 02 63 1E DF 3D 93 00 F0 FF 13 01 F0 FF
33 AF 20 02 93 0E F0 FF 93 01 10 02 63 12 DF 3D
93 00 F0 FF 13 01 10 00 33 AF 20 02 93 0E F0 FF
93 01 20 02 63 16 DF 3B 93 00 10 00 13 01 F0 FF
33 AF 20 02 93 0E 00 00 93 01 30 02 63 1A DF 39
B7 00 D0 00 37 01 B0 00 B3 A0 20 02 B7 9E 00 00
93 8E 0E F0 93 01 80 00 63 9C D0 37 B7 00 E0 00
37 01 B0 00 33 A1 20 02 B7 AE 00 00 93 8E 0E A0
93 01 90 00 63 1E D1 35 B7 00 D0 00 B3 A0 10 02
B7 BE 00 00 93 8E 0E 90 93 01 A0 00 63 92 D0 35
13 02 00 00 B7 00 D0 00 37 01 B0 00 33 AF 20 02
13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 B0 00 63 1A D3 31
13 02 00 00 B7 00 E0 00 37 01 B0 00 33 AF 20 02
13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E A0 93 01 C0 00
63 10 D3 2F 13 02 00 00 B7 00 F0 00 37 01 B0 00
33 AF 20 02 13 00 00 00 13 00 00 00 13 03 0F 00
13 02 12 00 93 02 20 00 E3 10 52 FE B7 AE 00 00
93 8E 0E 50 93 01 D0 00 63 14 D3 2B 13 02 00 00
B7 00 D0 00 37 01 B0 00 33 AF 20 02 13 02 12 00
93 02 20 00 E3 16 52 FE B7 9E 00 00 93 8E 0E F0
93 01 E0 00 63 1E DF 27 13 02 00 00 B7 00 E0 00
37 01 B0 00 13 00 00 00 33 AF 20 02 13 02 12 00
93 02 20 00 E3 14 52 FE B7 AE 00 00 93 8E 0E A0
93 01 F0 00 63 16 DF 25 13 02 00 00 B7 00 F0 00
37 01 B0 00 13 00 00 00 13 00 00 00 33 AF 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 00 01 63 1C DF 21 13 02 00 00
B7 00 D0 00 13 00 00 00 37 01 B0 00 33 AF 20 02
13 02 12 00 93 02 20 00 E3 14 52 FE B7 9E 00 00
93 8E 0E F0 93 01 10 01 63 14 DF 1F 13 02 00 00
B7 00 E0 00 13 00 00 00 37 01 B0 00 13 00 00 00
33 AF 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 20 01 63 1A DF 1B
13 02 00 00 B7 00 F0 00 13 00 00 00 13 00 00 00
37 01 B0 00 33 AF 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 30 01
63 10 DF 19 13 02 00 00 37 01 B0 00 B7 00 D0 00
33 AF 20 02 13 02 12 00 93 02 20 00 E3 16 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 40 01 63 1A DF 15
13 02 00 00 37 01 B0 00 B7 00 E0 00 13 00 00 00
33 AF 20 02 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 50 01 63 12 DF 13
13 02 00 00 37 01 B0 00 B7 00 F0 00 13 00 00 00
13 00 00 00 33 AF 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 60 01
63 18 DF 0F 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 D0 00 33 AF 20 02 13 02 12 00 93 02 20 00
E3 14 52 FE B7 9E 00 00 93 8E 0E F0 93 01 70 01
63 10 DF 0D 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 E0 00 13 00 00 00 33 AF 20 02 13 02 12 00
93 02 20 00 E3 12 52 FE B7 AE 00 00 93 8E 0E A0
93 01 80 01 63 16 DF 09 13 02 00 00 37 01 B0 00
13 00 00 00 13 00 00 00 B7 00 F0 00 33 AF 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 90 01 63 1C DF 05 B7 00 00 7C
33 21 10 02 93 0E 00 00 93 01 A0 01 63 12 D1 05
B7 00 00 80 33 A1 00 02 93 0E 00 00 93 01 B0 01
63 18 D1 03 B3 20 00 02 93 0E 00 00 93 01 C0 01
63 90 D0 03 B7 00 10 02 37 01 20 02 33 A0 20 02
93 0E 00 00 93 01 D0 01 63 14 D0 01 63 18 30 00
13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00
93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
@00000540
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

BIN
tests/isa/generated/rv32um-p-mulhu Normal file
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BIN
tests/isa/generated/rv32um-p-mulhu.bin Normal file
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406
tests/isa/generated/rv32um-p-mulhu.dump Normal file
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generated/rv32um-p-mulhu: file format elf32-littleriscv
Disassembly of section .text.init:
00000000 <_start>:
0: 00000d13 li s10,0
4: 00000d93 li s11,0
00000008 <test_2>:
8: 00000093 li ra,0
c: 00000113 li sp,0
10: 0220bf33 mulhu t5,ra,sp
14: 00000e93 li t4,0
18: 00200193 li gp,2
1c: 4bdf1a63 bne t5,t4,4d0 <fail>
00000020 <test_3>:
20: 00100093 li ra,1
24: 00100113 li sp,1
28: 0220bf33 mulhu t5,ra,sp
2c: 00000e93 li t4,0
30: 00300193 li gp,3
34: 49df1e63 bne t5,t4,4d0 <fail>
00000038 <test_4>:
38: 00300093 li ra,3
3c: 00700113 li sp,7
40: 0220bf33 mulhu t5,ra,sp
44: 00000e93 li t4,0
48: 00400193 li gp,4
4c: 49df1263 bne t5,t4,4d0 <fail>
00000050 <test_5>:
50: 00000093 li ra,0
54: ffff8137 lui sp,0xffff8
58: 0220bf33 mulhu t5,ra,sp
5c: 00000e93 li t4,0
60: 00500193 li gp,5
64: 47df1663 bne t5,t4,4d0 <fail>
00000068 <test_6>:
68: 800000b7 lui ra,0x80000
6c: 00000113 li sp,0
70: 0220bf33 mulhu t5,ra,sp
74: 00000e93 li t4,0
78: 00600193 li gp,6
7c: 45df1a63 bne t5,t4,4d0 <fail>
00000080 <test_7>:
80: 800000b7 lui ra,0x80000
84: ffff8137 lui sp,0xffff8
88: 0220bf33 mulhu t5,ra,sp
8c: 7fffceb7 lui t4,0x7fffc
90: 00700193 li gp,7
94: 43df1e63 bne t5,t4,4d0 <fail>
00000098 <test_30>:
98: aaaab0b7 lui ra,0xaaaab
9c: aab08093 addi ra,ra,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
a0: 00030137 lui sp,0x30
a4: e7d10113 addi sp,sp,-387 # 2fe7d <begin_signature+0x2ee7d>
a8: 0220bf33 mulhu t5,ra,sp
ac: 00020eb7 lui t4,0x20
b0: efee8e93 addi t4,t4,-258 # 1fefe <begin_signature+0x1eefe>
b4: 01e00193 li gp,30
b8: 41df1c63 bne t5,t4,4d0 <fail>
000000bc <test_31>:
bc: 000300b7 lui ra,0x30
c0: e7d08093 addi ra,ra,-387 # 2fe7d <begin_signature+0x2ee7d>
c4: aaaab137 lui sp,0xaaaab
c8: aab10113 addi sp,sp,-1365 # aaaaaaab <begin_signature+0xaaaa9aab>
cc: 0220bf33 mulhu t5,ra,sp
d0: 00020eb7 lui t4,0x20
d4: efee8e93 addi t4,t4,-258 # 1fefe <begin_signature+0x1eefe>
d8: 01f00193 li gp,31
dc: 3fdf1a63 bne t5,t4,4d0 <fail>
000000e0 <test_32>:
e0: ff0000b7 lui ra,0xff000
e4: ff000137 lui sp,0xff000
e8: 0220bf33 mulhu t5,ra,sp
ec: fe010eb7 lui t4,0xfe010
f0: 02000193 li gp,32
f4: 3ddf1e63 bne t5,t4,4d0 <fail>
000000f8 <test_33>:
f8: fff00093 li ra,-1
fc: fff00113 li sp,-1
100: 0220bf33 mulhu t5,ra,sp
104: ffe00e93 li t4,-2
108: 02100193 li gp,33
10c: 3ddf1263 bne t5,t4,4d0 <fail>
00000110 <test_34>:
110: fff00093 li ra,-1
114: 00100113 li sp,1
118: 0220bf33 mulhu t5,ra,sp
11c: 00000e93 li t4,0
120: 02200193 li gp,34
124: 3bdf1663 bne t5,t4,4d0 <fail>
00000128 <test_35>:
128: 00100093 li ra,1
12c: fff00113 li sp,-1
130: 0220bf33 mulhu t5,ra,sp
134: 00000e93 li t4,0
138: 02300193 li gp,35
13c: 39df1a63 bne t5,t4,4d0 <fail>
00000140 <test_8>:
140: 00d000b7 lui ra,0xd00
144: 00b00137 lui sp,0xb00
148: 0220b0b3 mulhu ra,ra,sp
14c: 00009eb7 lui t4,0x9
150: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
154: 00800193 li gp,8
158: 37d09c63 bne ra,t4,4d0 <fail>
0000015c <test_9>:
15c: 00e000b7 lui ra,0xe00
160: 00b00137 lui sp,0xb00
164: 0220b133 mulhu sp,ra,sp
168: 0000aeb7 lui t4,0xa
16c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
170: 00900193 li gp,9
174: 35d11e63 bne sp,t4,4d0 <fail>
00000178 <test_10>:
178: 00d000b7 lui ra,0xd00
17c: 0210b0b3 mulhu ra,ra,ra
180: 0000beb7 lui t4,0xb
184: 900e8e93 addi t4,t4,-1792 # a900 <begin_signature+0x9900>
188: 00a00193 li gp,10
18c: 35d09263 bne ra,t4,4d0 <fail>
00000190 <test_11>:
190: 00000213 li tp,0
194: 00d000b7 lui ra,0xd00
198: 00b00137 lui sp,0xb00
19c: 0220bf33 mulhu t5,ra,sp
1a0: 000f0313 mv t1,t5
1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1a8: 00200293 li t0,2
1ac: fe5214e3 bne tp,t0,194 <test_11+0x4>
1b0: 00009eb7 lui t4,0x9
1b4: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
1b8: 00b00193 li gp,11
1bc: 31d31a63 bne t1,t4,4d0 <fail>
000001c0 <test_12>:
1c0: 00000213 li tp,0
1c4: 00e000b7 lui ra,0xe00
1c8: 00b00137 lui sp,0xb00
1cc: 0220bf33 mulhu t5,ra,sp
1d0: 00000013 nop
1d4: 000f0313 mv t1,t5
1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
1dc: 00200293 li t0,2
1e0: fe5212e3 bne tp,t0,1c4 <test_12+0x4>
1e4: 0000aeb7 lui t4,0xa
1e8: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
1ec: 00c00193 li gp,12
1f0: 2fd31063 bne t1,t4,4d0 <fail>
000001f4 <test_13>:
1f4: 00000213 li tp,0
1f8: 00f000b7 lui ra,0xf00
1fc: 00b00137 lui sp,0xb00
200: 0220bf33 mulhu t5,ra,sp
204: 00000013 nop
208: 00000013 nop
20c: 000f0313 mv t1,t5
210: 00120213 addi tp,tp,1 # 1 <_start+0x1>
214: 00200293 li t0,2
218: fe5210e3 bne tp,t0,1f8 <test_13+0x4>
21c: 0000aeb7 lui t4,0xa
220: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
224: 00d00193 li gp,13
228: 2bd31463 bne t1,t4,4d0 <fail>
0000022c <test_14>:
22c: 00000213 li tp,0
230: 00d000b7 lui ra,0xd00
234: 00b00137 lui sp,0xb00
238: 0220bf33 mulhu t5,ra,sp
23c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
240: 00200293 li t0,2
244: fe5216e3 bne tp,t0,230 <test_14+0x4>
248: 00009eb7 lui t4,0x9
24c: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
250: 00e00193 li gp,14
254: 27df1e63 bne t5,t4,4d0 <fail>
00000258 <test_15>:
258: 00000213 li tp,0
25c: 00e000b7 lui ra,0xe00
260: 00b00137 lui sp,0xb00
264: 00000013 nop
268: 0220bf33 mulhu t5,ra,sp
26c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
270: 00200293 li t0,2
274: fe5214e3 bne tp,t0,25c <test_15+0x4>
278: 0000aeb7 lui t4,0xa
27c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
280: 00f00193 li gp,15
284: 25df1663 bne t5,t4,4d0 <fail>
00000288 <test_16>:
288: 00000213 li tp,0
28c: 00f000b7 lui ra,0xf00
290: 00b00137 lui sp,0xb00
294: 00000013 nop
298: 00000013 nop
29c: 0220bf33 mulhu t5,ra,sp
2a0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2a4: 00200293 li t0,2
2a8: fe5212e3 bne tp,t0,28c <test_16+0x4>
2ac: 0000aeb7 lui t4,0xa
2b0: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
2b4: 01000193 li gp,16
2b8: 21df1c63 bne t5,t4,4d0 <fail>
000002bc <test_17>:
2bc: 00000213 li tp,0
2c0: 00d000b7 lui ra,0xd00
2c4: 00000013 nop
2c8: 00b00137 lui sp,0xb00
2cc: 0220bf33 mulhu t5,ra,sp
2d0: 00120213 addi tp,tp,1 # 1 <_start+0x1>
2d4: 00200293 li t0,2
2d8: fe5214e3 bne tp,t0,2c0 <test_17+0x4>
2dc: 00009eb7 lui t4,0x9
2e0: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
2e4: 01100193 li gp,17
2e8: 1fdf1463 bne t5,t4,4d0 <fail>
000002ec <test_18>:
2ec: 00000213 li tp,0
2f0: 00e000b7 lui ra,0xe00
2f4: 00000013 nop
2f8: 00b00137 lui sp,0xb00
2fc: 00000013 nop
300: 0220bf33 mulhu t5,ra,sp
304: 00120213 addi tp,tp,1 # 1 <_start+0x1>
308: 00200293 li t0,2
30c: fe5212e3 bne tp,t0,2f0 <test_18+0x4>
310: 0000aeb7 lui t4,0xa
314: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
318: 01200193 li gp,18
31c: 1bdf1a63 bne t5,t4,4d0 <fail>
00000320 <test_19>:
320: 00000213 li tp,0
324: 00f000b7 lui ra,0xf00
328: 00000013 nop
32c: 00000013 nop
330: 00b00137 lui sp,0xb00
334: 0220bf33 mulhu t5,ra,sp
338: 00120213 addi tp,tp,1 # 1 <_start+0x1>
33c: 00200293 li t0,2
340: fe5212e3 bne tp,t0,324 <test_19+0x4>
344: 0000aeb7 lui t4,0xa
348: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
34c: 01300193 li gp,19
350: 19df1063 bne t5,t4,4d0 <fail>
00000354 <test_20>:
354: 00000213 li tp,0
358: 00b00137 lui sp,0xb00
35c: 00d000b7 lui ra,0xd00
360: 0220bf33 mulhu t5,ra,sp
364: 00120213 addi tp,tp,1 # 1 <_start+0x1>
368: 00200293 li t0,2
36c: fe5216e3 bne tp,t0,358 <test_20+0x4>
370: 00009eb7 lui t4,0x9
374: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
378: 01400193 li gp,20
37c: 15df1a63 bne t5,t4,4d0 <fail>
00000380 <test_21>:
380: 00000213 li tp,0
384: 00b00137 lui sp,0xb00
388: 00e000b7 lui ra,0xe00
38c: 00000013 nop
390: 0220bf33 mulhu t5,ra,sp
394: 00120213 addi tp,tp,1 # 1 <_start+0x1>
398: 00200293 li t0,2
39c: fe5214e3 bne tp,t0,384 <test_21+0x4>
3a0: 0000aeb7 lui t4,0xa
3a4: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
3a8: 01500193 li gp,21
3ac: 13df1263 bne t5,t4,4d0 <fail>
000003b0 <test_22>:
3b0: 00000213 li tp,0
3b4: 00b00137 lui sp,0xb00
3b8: 00f000b7 lui ra,0xf00
3bc: 00000013 nop
3c0: 00000013 nop
3c4: 0220bf33 mulhu t5,ra,sp
3c8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3cc: 00200293 li t0,2
3d0: fe5212e3 bne tp,t0,3b4 <test_22+0x4>
3d4: 0000aeb7 lui t4,0xa
3d8: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
3dc: 01600193 li gp,22
3e0: 0fdf1863 bne t5,t4,4d0 <fail>
000003e4 <test_23>:
3e4: 00000213 li tp,0
3e8: 00b00137 lui sp,0xb00
3ec: 00000013 nop
3f0: 00d000b7 lui ra,0xd00
3f4: 0220bf33 mulhu t5,ra,sp
3f8: 00120213 addi tp,tp,1 # 1 <_start+0x1>
3fc: 00200293 li t0,2
400: fe5214e3 bne tp,t0,3e8 <test_23+0x4>
404: 00009eb7 lui t4,0x9
408: f00e8e93 addi t4,t4,-256 # 8f00 <begin_signature+0x7f00>
40c: 01700193 li gp,23
410: 0ddf1063 bne t5,t4,4d0 <fail>
00000414 <test_24>:
414: 00000213 li tp,0
418: 00b00137 lui sp,0xb00
41c: 00000013 nop
420: 00e000b7 lui ra,0xe00
424: 00000013 nop
428: 0220bf33 mulhu t5,ra,sp
42c: 00120213 addi tp,tp,1 # 1 <_start+0x1>
430: 00200293 li t0,2
434: fe5212e3 bne tp,t0,418 <test_24+0x4>
438: 0000aeb7 lui t4,0xa
43c: a00e8e93 addi t4,t4,-1536 # 9a00 <begin_signature+0x8a00>
440: 01800193 li gp,24
444: 09df1663 bne t5,t4,4d0 <fail>
00000448 <test_25>:
448: 00000213 li tp,0
44c: 00b00137 lui sp,0xb00
450: 00000013 nop
454: 00000013 nop
458: 00f000b7 lui ra,0xf00
45c: 0220bf33 mulhu t5,ra,sp
460: 00120213 addi tp,tp,1 # 1 <_start+0x1>
464: 00200293 li t0,2
468: fe5212e3 bne tp,t0,44c <test_25+0x4>
46c: 0000aeb7 lui t4,0xa
470: 500e8e93 addi t4,t4,1280 # a500 <begin_signature+0x9500>
474: 01900193 li gp,25
478: 05df1c63 bne t5,t4,4d0 <fail>
0000047c <test_26>:
47c: 7c0000b7 lui ra,0x7c000
480: 02103133 mulhu sp,zero,ra
484: 00000e93 li t4,0
488: 01a00193 li gp,26
48c: 05d11263 bne sp,t4,4d0 <fail>
00000490 <test_27>:
490: 800000b7 lui ra,0x80000
494: 0200b133 mulhu sp,ra,zero
498: 00000e93 li t4,0
49c: 01b00193 li gp,27
4a0: 03d11863 bne sp,t4,4d0 <fail>
000004a4 <test_28>:
4a4: 020030b3 mulhu ra,zero,zero
4a8: 00000e93 li t4,0
4ac: 01c00193 li gp,28
4b0: 03d09063 bne ra,t4,4d0 <fail>
000004b4 <test_29>:
4b4: 021000b7 lui ra,0x2100
4b8: 02200137 lui sp,0x2200
4bc: 0220b033 mulhu zero,ra,sp
4c0: 00000e93 li t4,0
4c4: 01d00193 li gp,29
4c8: 01d01463 bne zero,t4,4d0 <fail>
4cc: 00301863 bne zero,gp,4dc <pass>
000004d0 <fail>:
4d0: 00100d13 li s10,1
4d4: 00000d93 li s11,0
000004d8 <loop_fail>:
4d8: 0000006f j 4d8 <loop_fail>
000004dc <pass>:
4dc: 00100d13 li s10,1
4e0: 00100d93 li s11,1
000004e4 <loop_pass>:
4e4: 0000006f j 4e4 <loop_pass>
...
Disassembly of section .tohost:
00000540 <tohost>:
...
00000580 <fromhost>:
...

88
tests/isa/generated/rv32um-p-mulhu.verilog Normal file
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@ -0,0 +1,88 @@
@00000000
13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00
33 BF 20 02 93 0E 00 00 93 01 20 00 63 1A DF 4B
93 00 10 00 13 01 10 00 33 BF 20 02 93 0E 00 00
93 01 30 00 63 1E DF 49 93 00 30 00 13 01 70 00
33 BF 20 02 93 0E 00 00 93 01 40 00 63 12 DF 49
93 00 00 00 37 81 FF FF 33 BF 20 02 93 0E 00 00
93 01 50 00 63 16 DF 47 B7 00 00 80 13 01 00 00
33 BF 20 02 93 0E 00 00 93 01 60 00 63 1A DF 45
B7 00 00 80 37 81 FF FF 33 BF 20 02 B7 CE FF 7F
93 01 70 00 63 1E DF 43 B7 B0 AA AA 93 80 B0 AA
37 01 03 00 13 01 D1 E7 33 BF 20 02 B7 0E 02 00
93 8E EE EF 93 01 E0 01 63 1C DF 41 B7 00 03 00
93 80 D0 E7 37 B1 AA AA 13 01 B1 AA 33 BF 20 02
B7 0E 02 00 93 8E EE EF 93 01 F0 01 63 1A DF 3F
B7 00 00 FF 37 01 00 FF 33 BF 20 02 B7 0E 01 FE
93 01 00 02 63 1E DF 3D 93 00 F0 FF 13 01 F0 FF
33 BF 20 02 93 0E E0 FF 93 01 10 02 63 12 DF 3D
93 00 F0 FF 13 01 10 00 33 BF 20 02 93 0E 00 00
93 01 20 02 63 16 DF 3B 93 00 10 00 13 01 F0 FF
33 BF 20 02 93 0E 00 00 93 01 30 02 63 1A DF 39
B7 00 D0 00 37 01 B0 00 B3 B0 20 02 B7 9E 00 00
93 8E 0E F0 93 01 80 00 63 9C D0 37 B7 00 E0 00
37 01 B0 00 33 B1 20 02 B7 AE 00 00 93 8E 0E A0
93 01 90 00 63 1E D1 35 B7 00 D0 00 B3 B0 10 02
B7 BE 00 00 93 8E 0E 90 93 01 A0 00 63 92 D0 35
13 02 00 00 B7 00 D0 00 37 01 B0 00 33 BF 20 02
13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 B0 00 63 1A D3 31
13 02 00 00 B7 00 E0 00 37 01 B0 00 33 BF 20 02
13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E A0 93 01 C0 00
63 10 D3 2F 13 02 00 00 B7 00 F0 00 37 01 B0 00
33 BF 20 02 13 00 00 00 13 00 00 00 13 03 0F 00
13 02 12 00 93 02 20 00 E3 10 52 FE B7 AE 00 00
93 8E 0E 50 93 01 D0 00 63 14 D3 2B 13 02 00 00
B7 00 D0 00 37 01 B0 00 33 BF 20 02 13 02 12 00
93 02 20 00 E3 16 52 FE B7 9E 00 00 93 8E 0E F0
93 01 E0 00 63 1E DF 27 13 02 00 00 B7 00 E0 00
37 01 B0 00 13 00 00 00 33 BF 20 02 13 02 12 00
93 02 20 00 E3 14 52 FE B7 AE 00 00 93 8E 0E A0
93 01 F0 00 63 16 DF 25 13 02 00 00 B7 00 F0 00
37 01 B0 00 13 00 00 00 13 00 00 00 33 BF 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 00 01 63 1C DF 21 13 02 00 00
B7 00 D0 00 13 00 00 00 37 01 B0 00 33 BF 20 02
13 02 12 00 93 02 20 00 E3 14 52 FE B7 9E 00 00
93 8E 0E F0 93 01 10 01 63 14 DF 1F 13 02 00 00
B7 00 E0 00 13 00 00 00 37 01 B0 00 13 00 00 00
33 BF 20 02 13 02 12 00 93 02 20 00 E3 12 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 20 01 63 1A DF 1B
13 02 00 00 B7 00 F0 00 13 00 00 00 13 00 00 00
37 01 B0 00 33 BF 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 30 01
63 10 DF 19 13 02 00 00 37 01 B0 00 B7 00 D0 00
33 BF 20 02 13 02 12 00 93 02 20 00 E3 16 52 FE
B7 9E 00 00 93 8E 0E F0 93 01 40 01 63 1A DF 15
13 02 00 00 37 01 B0 00 B7 00 E0 00 13 00 00 00
33 BF 20 02 13 02 12 00 93 02 20 00 E3 14 52 FE
B7 AE 00 00 93 8E 0E A0 93 01 50 01 63 12 DF 13
13 02 00 00 37 01 B0 00 B7 00 F0 00 13 00 00 00
13 00 00 00 33 BF 20 02 13 02 12 00 93 02 20 00
E3 12 52 FE B7 AE 00 00 93 8E 0E 50 93 01 60 01
63 18 DF 0F 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 D0 00 33 BF 20 02 13 02 12 00 93 02 20 00
E3 14 52 FE B7 9E 00 00 93 8E 0E F0 93 01 70 01
63 10 DF 0D 13 02 00 00 37 01 B0 00 13 00 00 00
B7 00 E0 00 13 00 00 00 33 BF 20 02 13 02 12 00
93 02 20 00 E3 12 52 FE B7 AE 00 00 93 8E 0E A0
93 01 80 01 63 16 DF 09 13 02 00 00 37 01 B0 00
13 00 00 00 13 00 00 00 B7 00 F0 00 33 BF 20 02
13 02 12 00 93 02 20 00 E3 12 52 FE B7 AE 00 00
93 8E 0E 50 93 01 90 01 63 1C DF 05 B7 00 00 7C
33 31 10 02 93 0E 00 00 93 01 A0 01 63 12 D1 05
B7 00 00 80 33 B1 00 02 93 0E 00 00 93 01 B0 01
63 18 D1 03 B3 30 00 02 93 0E 00 00 93 01 C0 01
63 90 D0 03 B7 00 10 02 37 01 20 02 33 B0 20 02
93 0E 00 00 93 01 D0 01 63 14 D0 01 63 18 30 00
13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00
93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
@00000540
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00

9
tests/isa/rv32um/Makefrag Normal file
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#=======================================================================
# Makefrag for rv32um tests
#-----------------------------------------------------------------------
rv32um_sc_tests = \
mul mulh mulhsu mulhu \
rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))

84
tests/isa/rv32um/mul.S Normal file
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# See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
TEST_RR_ZEROSRC12( 28, mul, 0 );
TEST_RR_ZERODEST( 29, mul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END

81
tests/isa/rv32um/mulh.S Normal file
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# See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulh, 0 );
TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END

83
tests/isa/rv32um/mulhsu.S Normal file
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# See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END

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tests/isa/rv32um/mulhu.S Normal file
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# See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhu, 0 );
TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END