From 9420b85796454eba9261241d71e6521371d2d93b Mon Sep 17 00:00:00 2001 From: Blue Liang Date: Mon, 13 Jan 2020 08:26:41 +0800 Subject: [PATCH] add div inst Signed-off-by: Blue Liang --- rtl/defines.v | 10 ++ rtl/div.v | 131 +++++++++++++++++++++ rtl/ex.v | 132 +++++++++++++++++++++- rtl/id.v | 46 ++++++++ rtl/if_id.v | 4 + rtl/openriscv_core.v | 42 ++++++- rtl/pc_reg.v | 6 + sim/openriscv_core_tb.v | 2 +- sim/sim_default_nowave.bat | 2 +- sim/sim_new_nowave.bat | 2 +- tests/isa/generated/rv32um-p-div | Bin 0 -> 5336 bytes tests/isa/generated/rv32um-p-div.bin | Bin 0 -> 392 bytes tests/isa/generated/rv32um-p-div.dump | 105 +++++++++++++++++ tests/isa/generated/rv32um-p-div.verilog | 24 ++++ tests/isa/generated/rv32um-p-divu | Bin 0 -> 5336 bytes tests/isa/generated/rv32um-p-divu.bin | Bin 0 -> 392 bytes tests/isa/generated/rv32um-p-divu.dump | 107 ++++++++++++++++++ tests/isa/generated/rv32um-p-divu.verilog | 24 ++++ tests/isa/generated/rv32um-p-rem | Bin 0 -> 5336 bytes tests/isa/generated/rv32um-p-rem.bin | Bin 0 -> 392 bytes tests/isa/generated/rv32um-p-rem.dump | 105 +++++++++++++++++ tests/isa/generated/rv32um-p-rem.verilog | 24 ++++ tests/isa/generated/rv32um-p-remu | Bin 0 -> 5336 bytes tests/isa/generated/rv32um-p-remu.bin | Bin 0 -> 392 bytes tests/isa/generated/rv32um-p-remu.dump | 105 +++++++++++++++++ tests/isa/generated/rv32um-p-remu.verilog | 24 ++++ tests/isa/rv32um/Makefrag | 1 + tests/isa/rv32um/div.S | 41 +++++++ tests/isa/rv32um/divu.S | 41 +++++++ tests/isa/rv32um/rem.S | 41 +++++++ tests/isa/rv32um/remu.S | 41 +++++++ 31 files changed, 1053 insertions(+), 7 deletions(-) create mode 100644 rtl/div.v create mode 100644 tests/isa/generated/rv32um-p-div create mode 100644 tests/isa/generated/rv32um-p-div.bin create mode 100644 tests/isa/generated/rv32um-p-div.dump create mode 100644 tests/isa/generated/rv32um-p-div.verilog create mode 100644 tests/isa/generated/rv32um-p-divu create mode 100644 tests/isa/generated/rv32um-p-divu.bin create mode 100644 tests/isa/generated/rv32um-p-divu.dump create mode 100644 tests/isa/generated/rv32um-p-divu.verilog create mode 100644 tests/isa/generated/rv32um-p-rem create mode 100644 tests/isa/generated/rv32um-p-rem.bin create mode 100644 tests/isa/generated/rv32um-p-rem.dump create mode 100644 tests/isa/generated/rv32um-p-rem.verilog create mode 100644 tests/isa/generated/rv32um-p-remu create mode 100644 tests/isa/generated/rv32um-p-remu.bin create mode 100644 tests/isa/generated/rv32um-p-remu.dump create mode 100644 tests/isa/generated/rv32um-p-remu.verilog create mode 100644 tests/isa/rv32um/div.S create mode 100644 tests/isa/rv32um/divu.S create mode 100644 tests/isa/rv32um/rem.S create mode 100644 tests/isa/rv32um/remu.S diff --git a/rtl/defines.v b/rtl/defines.v index cfe6eac..156a7e4 100644 --- a/rtl/defines.v +++ b/rtl/defines.v @@ -29,6 +29,12 @@ `define ChipDisable 1'b0 `define JumpEnable 1'b1 `define JumpDisable 1'b0 +`define DivResultNotReady 1'b0 +`define DivResultReady 1'b1 +`define DivStart 1'b1 +`define DivStop 1'b0 +`define HoldEnable 1'b1 +`define HoldDisable 1'b0 // I type inst `define INST_TYPE_I 7'b0010011 @@ -71,6 +77,10 @@ `define INST_MULH 3'b001 `define INST_MULHSU 3'b010 `define INST_MULHU 3'b011 +`define INST_DIV 3'b100 +`define INST_DIVU 3'b101 +`define INST_REM 3'b110 +`define INST_REMU 3'b111 // J type inst `define INST_JAL 7'b1101111 diff --git a/rtl/div.v b/rtl/div.v new file mode 100644 index 0000000..87267b6 --- /dev/null +++ b/rtl/div.v @@ -0,0 +1,131 @@ +`include "defines.v" + + +module div ( + + input wire clk, + input wire rst, + + input wire[`RegBus] dividend_i, + input wire[`RegBus] divisor_i, + input wire start_i, + + output reg[`DoubleRegBus] result_o, + output reg ready_o + +); + + parameter STATE_IDLE = 0; + parameter STATE_START = 1; + parameter STATE_REVERT = 2; + parameter STATE_END = 3; + + + reg[`RegBus] dividend_temp; + reg[`RegBus] divisor_temp; + reg[1:0] state; + reg[6:0] count; + reg[`RegBus] div_result; + reg[`RegBus] div_remain; + reg[`RegBus] minuend; + reg[`RegBus] divisor_zero_result; + + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + state <= STATE_IDLE; + ready_o <= `DivResultNotReady; + result_o <= {`ZeroWord, `ZeroWord}; + div_result <= `ZeroWord; + div_remain <= `ZeroWord; + divisor_zero_result <= ~32'b00000001 + 1'b1; + end else begin + case (state) + STATE_IDLE: begin + if (start_i == `DivStart) begin + if (divisor_i == `ZeroWord) begin + ready_o <= `DivResultReady; + result_o <= {`ZeroWord, divisor_zero_result}; + end else begin + count <= 7'd31; + state <= STATE_START; + if (dividend_i[31] == 1'b1) begin + dividend_temp <= ~dividend_i + 1; + minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1; + end else begin + dividend_temp <= dividend_i; + minuend <= (dividend_i >> 7'd31) & 1'b1; + end + if (divisor_i[31] == 1'b1) begin + divisor_temp <= ~divisor_i + 1; + end else begin + divisor_temp <= divisor_i; + end + div_result <= `ZeroWord; + div_remain <= `ZeroWord; + end + end else begin + ready_o <= `DivResultNotReady; + result_o <= {`ZeroWord, `ZeroWord}; + end + end + + STATE_START: begin + if (start_i == `DivStart) begin + if (count >= 7'd1) begin + if (minuend >= divisor_temp) begin + div_result <= (div_result << 1'b1) | 1'b1; + minuend <= ((minuend - divisor_temp) << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1); + end else begin + div_result <= (div_result << 1'b1) | 1'b0; + minuend <= (minuend << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1); + end + count <= count - 1'b1; + end else begin + state <= STATE_REVERT; + if (minuend >= divisor_temp) begin + div_result <= (div_result << 1'b1) | 1'b1; + div_remain <= minuend - divisor_temp; + end else begin + div_result <= (div_result << 1'b1) | 1'b0; + div_remain <= minuend; + end + end + end else begin + ready_o <= `DivResultReady; + result_o <= {`ZeroWord, `ZeroWord}; + state <= STATE_IDLE; + end + end + + STATE_REVERT: begin + if (start_i == `DivStart) begin + if (dividend_i[31] ^ divisor_i[31] == 1'b1) begin + div_result <= ~div_result + 1'b1; + end + if (((dividend_i[31] == 1'b1) && (div_remain >= 0)) || ((dividend_i[31] == 1'b0) && (div_remain < 0))) begin + div_remain <= ~div_remain + 1'b1; + end + state <= STATE_END; + end else begin + ready_o <= `DivResultReady; + result_o <= {`ZeroWord, `ZeroWord}; + state <= STATE_IDLE; + end + end + + STATE_END: begin + if (start_i == `DivStart) begin + ready_o <= `DivResultReady; + result_o <= {div_remain, div_result}; + end else begin + state <= STATE_IDLE; + ready_o <= `DivResultNotReady; + end + end + + endcase + end + end + +endmodule diff --git a/rtl/ex.v b/rtl/ex.v index fa2d78f..bed7591 100644 --- a/rtl/ex.v +++ b/rtl/ex.v @@ -26,6 +26,8 @@ module ex ( input wire[`SramBus] inst_i, // inst content input wire inst_valid_i, input wire[`SramAddrBus] inst_addr_i, // inst addr + input wire reg_we_i, + input wire[`RegAddrBus] reg_waddr_i, // from regs input wire[`RegBus] reg1_rdata_i, // reg1 read data @@ -34,6 +36,10 @@ module ex ( // from sram input wire[`SramBus] sram_rdata_i, // ram read data + // from div + input wire div_ready_i, + input wire[`DoubleRegBus] div_result_i, + // to sram output reg[`SramBus] sram_wdata_o, // ram write data output reg[`SramAddrBus] sram_raddr_o, // ram read addr @@ -41,6 +47,17 @@ module ex ( // to regs output reg[`RegBus] reg_wdata_o, // reg write data + output reg reg_we_o, // reg write enable + output reg[`RegAddrBus] reg_waddr_o, // reg write addr + + // to div + output reg[`RegBus] div_dividend_o, + output reg[`RegBus] div_divisor_o, + output reg div_start_o, + + // to pc_reg + output reg hold_flag_o, + output reg[`RegBus] hold_addr_o, // to pc_reg output reg jump_flag_o, // if jump or not flag @@ -59,10 +76,16 @@ module ex ( wire[`DoubleRegBus] mulhsu_temp_invert; wire[`RegBus] op1_mul; wire[`RegBus] op2_mul; + reg div_starting; + reg is_jumping; + reg div_reg_we; + reg[4:0] div_rd_reg; + reg[2:0] div_funct3; wire[6:0] opcode = inst_i[6:0]; wire[2:0] funct3 = inst_i[14:12]; wire[6:0] funct7 = inst_i[31:25]; + wire[4:0] rd = inst_i[11:7]; assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]}; assign shift_bits = inst_i[24:20]; @@ -79,13 +102,66 @@ module ex ( if (rst == `RstEnable) begin sram_raddr_o <= `ZeroWord; jump_flag_o <= `JumpDisable; + hold_flag_o <= `HoldDisable; sram_raddr_index <= 2'b0; sram_waddr_index <= 2'b0; + div_starting <= `DivStop; + is_jumping <= `False; + div_reg_we <= `WriteDisable; + div_start_o <= `DivStop; end end always @ (*) begin - if (inst_valid_i == `InstValid) begin + div_dividend_o <= reg1_rdata_i; + div_divisor_o <= reg2_rdata_i; + end + + always @ (*) begin + reg_we_o <= reg_we_i | div_reg_we; + end + + always @ (*) begin + if ((is_jumping == `False) && (div_starting == `DivStart)) begin + if (div_ready_i == `DivResultReady) begin + case (div_funct3) + `INST_DIV: begin + div_reg_we <= `WriteEnable; + reg_waddr_o <= div_rd_reg; + reg_wdata_o <= div_result_i[31:0]; + div_starting <= `DivStop; + div_start_o <= `DivStop; + hold_flag_o <= `HoldDisable; + end + `INST_DIVU: begin + div_reg_we <= `WriteEnable; + reg_waddr_o <= div_rd_reg; + reg_wdata_o <= div_result_i[31:0]; + div_starting <= `DivStop; + div_start_o <= `DivStop; + hold_flag_o <= `HoldDisable; + end + `INST_REM: begin + div_reg_we <= `WriteEnable; + reg_waddr_o <= div_rd_reg; + reg_wdata_o <= div_result_i[63:32]; + div_starting <= `DivStop; + div_start_o <= `DivStop; + hold_flag_o <= `HoldDisable; + end + `INST_REMU: begin + div_reg_we <= `WriteEnable; + reg_waddr_o <= div_rd_reg; + reg_wdata_o <= div_result_i[63:32]; + div_starting <= `DivStop; + div_start_o <= `DivStop; + hold_flag_o <= `HoldDisable; + end + endcase + end + end else if (inst_valid_i == `InstValid) begin + div_reg_we <= `WriteDisable; + reg_waddr_o <= reg_waddr_i; case (opcode) `INST_TYPE_I: begin case (funct3) @@ -265,6 +341,42 @@ module ex ( reg_wdata_o <= mulhsu_temp[63:32]; end end + `INST_DIV: begin + jump_flag_o <= `JumpDisable; + hold_flag_o <= `HoldEnable; + div_start_o <= `DivStart; + div_starting <= `DivStart; + div_rd_reg <= rd; + div_funct3 <= funct3; + hold_addr_o <= inst_addr_i + 4'h4; + end + `INST_DIVU: begin + jump_flag_o <= `JumpDisable; + hold_flag_o <= `HoldEnable; + div_start_o <= `DivStart; + div_starting <= `DivStart; + div_rd_reg <= rd; + div_funct3 <= funct3; + hold_addr_o <= inst_addr_i + 4'h4; + end + `INST_REM: begin + jump_flag_o <= `JumpDisable; + hold_flag_o <= `HoldEnable; + div_start_o <= `DivStart; + div_starting <= `DivStart; + div_rd_reg <= rd; + div_funct3 <= funct3; + hold_addr_o <= inst_addr_i + 4'h4; + end + `INST_REMU: begin + jump_flag_o <= `JumpDisable; + hold_flag_o <= `HoldEnable; + div_start_o <= `DivStart; + div_starting <= `DivStart; + div_rd_reg <= rd; + div_funct3 <= funct3; + hold_addr_o <= inst_addr_i + 4'h4; + end endcase end end @@ -323,6 +435,7 @@ module ex ( `INST_BEQ: begin if (reg1_rdata_i == reg2_rdata_i) begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else begin jump_flag_o <= `JumpDisable; @@ -331,6 +444,7 @@ module ex ( `INST_BNE: begin if (reg1_rdata_i != reg2_rdata_i) begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else begin jump_flag_o <= `JumpDisable; @@ -339,12 +453,14 @@ module ex ( `INST_BLT: begin if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i >= reg2_rdata_i) begin jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin @@ -352,6 +468,7 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else begin @@ -361,12 +478,14 @@ module ex ( `INST_BGE: begin if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i < reg2_rdata_i) begin jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin @@ -374,6 +493,7 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else begin @@ -388,6 +508,7 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin @@ -395,10 +516,12 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end @@ -410,6 +533,7 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin @@ -417,10 +541,12 @@ module ex ( jump_flag_o <= `JumpDisable; end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end else begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end end @@ -428,11 +554,13 @@ module ex ( end `INST_JAL: begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; reg_wdata_o <= inst_addr_i + 4'h4; end `INST_JALR: begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe); reg_wdata_o <= inst_addr_i + 4'h4; end @@ -446,9 +574,11 @@ module ex ( end `INST_NOP: begin jump_flag_o <= `JumpDisable; + is_jumping <= `False; end `INST_FENCE: begin jump_flag_o <= `JumpEnable; + is_jumping <= `True; jump_addr_o <= inst_addr_i + 4'h4; end default: begin diff --git a/rtl/id.v b/rtl/id.v index db8590c..fe99833 100644 --- a/rtl/id.v +++ b/rtl/id.v @@ -24,6 +24,7 @@ module id ( input wire[`SramBus] inst_i, // inst content input wire[`SramAddrBus] inst_addr_i, // inst addr input wire jump_flag_ex_i, + input wire hold_flag_ex_i, // to regs output reg reg1_re_o, // reg1 read enable @@ -66,6 +67,11 @@ module id ( sram_we_o <= `WriteDisable; reg_we_o <= `WriteDisable; inst_o <= `INST_NOP; + end else if (hold_flag_ex_i == `HoldEnable) begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + inst_o <= `INST_NOP; end else begin inst_o <= inst_i; inst_addr_o <= inst_addr_i; @@ -271,6 +277,46 @@ module id ( reg2_raddr_o <= rs2; sram_we_o <= `WriteDisable; end + `INST_DIV: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteDisable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_DIVU: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteDisable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_REM: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteDisable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_REMU: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteDisable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end default: begin inst_valid_o <= `InstInvalid; end diff --git a/rtl/if_id.v b/rtl/if_id.v index 2d24d72..ee54edf 100644 --- a/rtl/if_id.v +++ b/rtl/if_id.v @@ -26,6 +26,7 @@ module if_id ( input wire[`SramAddrBus] inst_addr_i, // inst addr input wire jump_flag_ex_i, + input wire hold_flag_ex_i, output reg[`SramBus] inst_o, output reg[`SramAddrBus] inst_addr_o @@ -39,6 +40,9 @@ module if_id ( end else if (jump_flag_ex_i == `JumpEnable) begin inst_o <= `INST_NOP; inst_addr_o <= `ZeroWord; + end else if (hold_flag_ex_i == `HoldEnable) begin + inst_o <= `INST_NOP; + inst_addr_o <= `ZeroWord; end else begin inst_o <= inst_i; inst_addr_o <= inst_addr_i; diff --git a/rtl/openriscv_core.v b/rtl/openriscv_core.v index 418f04f..1ef6df7 100644 --- a/rtl/openriscv_core.v +++ b/rtl/openriscv_core.v @@ -53,6 +53,13 @@ module openriscv_core ( wire[`SramAddrBus] ex_sram_waddr_o; wire ex_jump_flag_o; wire[`RegBus] ex_jump_addr_o; + wire[`RegBus] ex_div_dividend_o; + wire[`RegBus] ex_div_divisor_o; + wire ex_div_start_o; + wire ex_hold_flag_o; + wire[`RegBus] ex_hold_addr_o; + wire ex_reg_we_o; + wire[`RegAddrBus] ex_reg_waddr_o; // regs wire[`RegBus] regs_rdata1_o; @@ -62,6 +69,10 @@ module openriscv_core ( wire[`SramBus] ram_pc_rdata_o; wire[`SramBus] ram_ex_rdata_o; + // div + wire[`DoubleRegBus] div_result_o; + wire div_ready_o; + sim_ram u_sim_ram( .clk(clk), .rst(rst), @@ -81,6 +92,8 @@ module openriscv_core ( .rst(rst), .pc_o(pc_pc_o), .re_o(pc_re_o), + .hold_flag_ex_i(ex_hold_flag_o), + .hold_addr_ex_i(ex_hold_addr_o), .jump_flag_ex_i(ex_jump_flag_o), .jump_addr_ex_i(ex_jump_addr_o) ); @@ -88,8 +101,8 @@ module openriscv_core ( regs u_regs( .clk(clk), .rst(rst), - .we(id_reg_we_o), - .waddr(id_reg_waddr_o), + .we(ex_reg_we_o), + .waddr(ex_reg_waddr_o), .wdata(ex_reg_wdata_o), .re1(id_reg1_re_o), .raddr1(id_reg1_raddr_o), @@ -106,7 +119,8 @@ module openriscv_core ( .inst_addr_i(pc_pc_o), .inst_o(if_inst_o), .inst_addr_o(if_inst_addr_o), - .jump_flag_ex_i(ex_jump_flag_o) + .jump_flag_ex_i(ex_jump_flag_o), + .hold_flag_ex_i(ex_hold_flag_o) ); id u_id( @@ -116,6 +130,7 @@ module openriscv_core ( .inst_addr_o(id_inst_addr_o), .inst_addr_i(if_inst_addr_o), .jump_flag_ex_i(ex_jump_flag_o), + .hold_flag_ex_i(ex_hold_flag_o), .reg1_re_o(id_reg1_re_o), .reg1_raddr_o(id_reg1_raddr_o), .reg2_re_o(id_reg2_re_o), @@ -134,15 +149,36 @@ module openriscv_core ( .inst_i(id_inst_o), .inst_addr_i(id_inst_addr_o), .inst_valid_i(id_inst_valid_o), + .reg_we_i(id_reg_we_o), + .reg_waddr_i(id_reg_waddr_o), .reg1_rdata_i(regs_rdata1_o), .reg2_rdata_i(regs_rdata2_o), .reg_wdata_o(ex_reg_wdata_o), + .reg_we_o(ex_reg_we_o), + .reg_waddr_o(ex_reg_waddr_o), .sram_rdata_i(ram_ex_rdata_o), .sram_wdata_o(ex_sram_wdata_o), .sram_raddr_o(ex_sram_raddr_o), .sram_waddr_o(ex_sram_waddr_o), + .div_dividend_o(ex_div_dividend_o), + .div_divisor_o(ex_div_divisor_o), + .div_ready_i(div_ready_o), + .div_result_i(div_result_o), + .div_start_o(ex_div_start_o), + .hold_flag_o(ex_hold_flag_o), + .hold_addr_o(ex_hold_addr_o), .jump_flag_o(ex_jump_flag_o), .jump_addr_o(ex_jump_addr_o) ); + div u_div( + .clk(clk), + .rst(rst), + .dividend_i(ex_div_dividend_o), + .divisor_i(ex_div_divisor_o), + .start_i(ex_div_start_o), + .result_o(div_result_o), + .ready_o(div_ready_o) + ); + endmodule diff --git a/rtl/pc_reg.v b/rtl/pc_reg.v index 5bc0c29..225538b 100644 --- a/rtl/pc_reg.v +++ b/rtl/pc_reg.v @@ -25,6 +25,9 @@ module pc_reg ( input wire jump_flag_ex_i, input wire[`RegBus] jump_addr_ex_i, + input wire hold_flag_ex_i, + input wire[`RegBus] hold_addr_ex_i, + output reg[`SramAddrBus] pc_o, output reg re_o @@ -39,6 +42,9 @@ module pc_reg ( end else if (jump_flag_ex_i == `JumpEnable) begin pc_o <= jump_addr_ex_i; offset <= jump_addr_ex_i + 4'h4; + end else if (hold_flag_ex_i == `HoldEnable) begin + pc_o <= hold_addr_ex_i; + offset <= hold_addr_ex_i; end else begin pc_o <= offset; offset <= offset + 4'h4; diff --git a/sim/openriscv_core_tb.v b/sim/openriscv_core_tb.v index 52a94c8..d79fc03 100644 --- a/sim/openriscv_core_tb.v +++ b/sim/openriscv_core_tb.v @@ -53,7 +53,7 @@ module openriscv_core_tb; // sim timeout initial begin - #100000 + #5000000 $display("Time Out."); $finish; end diff --git a/sim/sim_default_nowave.bat b/sim/sim_default_nowave.bat index 85767d6..b7e82cf 100644 --- a/sim/sim_default_nowave.bat +++ b/sim/sim_default_nowave.bat @@ -1,2 +1,2 @@ -iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v +iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v ..\rtl\div.v vvp out.vvp diff --git a/sim/sim_new_nowave.bat b/sim/sim_new_nowave.bat index 0232fb0..bc99a96 100644 --- a/sim/sim_new_nowave.bat +++ b/sim/sim_new_nowave.bat @@ -1,3 +1,3 @@ ..\tools\BinToMem_CLI.exe %1 %2 -iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v +iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v ..\rtl\div.v vvp out.vvp diff --git a/tests/isa/generated/rv32um-p-div b/tests/isa/generated/rv32um-p-div new file mode 100644 index 0000000000000000000000000000000000000000..3d38e37421b490571182a6132af23a8461284f51 GIT binary patch literal 5336 zcmeHLzi-n(6n>YaEfoqfxI-lvG9jiYp`jF(x&jI)0d;66ECt87jin@Z;{$<^APZ7Q zBrlAW*jQkL4MsNj53(>YFa)u5BD|M(r{2hhknTz6@5enq+n=|4extQ1gaBOy_yt-u z(ERT5P6I0FUx0a-<9$cp0dRmf&{`nN@Q*tzvkBM)Yyvg`n}AKgCSVh=3D^W|0yY7g zfKA|ECg7FO{uF@1rV0K{>2T@N-&6dV(ch1w6v*H$$%> zuNZnAIeA10#9-3DJV{GfPE>N lCFDqFNWXaz7tPXjbOzv~7Kk*5itaJ{-n#(R*$!WH-yiY9w0{5q literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-div.bin b/tests/isa/generated/rv32um-p-div.bin new file mode 100644 index 0000000000000000000000000000000000000000..e9240644c4813c7b3c9c6469a61a224c2de156fb GIT binary patch literal 392 zcmWgUWnh>L!VC_K!i)(F#^)87Ci59EOlDMINEW%zJDK6YKZN*&|C1RF7?LIKb3@cG z_zzJJ5_e!ombuRfQ4bRbnG?W}EC3Q`U=U^$fSM1q4`>(Ae0GTV2dFt9@dA+ftPpVq zsQM2;^BX|sGf!p^0Gfj=J^^GtP#k1FviJg!`HaaD1`NWy0$@MpgVcc80t_JbU;+Ti Cz(Run literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-div.dump b/tests/isa/generated/rv32um-p-div.dump new file mode 100644 index 0000000..7a5444a --- /dev/null +++ b/tests/isa/generated/rv32um-p-div.dump @@ -0,0 +1,105 @@ + +generated/rv32um-p-div: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 01400093 li ra,20 + c: 00600113 li sp,6 + 10: 0220cf33 div t5,ra,sp + 14: 00300e93 li t4,3 + 18: 00200193 li gp,2 + 1c: 0ddf1463 bne t5,t4,e4 + +00000020 : + 20: fec00093 li ra,-20 + 24: 00600113 li sp,6 + 28: 0220cf33 div t5,ra,sp + 2c: ffd00e93 li t4,-3 + 30: 00300193 li gp,3 + 34: 0bdf1863 bne t5,t4,e4 + +00000038 : + 38: 01400093 li ra,20 + 3c: ffa00113 li sp,-6 + 40: 0220cf33 div t5,ra,sp + 44: ffd00e93 li t4,-3 + 48: 00400193 li gp,4 + 4c: 09df1c63 bne t5,t4,e4 + +00000050 : + 50: fec00093 li ra,-20 + 54: ffa00113 li sp,-6 + 58: 0220cf33 div t5,ra,sp + 5c: 00300e93 li t4,3 + 60: 00500193 li gp,5 + 64: 09df1063 bne t5,t4,e4 + +00000068 : + 68: 00000093 li ra,0 + 6c: 00100113 li sp,1 + 70: 0220cf33 div t5,ra,sp + 74: 00000e93 li t4,0 + 78: 00600193 li gp,6 + 7c: 07df1463 bne t5,t4,e4 + +00000080 : + 80: 00000093 li ra,0 + 84: fff00113 li sp,-1 + 88: 0220cf33 div t5,ra,sp + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 05df1863 bne t5,t4,e4 + +00000098 : + 98: 00000093 li ra,0 + 9c: 00000113 li sp,0 + a0: 0220cf33 div t5,ra,sp + a4: fff00e93 li t4,-1 + a8: 00800193 li gp,8 + ac: 03df1c63 bne t5,t4,e4 + +000000b0 : + b0: 00100093 li ra,1 + b4: 00000113 li sp,0 + b8: 0220cf33 div t5,ra,sp + bc: fff00e93 li t4,-1 + c0: 00900193 li gp,9 + c4: 03df1063 bne t5,t4,e4 + +000000c8 : + c8: 00000093 li ra,0 + cc: 00000113 li sp,0 + d0: 0220cf33 div t5,ra,sp + d4: fff00e93 li t4,-1 + d8: 00a00193 li gp,10 + dc: 01df1463 bne t5,t4,e4 + e0: 00301863 bne zero,gp,f0 + +000000e4 : + e4: 00100d13 li s10,1 + e8: 00000d93 li s11,0 + +000000ec : + ec: 0000006f j ec + +000000f0 : + f0: 00100d13 li s10,1 + f4: 00100d93 li s11,1 + +000000f8 : + f8: 0000006f j f8 + ... + +Disassembly of section .tohost: + +00000140 : + ... + +00000180 : + ... diff --git a/tests/isa/generated/rv32um-p-div.verilog b/tests/isa/generated/rv32um-p-div.verilog new file mode 100644 index 0000000..9a61cda --- /dev/null +++ b/tests/isa/generated/rv32um-p-div.verilog @@ -0,0 +1,24 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00 +33 CF 20 02 93 0E 30 00 93 01 20 00 63 14 DF 0D +93 00 C0 FE 13 01 60 00 33 CF 20 02 93 0E D0 FF +93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF +33 CF 20 02 93 0E D0 FF 93 01 40 00 63 1C DF 09 +93 00 C0 FE 13 01 A0 FF 33 CF 20 02 93 0E 30 00 +93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00 +33 CF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07 +93 00 00 00 13 01 F0 FF 33 CF 20 02 93 0E 00 00 +93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00 +33 CF 20 02 93 0E F0 FF 93 01 80 00 63 1C DF 03 +93 00 10 00 13 01 00 00 33 CF 20 02 93 0E F0 FF +93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00 +33 CF 20 02 93 0E F0 FF 93 01 A0 00 63 14 DF 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 +@00000140 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32um-p-divu b/tests/isa/generated/rv32um-p-divu new file mode 100644 index 0000000000000000000000000000000000000000..5c13d7c3e646b199faa65cd7541c78d56d6d7a69 GIT binary patch literal 5336 zcmeHL&5P4O6o1opcP-K-8j%G(^d#aTv~JxG5zM0QDpv8ZieR9oG20EaO-x2ngf$0+ zJ&BO3hXrrFcoFJJ{R8|Ta@}J^4<5w&UM9i8lea~ffywV<-n?Xfxy|z{?RCZ&6r%*+ zpinI|_jR$-f;#%AVHRe@x>oD}*u@Pr=g5-$KNX6p1XKbl0hNGCKqa6OPzk66R01ji zm4He>C2)`l=rw?ZCYVfT_hB)umy-DgB&-h3@wAq}=U;_C{x~|5yxJKhtO3qKdRXk) zn~FWygPGu*Osis#?B4=MORHmmSZ7-Hj`2Li3BJ!cmd*)(BJ~NV|BUb<|E9?_VKMbD zCwR%A<9&m8FZr*jKl<>OzeoL!hjikHC-%Hv<{zcL;^6!#< zhfa&8lKz0&lr&sAZ{3dEFtXa$ z)^2WG-)UNFL2%jTw$=6>yKil}gTQi}jqq-7`HtZOcO%|8D_~JTOTak+O9GY!tO!^Y z&}=~8_k+%s?ezr<>?i_v_@EPcy`jw?g)Vg6o;Q?qC*pRRJm46#2u#94wEz0p9RPx-&GIReFBH3k}l&g6J;A*}` yVCI}^N;xOk#kv5^3UZ_w(r>Qfq+Z4NaTMTFArPq#4ca5ujq!fc$X3LosQV4Ie7C~@ literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-divu.bin b/tests/isa/generated/rv32um-p-divu.bin new file mode 100644 index 0000000000000000000000000000000000000000..9bfee71a129ec6473608c8626048fcf4265b4acb GIT binary patch literal 392 zcmWgUWnh>L!VC_K!i)(F#`hJNCi59EOlDMINEW-#JDK6YKbZLTeXF!4_tmYM%xJ)n zEODP3qG!Q>h#sIBj1CORGWR(ldXU8f7?K6z#z;k0QP4- ONDY`RzyM+o761T|^F_!2 literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-divu.dump b/tests/isa/generated/rv32um-p-divu.dump new file mode 100644 index 0000000..12d7306 --- /dev/null +++ b/tests/isa/generated/rv32um-p-divu.dump @@ -0,0 +1,107 @@ + +generated/rv32um-p-divu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 01400093 li ra,20 + c: 00600113 li sp,6 + 10: 0220df33 divu t5,ra,sp + 14: 00300e93 li t4,3 + 18: 00200193 li gp,2 + 1c: 0ddf1663 bne t5,t4,e8 + +00000020 : + 20: fec00093 li ra,-20 + 24: 00600113 li sp,6 + 28: 0220df33 divu t5,ra,sp + 2c: 2aaabeb7 lui t4,0x2aaab + 30: aa7e8e93 addi t4,t4,-1369 # 2aaaaaa7 + 34: 00300193 li gp,3 + 38: 0bdf1863 bne t5,t4,e8 + +0000003c : + 3c: 01400093 li ra,20 + 40: ffa00113 li sp,-6 + 44: 0220df33 divu t5,ra,sp + 48: 00000e93 li t4,0 + 4c: 00400193 li gp,4 + 50: 09df1c63 bne t5,t4,e8 + +00000054 : + 54: fec00093 li ra,-20 + 58: ffa00113 li sp,-6 + 5c: 0220df33 divu t5,ra,sp + 60: 00000e93 li t4,0 + 64: 00500193 li gp,5 + 68: 09df1063 bne t5,t4,e8 + +0000006c : + 6c: 800000b7 lui ra,0x80000 + 70: 00100113 li sp,1 + 74: 0220df33 divu t5,ra,sp + 78: 80000eb7 lui t4,0x80000 + 7c: 00600193 li gp,6 + 80: 07df1463 bne t5,t4,e8 + +00000084 : + 84: 800000b7 lui ra,0x80000 + 88: fff00113 li sp,-1 + 8c: 0220df33 divu t5,ra,sp + 90: 00000e93 li t4,0 + 94: 00700193 li gp,7 + 98: 05df1863 bne t5,t4,e8 + +0000009c : + 9c: 800000b7 lui ra,0x80000 + a0: 00000113 li sp,0 + a4: 0220df33 divu t5,ra,sp + a8: fff00e93 li t4,-1 + ac: 00800193 li gp,8 + b0: 03df1c63 bne t5,t4,e8 + +000000b4 : + b4: 00100093 li ra,1 + b8: 00000113 li sp,0 + bc: 0220df33 divu t5,ra,sp + c0: fff00e93 li t4,-1 + c4: 00900193 li gp,9 + c8: 03df1063 bne t5,t4,e8 + +000000cc : + cc: 00000093 li ra,0 + d0: 00000113 li sp,0 + d4: 0220df33 divu t5,ra,sp + d8: fff00e93 li t4,-1 + dc: 00a00193 li gp,10 + e0: 01df1463 bne t5,t4,e8 + e4: 00301863 bne zero,gp,f4 + +000000e8 : + e8: 00100d13 li s10,1 + ec: 00000d93 li s11,0 + +000000f0 : + f0: 0000006f j f0 + +000000f4 : + f4: 00100d13 li s10,1 + f8: 00100d93 li s11,1 + +000000fc : + fc: 0000006f j fc + 100: 0000 unimp + ... + +Disassembly of section .tohost: + +00000140 : + ... + +00000180 : + ... diff --git a/tests/isa/generated/rv32um-p-divu.verilog b/tests/isa/generated/rv32um-p-divu.verilog new file mode 100644 index 0000000..eeb0965 --- /dev/null +++ b/tests/isa/generated/rv32um-p-divu.verilog @@ -0,0 +1,24 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00 +33 DF 20 02 93 0E 30 00 93 01 20 00 63 16 DF 0D +93 00 C0 FE 13 01 60 00 33 DF 20 02 B7 BE AA 2A +93 8E 7E AA 93 01 30 00 63 18 DF 0B 93 00 40 01 +13 01 A0 FF 33 DF 20 02 93 0E 00 00 93 01 40 00 +63 1C DF 09 93 00 C0 FE 13 01 A0 FF 33 DF 20 02 +93 0E 00 00 93 01 50 00 63 10 DF 09 B7 00 00 80 +13 01 10 00 33 DF 20 02 B7 0E 00 80 93 01 60 00 +63 14 DF 07 B7 00 00 80 13 01 F0 FF 33 DF 20 02 +93 0E 00 00 93 01 70 00 63 18 DF 05 B7 00 00 80 +13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 80 00 +63 1C DF 03 93 00 10 00 13 01 00 00 33 DF 20 02 +93 0E F0 FF 93 01 90 00 63 10 DF 03 93 00 00 00 +13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 A0 00 +63 14 DF 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 +@00000140 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32um-p-rem b/tests/isa/generated/rv32um-p-rem new file mode 100644 index 0000000000000000000000000000000000000000..82b1da5362c74b353666f587bcdee99c5a0effeb GIT binary patch literal 5336 zcmeHLzi-n(82y~2Efoqfn4uC3o)A-%&`=5su7Cm}MU^NMmV#s4#!?cS_(1%SAPZ7Q zBrlAW*jQkL4MzTpFfcG6QN+@T@V=Z+xseSa-6x&D_uf5!wx73qex;tvZEEL zo#*WFd@Ee4lT(Ec-4r)xPJq`3#DS{cq7n8vg+9X`C)y@NZ|)F!Nj2*KS_D@vPymrRn8B z1b!_ty8%-|IWT~_A6(nXJ1m&A~^Hxj~6=Q?8n)je{;T7 CW: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 01400093 li ra,20 + c: 00600113 li sp,6 + 10: 0220ef33 rem t5,ra,sp + 14: 00200e93 li t4,2 + 18: 00200193 li gp,2 + 1c: 0ddf1463 bne t5,t4,e4 + +00000020 : + 20: fec00093 li ra,-20 + 24: 00600113 li sp,6 + 28: 0220ef33 rem t5,ra,sp + 2c: ffe00e93 li t4,-2 + 30: 00300193 li gp,3 + 34: 0bdf1863 bne t5,t4,e4 + +00000038 : + 38: 01400093 li ra,20 + 3c: ffa00113 li sp,-6 + 40: 0220ef33 rem t5,ra,sp + 44: 00200e93 li t4,2 + 48: 00400193 li gp,4 + 4c: 09df1c63 bne t5,t4,e4 + +00000050 : + 50: fec00093 li ra,-20 + 54: ffa00113 li sp,-6 + 58: 0220ef33 rem t5,ra,sp + 5c: ffe00e93 li t4,-2 + 60: 00500193 li gp,5 + 64: 09df1063 bne t5,t4,e4 + +00000068 : + 68: 00000093 li ra,0 + 6c: 00100113 li sp,1 + 70: 0220ef33 rem t5,ra,sp + 74: 00000e93 li t4,0 + 78: 00600193 li gp,6 + 7c: 07df1463 bne t5,t4,e4 + +00000080 : + 80: 00000093 li ra,0 + 84: fff00113 li sp,-1 + 88: 0220ef33 rem t5,ra,sp + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 05df1863 bne t5,t4,e4 + +00000098 : + 98: 00000093 li ra,0 + 9c: 00000113 li sp,0 + a0: 0220ef33 rem t5,ra,sp + a4: 00000e93 li t4,0 + a8: 00800193 li gp,8 + ac: 03df1c63 bne t5,t4,e4 + +000000b0 : + b0: 00100093 li ra,1 + b4: 00000113 li sp,0 + b8: 0220ef33 rem t5,ra,sp + bc: 00100e93 li t4,1 + c0: 00900193 li gp,9 + c4: 03df1063 bne t5,t4,e4 + +000000c8 : + c8: 00000093 li ra,0 + cc: 00000113 li sp,0 + d0: 0220ef33 rem t5,ra,sp + d4: 00000e93 li t4,0 + d8: 00a00193 li gp,10 + dc: 01df1463 bne t5,t4,e4 + e0: 00301863 bne zero,gp,f0 + +000000e4 : + e4: 00100d13 li s10,1 + e8: 00000d93 li s11,0 + +000000ec : + ec: 0000006f j ec + +000000f0 : + f0: 00100d13 li s10,1 + f4: 00100d93 li s11,1 + +000000f8 : + f8: 0000006f j f8 + ... + +Disassembly of section .tohost: + +00000140 : + ... + +00000180 : + ... diff --git a/tests/isa/generated/rv32um-p-rem.verilog b/tests/isa/generated/rv32um-p-rem.verilog new file mode 100644 index 0000000..d458ac2 --- /dev/null +++ b/tests/isa/generated/rv32um-p-rem.verilog @@ -0,0 +1,24 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00 +33 EF 20 02 93 0E 20 00 93 01 20 00 63 14 DF 0D +93 00 C0 FE 13 01 60 00 33 EF 20 02 93 0E E0 FF +93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF +33 EF 20 02 93 0E 20 00 93 01 40 00 63 1C DF 09 +93 00 C0 FE 13 01 A0 FF 33 EF 20 02 93 0E E0 FF +93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00 +33 EF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07 +93 00 00 00 13 01 F0 FF 33 EF 20 02 93 0E 00 00 +93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00 +33 EF 20 02 93 0E 00 00 93 01 80 00 63 1C DF 03 +93 00 10 00 13 01 00 00 33 EF 20 02 93 0E 10 00 +93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00 +33 EF 20 02 93 0E 00 00 93 01 A0 00 63 14 DF 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 +@00000140 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32um-p-remu b/tests/isa/generated/rv32um-p-remu new file mode 100644 index 0000000000000000000000000000000000000000..3fc8d8960a1fa1ed22e93419bb8865d023dc07a3 GIT binary patch literal 5336 zcmeHLF>ljA82v6uTPhS}FheC6G9jiYp`k4-xPlZA0d*(~SPG7Dn@CA);sb$@APZ7Q zBrlAW*jQkLjgI__EDQ_`MJ$~f-k0- z;x||AG^hgoJk8Ub+IRFFM7y|w*8)q1{@Y=ZO~58#6R-)`1Z)B}0h@qLz$Rc5unE`% zYy$r>0k=$)@gh&S;sGsBD~0Stg)&j0@bsjd(f-k&dX2)R$#Lc1n<~F2GT~8pcCx7a zTHim)#3qFf>qM?_^7(iko`v}fNgV}suZeq-Cpf@;gEHB`H(+KOtcs;#MZNws>7`f;4Jw}W0^ zp(IFCiiQu{X>Vs3$j76II?+yVXz+F_gOQ{*T(muk2i-W8B;#45YWi#-gATeJsovE{ zMo(q6H|$BOYB#6ycXb9fj%i-o@efLQZY+7Zeh!`GA{OWBog})E?{V{T%$`Dyx$VN2 mKr8_R&N~0*MJ%4B>+lrOXHC#~4j12J`aZfu)!B}^Xx}d=g|2u2 literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-remu.bin b/tests/isa/generated/rv32um-p-remu.bin new file mode 100644 index 0000000000000000000000000000000000000000..e494470bf2d637df7859fdbd7dcc4757ff5d4c02 GIT binary patch literal 392 zcmd6i(FwvZ5QhJ=h=@c2@u3esWQ2kXWQ2|&+yFX)BM7%ZN9iV6!3o;lH4W$n1_GCl zkMBrufY?Q%KzH2cxRY~)Py}DH6O7X@@4#(76@QqEpGYWyulZQ~%Ew8l2Ycf{Aiwo> zpYGEBq43YvG5)mvzHof`FY7k~ubs-h`fuwiw|?c;8LUs-b_h;A{o})&b@uD5&%Zef DnkhWD literal 0 HcmV?d00001 diff --git a/tests/isa/generated/rv32um-p-remu.dump b/tests/isa/generated/rv32um-p-remu.dump new file mode 100644 index 0000000..7b978c1 --- /dev/null +++ b/tests/isa/generated/rv32um-p-remu.dump @@ -0,0 +1,105 @@ + +generated/rv32um-p-remu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 01400093 li ra,20 + c: 00600113 li sp,6 + 10: 0220ff33 remu t5,ra,sp + 14: 00200e93 li t4,2 + 18: 00200193 li gp,2 + 1c: 0ddf1463 bne t5,t4,e4 + +00000020 : + 20: fec00093 li ra,-20 + 24: 00600113 li sp,6 + 28: 0220ff33 remu t5,ra,sp + 2c: 00200e93 li t4,2 + 30: 00300193 li gp,3 + 34: 0bdf1863 bne t5,t4,e4 + +00000038 : + 38: 01400093 li ra,20 + 3c: ffa00113 li sp,-6 + 40: 0220ff33 remu t5,ra,sp + 44: 01400e93 li t4,20 + 48: 00400193 li gp,4 + 4c: 09df1c63 bne t5,t4,e4 + +00000050 : + 50: fec00093 li ra,-20 + 54: ffa00113 li sp,-6 + 58: 0220ff33 remu t5,ra,sp + 5c: fec00e93 li t4,-20 + 60: 00500193 li gp,5 + 64: 09df1063 bne t5,t4,e4 + +00000068 : + 68: 00000093 li ra,0 + 6c: 00100113 li sp,1 + 70: 0220ff33 remu t5,ra,sp + 74: 00000e93 li t4,0 + 78: 00600193 li gp,6 + 7c: 07df1463 bne t5,t4,e4 + +00000080 : + 80: 00000093 li ra,0 + 84: fff00113 li sp,-1 + 88: 0220ff33 remu t5,ra,sp + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 05df1863 bne t5,t4,e4 + +00000098 : + 98: 00000093 li ra,0 + 9c: 00000113 li sp,0 + a0: 0220ff33 remu t5,ra,sp + a4: 00000e93 li t4,0 + a8: 00800193 li gp,8 + ac: 03df1c63 bne t5,t4,e4 + +000000b0 : + b0: 00100093 li ra,1 + b4: 00000113 li sp,0 + b8: 0220ff33 remu t5,ra,sp + bc: 00100e93 li t4,1 + c0: 00900193 li gp,9 + c4: 03df1063 bne t5,t4,e4 + +000000c8 : + c8: 00000093 li ra,0 + cc: 00000113 li sp,0 + d0: 0220ff33 remu t5,ra,sp + d4: 00000e93 li t4,0 + d8: 00a00193 li gp,10 + dc: 01df1463 bne t5,t4,e4 + e0: 00301863 bne zero,gp,f0 + +000000e4 : + e4: 00100d13 li s10,1 + e8: 00000d93 li s11,0 + +000000ec : + ec: 0000006f j ec + +000000f0 : + f0: 00100d13 li s10,1 + f4: 00100d93 li s11,1 + +000000f8 : + f8: 0000006f j f8 + ... + +Disassembly of section .tohost: + +00000140 : + ... + +00000180 : + ... diff --git a/tests/isa/generated/rv32um-p-remu.verilog b/tests/isa/generated/rv32um-p-remu.verilog new file mode 100644 index 0000000..60aad77 --- /dev/null +++ b/tests/isa/generated/rv32um-p-remu.verilog @@ -0,0 +1,24 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00 +33 FF 20 02 93 0E 20 00 93 01 20 00 63 14 DF 0D +93 00 C0 FE 13 01 60 00 33 FF 20 02 93 0E 20 00 +93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF +33 FF 20 02 93 0E 40 01 93 01 40 00 63 1C DF 09 +93 00 C0 FE 13 01 A0 FF 33 FF 20 02 93 0E C0 FE +93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00 +33 FF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07 +93 00 00 00 13 01 F0 FF 33 FF 20 02 93 0E 00 00 +93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00 +33 FF 20 02 93 0E 00 00 93 01 80 00 63 1C DF 03 +93 00 10 00 13 01 00 00 33 FF 20 02 93 0E 10 00 +93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00 +33 FF 20 02 93 0E 00 00 93 01 A0 00 63 14 DF 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 +@00000140 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/rv32um/Makefrag b/tests/isa/rv32um/Makefrag index 158ab95..e9f1ec0 100644 --- a/tests/isa/rv32um/Makefrag +++ b/tests/isa/rv32um/Makefrag @@ -4,6 +4,7 @@ rv32um_sc_tests = \ mul mulh mulhsu mulhu \ + div divu rem remu rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) diff --git a/tests/isa/rv32um/div.S b/tests/isa/rv32um/div.S new file mode 100644 index 0000000..a4504a7 --- /dev/null +++ b/tests/isa/rv32um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32um/divu.S b/tests/isa/rv32um/divu.S new file mode 100644 index 0000000..cd348c9 --- /dev/null +++ b/tests/isa/rv32um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 715827879, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32um/rem.S b/tests/isa/rv32um/rem.S new file mode 100644 index 0000000..c318e2c --- /dev/null +++ b/tests/isa/rv32um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32um/remu.S b/tests/isa/rv32um/remu.S new file mode 100644 index 0000000..38d641d --- /dev/null +++ b/tests/isa/rv32um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END