From 8f3aa6bb2c84601889b84e7b5a78cf600d765386 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Mon, 12 Jul 2021 18:22:02 +0800 Subject: [PATCH] tests: add random instruction Signed-off-by: liangkangnan --- tests/random_instruction/Makefile | 47 ++++++++ tests/random_instruction/link.ld | 14 +++ tests/random_instruction/riscv_test.h | 154 ++++++++++++++++++++++++++ 3 files changed, 215 insertions(+) create mode 100644 tests/random_instruction/Makefile create mode 100644 tests/random_instruction/link.ld create mode 100644 tests/random_instruction/riscv_test.h diff --git a/tests/random_instruction/Makefile b/tests/random_instruction/Makefile new file mode 100644 index 0000000..04af477 --- /dev/null +++ b/tests/random_instruction/Makefile @@ -0,0 +1,47 @@ +TORTURE_PATH := ../../tools/riscv-torture + +NUM := 0 +export NUM + +src_dir := . + +default: all + +SRCS := $(wildcard $(src_dir)/*.S) + +ELFS = $(patsubst %.S, %, $(SRCS)) + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +RISCV_PREFIX ?= /opt/riscv32/bin/riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_LD ?= $(RISCV_PREFIX)ld +RISCV_GCC_OPTS ?= -march=rv32im -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy + +BIN_TO_MEM := $(src_dir)/../../tools/BinToMem.py + +#------------------------------------------------------------ +# Build assembly tests + +%.o:%.S riscv_test.h + $(RISCV_GCC) -c $< $(RISCV_GCC_OPTS) -I$(src_dir) -o $@ + +$(ELFS):%:%.o + $(RISCV_LD) $< -T$(src_dir)/link.ld -o $@ + $(RISCV_OBJDUMP) $@ > $@.dump + $(RISCV_OBJCOPY) -O verilog $@ $@.verilog + $(RISCV_OBJCOPY) -O binary $@ $@.bin + $(BIN_TO_MEM) $@.bin $@.mem + +all: $(ELFS) + +gen: + make -C $(TORTURE_PATH) gen + mv $(TORTURE_PATH)/output/test*.S . + +clean: + rm -rf *.o $(ELFS) *.dump *.mem *.verilog *.bin diff --git a/tests/random_instruction/link.ld b/tests/random_instruction/link.ld new file mode 100644 index 0000000..e9c685d --- /dev/null +++ b/tests/random_instruction/link.ld @@ -0,0 +1,14 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x00000000; + .text.init : { *(.text.init) } + /*.tohost ALIGN(0x1000) : { *(.tohost) }*/ + /*.text ALIGN(0x1000) : { *(.text) }*/ + .data ALIGN(0x1000) : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/random_instruction/riscv_test.h b/tests/random_instruction/riscv_test.h new file mode 100644 index 0000000..352f687 --- /dev/null +++ b/tests/random_instruction/riscv_test.h @@ -0,0 +1,154 @@ +// See LICENSE for license details. + +#ifndef __RISCV_TEST_H +#define __RISCV_TEST_H + +#ifndef __riscv_xlen +#define __riscv_xlen 32 +#endif + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV64M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV64S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#define RVTEST_RV32M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV32S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#if __riscv_xlen == 64 +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: +#else +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: +#endif + +#define INIT_PMP \ + la t0, 1f; \ + csrw mtvec, t0; \ + li t0, -1; /* Set up a PMP to permit all accesses */ \ + csrw pmpaddr0, t0; \ + li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ + csrw pmpcfg0, t0; \ + .align 2; \ +1: + +#define INIT_SPTBR \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi sptbr, 0; \ + .align 2; \ +1: + +#define DELEGATE_NO_TRAPS \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi medeleg, 0; \ + csrwi mideleg, 0; \ + csrwi mie, 0; \ + .align 2; \ +1: + +#define RVTEST_ENABLE_SUPERVISOR \ + li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ + csrs mstatus, a0; \ + li a0, SIP_SSIP | SIP_STIP; \ + csrs mideleg, a0; \ + +#define RVTEST_ENABLE_MACHINE \ + li a0, MSTATUS_MPP; \ + csrs mstatus, a0; \ + +#define RVTEST_FP_ENABLE \ + li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + +#define RISCV_MULTICORE_DISABLE \ + csrr a0, mhartid; \ + 1: bnez a0, 1b + +#define EXTRA_TVEC_USER +#define EXTRA_TVEC_MACHINE +#define EXTRA_INIT +#define EXTRA_INIT_TIMER + +#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ + +#define RVTEST_CODE_BEGIN \ + .section .text.init; \ + .align 6; \ + .globl _start; \ +_start: \ + csrrwi x0, sstatus, 0x0; + +//----------------------------------------------------------------------- +// End Macro +//----------------------------------------------------------------------- + +#define RVTEST_CODE_END + + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- + +#define RVTEST_PASS \ + csrrwi x0, sstatus, 0x3; \ + ecall + +#define TESTNUM gp + +#define RVTEST_FAIL \ + csrrwi x0, sstatus, 0x1; \ + ecall + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .pushsection .tohost,"aw",@progbits; \ + .align 6; .global tohost; tohost: .dword 0; \ + .align 6; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: + +#endif