diff --git a/tests/README.md b/tests/README.md
new file mode 100644
index 0000000..408058a
--- /dev/null
+++ b/tests/README.md
@@ -0,0 +1,7 @@
+# 目录说明
+
+example：包含C语言程序例程。
+
+isa：旧的指令兼容性测试源码。RISC-V官方已经不更新了。
+
+riscv-compliance：新的指令兼容性测试源码，RISC-V官方一直在更新。
\ No newline at end of file
diff --git a/tests/riscv-compliance/COPYING.BSD b/tests/riscv-compliance/COPYING.BSD
new file mode 100644
index 0000000..1d9da10
--- /dev/null
+++ b/tests/riscv-compliance/COPYING.BSD
@@ -0,0 +1,9 @@
+Copyright (c) <year> <owner>. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file
diff --git a/tests/riscv-compliance/COPYING.CC b/tests/riscv-compliance/COPYING.CC
new file mode 100644
index 0000000..0fb847e
--- /dev/null
+++ b/tests/riscv-compliance/COPYING.CC
@@ -0,0 +1,395 @@
+Attribution 4.0 International
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diff --git a/tests/riscv-compliance/ChangeLog b/tests/riscv-compliance/ChangeLog
new file mode 100644
index 0000000..9753d20
--- /dev/null
+++ b/tests/riscv-compliance/ChangeLog
@@ -0,0 +1,281 @@
+
+2020-04-24 Allen Baum <allen.baum@esperantotech.com>
+	* fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account
+	of tests with negative offsets (which causes stores outside the signature area)
+  
+2020-03-19 Neel Gala <neelgala@gmail.com>
+    * restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable
+      tests.
+    * based on the above fixed the directory structure for riscv-targets where-ever applicable. Only
+      tested riscvOVPsim and spike.
+    * fixed script bugs for spike as well
+    * renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files
+      and Makefrag
+    * renamed mbadaddr csr to mtval as raised in issue #31
+    * C.SWSP-01.S test updated to fix issue #37
+
+2020-03-18 Neel Gala <neelgala@gmail.com>
+    * fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile
+
+2020-02-07 Prashanth Mundkur <prashanth.mundkur@gmail.com>
+    * Support F extension on RV32 sail-riscv-c.
+
+2019-12-01 Allen Baum <allen.baum@esperantotech.com>
+        * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined
+	* add more complete list of macros, their uses, parameters, and whether they are required or optional
+	* minor structural changes (moving sentences, renumbering) and typo fixes
+	* clarified impact of debug macros
+	* clarified how SIGUPD and BASEUPD must be used
+        * remove section about test taxonomy, binary tests, emulated ops
+        * clarify/fix  boundary between test target and framework responsibilities
+	   (split test target into test target and test shell)
+        * remove To Be discussed items that have been discussed
+	* remove default case condition; if conditions are unchanged, part of same case
+        *  minor grammatical changes related to the above
+
+2019-10-16 Allen Baum <allen.baum@esperantotech.com>
+	* spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range.
+
+	* more gramatical fixes, clarifications added
+	* added To Be Discussed items regarding emulated instruction and binary tests
+
+2019-09-11 Allen Baum <allen.baum@esperantotech.com>
+	* spec/TestFormatSpec.adoc:   more grammar and typo corrections and changes
+	  clarified and added To Be Discussed issues
+
+2019-09-11 Allen Baum <allen.baum@esperantotech.com>
+    * spec/TestFormatSpec.adoc:   many grammar and typo corrections and changes
+	removed many "to Be Discussed items and made them official
+	Added wording to clarify spec intent (work in progress/goal rather than final)
+	Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE
+	Added detail on proposals for connection to framework (how framework selects tests).
+	Expanded definition of signature format
+	Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure
+	Added many "future work" items related to the above
+	Added examples and comments to code examples to indicate how proposed macros would be used
+   * .gitignore: added condition to ignore Mac file system artifacts
+
+
+2019-11-05 Lee Moore <moore@imperas.com>
+    * Restructured RV32I to move Zicsr and Zifencei into their own suites
+
+2019-10-14 Lee Moore <moore@imperas.com>
+    * Added Ability to run a single test by using the Make Variable RISCV_TEST
+    for example, to only run the test I-ADD-01 from the rv32i suite
+        make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01
+    * Added Top Level Variable to Makefile RISCV_TARGET_FLAGS, 
+    in the case of the RISCV_TARGET this can be passed and appended to the invocation
+    commandline configuration, for example to pass a command line flag to the RISCV_TARGET
+    to perform tracing. The value of this flag will be target specific
+        make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace"
+    This is has also been added to all other targets to allow target configuration from
+    the commandline
+
+2019-10-07 Philipp Wagner <phw@lowrisc.org>
+    * When executing the test suite, Ibex always writes an instruction
+      log. Update the Makefile to write it to a test-specific location
+      (next to all other log files).
+    * On Ibex, provide an additional .objdump-noalias disassembly file
+      with no aliases and numeric register names (instead of ABI names).
+      This file matches the Ibex trace and can be used to debug the test
+      runs.
+
+2019-08-29 Robert Balas <balasr@iis.ee.ethz.ch>
+    * Added support for using RI5CY as a target.
+    * Added subdirectory riscv-target/ri5cy
+
+2019-08-08 Lee Moore <moore@imperas.com>
+    * Added support for lowRISC/ibex RTL as a target using Verilator.
+      In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org
+
+2019-07-18 Paul Donahue <pdonahue@ventanamicro.com>
+    * Fix typos/grammar and use correct architectural terms.
+
+2019-06-21 Ben Selfridge <benselfridge@galois.com>
+    * Added support for using the the GRIFT simulator as a target.
+    * Added subdirectory riscv-target/grift
+    * updated README.md and doc/README.adoc
+
+2019-05-23 Prashanth Mundkur <prashanth.mundkur@gmail.com>
+    * Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
+	* added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml
+	* updated README.md and doc/README.adoc
+
+2019-04-05 Allen Baum <allen.baum@esperantotech.com>
+    * spec/TestFormatSpec.adoc:  Adding details, minor corrections, ToBeDiscussed
+      items and clarifications to the specification of the future compliance test
+      suite. Also removing restrictions on having absolate addresses in signature
+
+2019-02-21 Lee Moore <moore@imperas.com>
+    * Fixed     bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0
+    * Corrected commit I-LUI-01.S, register target changed but missed assertion
+
+2019-02-21 Deborah Soung <debs@sifive.com>
+    * added RiscvFormalSpec as a target with its own unique environment
+
+2019-02-15 Radek Hajek <radek.hajek@codasip.com>
+    * updated rv32i tests to support all registers (x31) with assertions
+    * updated spec/TestFormatSpec.adoc example ISA test with new assertions
+
+2019-02-05 Deborah Soung <debs@sifive.com>
+    * [Issue #33] fixing rv32si/ma_fetch.S test
+    * [Issue #32] fixing breakpoint test
+
+2019-02-01 Lee Moore <moore@imperas.com>
+    * updated Infrastructure macros to support non-volatile registers
+    * updated riscvOVPsim
+
+2019-01-29 Deborah Soung <debs@sifive.com>
+    * Added Rocket Chip generated cores as a target
+        * riscv-target/rocket/compliance_io.h created
+	* riscv-target/rocket/compliance_test.h created
+	* riscv-target/rocket/*/Makefile.include created for existing test suites
+	* README.adoc updated with instructions for using Rocket cores as targets
+	
+2019-01-22 Premysl Vaclavik  <pvaclavik@codasip.com>
+    * feature: initial version of Compliance Test Format Specification
+        * This new document outlines how we should like the compliance
+          system to work going forward. By contrast the doc/README.adoc file
+          describes the current system as it is.
+        * Approved at Compliance TG meeting of 9 Jan 2019.
+
+2019-01-02 Radek Hajek <radek.hajek@codasip.com>
+    * unified macros in all compliance tests
+
+2018-12-20 Lee Moore <moore@imperas.com>
+    * fixed riscvOVPsim 
+
+2018-11-22 Simon Davidmann <simond@imperas.com>
+    * added information on test suite status
+    
+2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
+    * Added support for using external target directories with $TARGETDIR
+
+2018-11-21 Neel Gala <neelgala@incoresemi.com>
+   	* riscv-test-suite/rv_/references/_.reference_output: changed signature 
+	  format for all tests to include only 4-bytes per line starting with the
+  	  most significant byte on the left.
+    	* riscv-target/spike/device/rv_/Makefile.include: Added a patch for 
+	  spike-device Makefiles where the old-signature format is post-processed 
+      	  to generate a signature in the new format at the end of each test.
+	* riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above.
+    	* Makefile: default target for Makefile is now to run all tests supported by 
+	  the target mentioned defined by RISCV_TARGET variable.
+
+2018-10-11 Simon Davidmann <simond@imperas.com>
+    * Ported github riscv/riscv-tests for RV32 processors to this compliance env
+    * rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui
+
+2018-09-10  Lee Moore  <moore@imperas.com>
+	* Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to 
+	  identify untested usage cases
+	* Macro renames to support GPR, (S)FPR, (D)FPR
+	* Added test suite RV32IM to test 32 bit Multiply and Divide instructions 
+	* Added test suite RV32IMC to test 32 bit Compressed instructions
+	* Added test suite RV64I to test 64 bit Integer instructions
+	* Added test suite RV64IM to test 64 bit Multiply and Divide instructions 
+	
+	
+2018-06-15  Radek Hajek  <hajek@codasip.com>
+
+	Modifications to support Codasip simulator.
+
+	The simulator is renamed as Codasip-simulator (was
+	Codasip-IA-simulator), compliance_test.h has been moved to target
+	directories and a COMPILE_TARGET has been added to Makefile to
+	allow use of LLVM.
+
+	* Makefile: Include Codasip simulator target.
+	* riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as
+	riscv-target/Codasip-simulator/compliance_io.h.
+	* riscv-target/Codasip-simulator/compliance_io.h: Renamed from
+	riscv-target/codasip-IA-simulator/compliance_io.
+	* riscv-target/Codasip-simulator/compliance_test.h: Created.
+	* riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include:
+	Renamed as
+	riscv-target/Codasip-simulator/device/rv32i/Makefile.include
+	* riscv-target/Codasip-simulator/device/rv32i/Makefile.include:
+	Renamed from
+	riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include.
+	* riscv-test-env/compliance_test.h: Renamed as
+	riscv-target/riscvOVPsim/compliance_test.h.
+	* riscv-target/riscvOVPsim/compliance_test.h: Renamed from
+	riscv-test-env/compliance_test.h.
+	* riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated
+	for new environment.
+	* riscv-target/spike/compliance_test.h: Created.
+	* riscv-target/spike/device/rv32i/Makefile.include: Updated for
+	new environment.
+	* riscv-test-suite/rv32i/Makefile: Likewise.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	Put placeholders in empty directories to make sure they show in
+	the GitHub hierarchy.
+
+	* riscv-test-suite/rv32i/.gitignore: Created.
+	* riscv-test-suite/rv32m/.gitignore: Created.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Make references to files in the repo into links.
+
+2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* .gitignore: Ignore editor backup files.
+
+2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Add better link to documentation README.md.
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Move AsciiDoc details into new README.md in the doc
+	directory.
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Fix typo in link to AsciiDoc cheat sheet
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* COPYING.BSD: Created.
+	* COPYING.CC: Created.
+	* README.md: Add git process, licensing and engineering process.
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Correct details for running the compliance tests and
+	directory for OVPsim.
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	Clean restructuring to just the work of interest.
+
+	* thought-experiments: Directory removed.
+	* .gitignore: Merged with TestStructure/.gitignore
+	* Makefile: Renamed from TestStructure/Makefile.
+	* TestStructure/Makefile: Renamed as Makefile.
+	* README.md: Merged with TestStructure/README.md.
+	* TestStructure/.gitignore: Deleted and contents moved into
+	.gitignore.
+	* TestStructure/README.md: Deleted and contents moved into
+	README.md.
+	* TestStructure/doc: Directory deleted.
+	* TestStructure/riscv-target: Directory moved to riscv-target.
+	* riscv-target: Directory moved from TestStructure/riscv-target
+	* TestStructure/riscv-test-env: Directory moved to riscv-test-env.
+	* riscv-test-env: Directory moved from
+	TestStructure/riscv-test-env.
+	* TestStructure/riscv-test-suite: Directory moved to
+	riscv-test-suite.
+	* riscv-test-suite: Directory moved from
+	TestStructure/riscv-test-suite.
+	* thought-experiments: Directory deleted.
+
+2018-05-21  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	Initial commit to populate the repository.
+
+	* ChangeLog: Created.
+	* README.md: Created.
diff --git a/tests/riscv-compliance/Makefile b/tests/riscv-compliance/Makefile
new file mode 100644
index 0000000..0147ebc
--- /dev/null
+++ b/tests/riscv-compliance/Makefile
@@ -0,0 +1,26 @@
+
+
+SHELL=cmd
+
+export RISCV_TARGET       ?= tinyriscv
+export RISCV_PREFIX       ?= ../../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/bin/riscv-none-embed-
+
+CURDIR = $(shell echo %cd%)
+
+export ROOTDIR    = $(subst \,/,$(CURDIR))
+export TARGETDIR ?= $(ROOTDIR)/riscv-target
+
+
+default: all
+
+
+all:
+	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32i RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32i run -C $(ROOTDIR)/riscv-test-suite/rv32i
+	$(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=rv32im RISCV_PREFIX=$(RISCV_PREFIX) RISCV_ISA=rv32im run -C $(ROOTDIR)/riscv-test-suite/rv32im
+
+
+
+clean:
+	clean -C $(ROOTDIR)/riscv-test-suite/rv32i
+	clean -C $(ROOTDIR)/riscv-test-suite/rv32im
+
diff --git a/tests/riscv-compliance/README.md b/tests/riscv-compliance/README.md
new file mode 100644
index 0000000..636a7a5
--- /dev/null
+++ b/tests/riscv-compliance/README.md
@@ -0,0 +1,101 @@
+本项目fork from https://github.com/riscv/riscv-compliance，对其进行了修改以便适配tinyriscv。
+
+使用方法：
+
+1.编译：make
+
+2.重新编译：先make clean， 然后再make，编译生成的文件在build_generated目录下。
+
+# RISC-V Compliance Task Group
+
+This is a repository for the work of the RISC-V Foundation Compliance Task Group. The repository owners are:
+- Jeremy Bennett (Embecosm)
+- Lee Moore (Imperas)
+
+Details of the RISC-V Foundation, the work of its task groups, and how to become a member can be found at [riscv.org](https://riscv.org/).
+
+## Contribution process
+
+You are encouraged to contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people.
+
+- Where a pull request is non-controversial one of the repository owners will immediately merge it. The repository uses rebase merges to maintain a linear history.
+
+- Other pull requests will be publicised to the task group for comment and decision at a subsequent meeting of the group. Everyone is encouraged to comment on a pull request. Such pull requests will be merged by when a consensus/decision has been reached by the task group.
+
+## Licensing
+
+In general:
+- code is licensed under the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`); while
+- documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`).
+
+The files [`COPYING.BSD`](./COPYING.BSD) and [`COPYING.CC`](./COPYING.CC) in the top level directory contain the complete text of these licenses.
+
+## Engineering practice
+
+- Documentation uses the structured text format _AsciiDoc_.  See [`doc/README.adoc`](doc/README.adoc) for more details.
+
+- Some directories use `ChangeLog` files to track changes in the code and documentation.  Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message.
+
+- Please include a comment with the SPDX license identifier in all source files, for example:
+```
+// SPDX-License-Identifier: BSD-3-Clause
+```
+
+## Running the compliance tests
+
+The only setup required is to define where the toolchain is found, and where the target / device is found.
+
+For the toolchain, the binaries must be in the search path and the compiler prefix is defined on the make line. The default value for this is
+
+    RISCV_PREFIX ?= riscv64-unknown-elf-
+
+The path to the RUN_TARGET is defined within the riscv-target Makefile.include.
+
+To run the rv32i test suite on riscvOVPsim
+
+    make RISCV_TARGET=riscvOVPsim RISCV_DEVICE=rv32i
+
+### Accessing riscvOVPsim
+
+As we create the RISCV.org compliance test suite, the Imperas developed _riscvOVPsim_ compliance simulator is included as part of this GitHub repository. For more information please contact info@ovpworld.org or info@imperas.com.
+
+For more information on riscvOVPsim look here: [riscv-ovpsim/README.md](riscv-ovpsim/README.md) and here: [riscv-ovpsim/doc/riscvOVPsim_User_Guide.pdf](riscv-ovpsim/doc/riscvOVPsim_User_Guide.pdf).
+
+### Using the simulators from the Sail RISC-V formal model
+
+The [Sail RISC-V formal model](https://github.com/rems-project/sail-riscv) generates two
+simulators, in C and OCaml.  They can be used as test targets for this compliance suite.
+
+For this purpose, the Sail model needs to be checked out and built on
+the machine running the compliance suite.  Follow the build
+instructions described the README for building the RV32 and RV64
+models.  Once built, please add `$SAIL_RISCV/c_emulator` and
+`$SAIL_RISCV/ocaml_emulator` to your path, where $SAIL_RISCV is the
+top-level directory containing the model.
+
+To test the compliance of the C simulator for the current RV32 and RV64 tests, use
+
+    make RISCV_TARGET=sail-riscv-c all_variant
+
+while the corresponding command for the OCaml simulator is
+
+    make RISCV_TARGET=sail-riscv-ocaml all_variant
+
+### Using the GRIFT simulator
+
+The [GRIFT](https://github.com/GaloisInc/grift) formal model and simulation tool
+can be used as a test target for this compliance suite.
+
+GRIFT needs to be cloned and built on the machine running the compliance
+suite. Follow the build instructions described in the README for building the
+GRIFT simulator. Once build, add the generated `grift-sim` executable to your
+path.
+
+To test the compliance of the GRIFT simulator for the current RV32 and RV64
+tests, use
+
+    make RISCV_TARGET=grift all_variant
+
+Note that the I-MISALIGN_LDST test fails for GRIFT because GRIFT currently
+supports misaligned loads and stores in hardware, while the test is specifically
+written for systems that trap on misaligned loads and stores.
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf
new file mode 100644
index 0000000..8fd8d45
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.bin
new file mode 100644
index 0000000..df94926
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.objdump
new file mode 100644
index 0000000..084a38d
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010f8033          	add	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff00b3          	add	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00ee8133          	add	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de01b3          	add	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cd8233          	add	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd02b3          	add	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00ac8333          	add	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c03b3          	add	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008b8433          	add	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b04b3          	add	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006a8533          	add	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a05b3          	add	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	00498633          	add	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003906b3          	add	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	00288733          	add	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001807b3          	add	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	00078833          	add	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f708b3          	add	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e68933          	add	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d609b3          	add	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c58a33          	add	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b50ab3          	add	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a48b33          	add	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01940bb3          	add	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	01838c33          	add	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01730cb3          	add	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	01628d33          	add	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01520db3          	add	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	01418e33          	add	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01310eb3          	add	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	01208f33          	add	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01100fb3          	add	t6,zero,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf
new file mode 100644
index 0000000..cac25a9
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.bin
new file mode 100644
index 0000000..2a189ca
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.objdump
new file mode 100644
index 0000000..10b2d00
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ADDI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000f8013          	mv	zero,t6
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f0093          	addi	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffe8113          	addi	sp,t4,-1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e0193          	addi	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800d8213          	addi	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d0293          	addi	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800c8313          	addi	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c0393          	addi	t2,s8,1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800b8413          	addi	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b0493          	addi	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800a8513          	addi	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a0593          	mv	a1,s4
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff98613          	addi	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff90693          	addi	a3,s2,-1
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	00188713          	addi	a4,a7,1
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00080793          	mv	a5,a6
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	00078813          	mv	a6,a5
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80170893          	addi	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff68913          	addi	s2,a3,-1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80060993          	addi	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	80058a13          	addi	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80050a93          	addi	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	80048b13          	addi	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00140b93          	addi	s7,s0,1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	80038c13          	addi	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80030c93          	addi	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	80028d13          	addi	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00020d93          	mv	s11,tp
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff18e13          	addi	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff10e93          	addi	t4,sp,-1
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	00108f13          	addi	t5,ra,1
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00000f93          	li	t6,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf
new file mode 100644
index 0000000..ea189b3
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.bin
new file mode 100644
index 0000000..55e0f2e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.objdump
new file mode 100644
index 0000000..4a94212
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-AND-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010ff033          	and	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff70b3          	and	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00eef133          	and	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de71b3          	and	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cdf233          	and	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd72b3          	and	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00acf333          	and	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c73b3          	and	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008bf433          	and	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b74b3          	and	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006af533          	and	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a75b3          	and	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	0049f633          	and	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003976b3          	and	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	0028f733          	and	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001877b3          	and	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	0007f833          	and	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f778b3          	and	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e6f933          	and	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d679b3          	and	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c5fa33          	and	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b57ab3          	and	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a4fb33          	and	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01947bb3          	and	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	0183fc33          	and	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01737cb3          	and	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	0162fd33          	and	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01527db3          	and	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	0141fe33          	and	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01317eb3          	and	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	0120ff33          	and	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01107fb3          	and	t6,zero,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf
new file mode 100644
index 0000000..e97a1eb
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.bin
new file mode 100644
index 0000000..04e3f07
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.objdump
new file mode 100644
index 0000000..ee13e59
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ANDI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000ff013          	andi	zero,t6,0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f7093          	andi	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffef113          	andi	sp,t4,-1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e7193          	andi	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800df213          	andi	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d7293          	andi	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800cf313          	andi	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c7393          	andi	t2,s8,1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800bf413          	andi	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b7493          	andi	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800af513          	andi	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a7593          	andi	a1,s4,0
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff9f613          	andi	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff97693          	andi	a3,s2,-1
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0018f713          	andi	a4,a7,1
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00087793          	andi	a5,a6,0
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007f813          	andi	a6,a5,0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80177893          	andi	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff6f913          	andi	s2,a3,-1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80067993          	andi	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	8005fa13          	andi	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80057a93          	andi	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	8004fb13          	andi	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00147b93          	andi	s7,s0,1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	8003fc13          	andi	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80037c93          	andi	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	8002fd13          	andi	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00027d93          	andi	s11,tp,0
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff1fe13          	andi	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff17e93          	andi	t4,sp,-1
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0010ff13          	andi	t5,ra,1
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00007f93          	andi	t6,zero,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf
new file mode 100644
index 0000000..1638d26
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.bin
new file mode 100644
index 0000000..2bec156
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.objdump
new file mode 100644
index 0000000..9476674
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf.objdump
@@ -0,0 +1,352 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-AUIPC-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	00000017          	auipc	zero,0x0
+  8c:	00000397          	auipc	t2,0x0
+  90:	ffc38393          	addi	t2,t2,-4 # 88 <begin_testcode+0x8>
+  94:	40700033          	neg	zero,t2
+  98:	0002a023          	sw	zero,0(t0)
+  9c:	00000097          	auipc	ra,0x0
+  a0:	00000397          	auipc	t2,0x0
+  a4:	ffc38393          	addi	t2,t2,-4 # 9c <begin_testcode+0x1c>
+  a8:	407080b3          	sub	ra,ra,t2
+  ac:	0012a223          	sw	ra,4(t0)
+  b0:	007ff117          	auipc	sp,0x7ff
+  b4:	00000397          	auipc	t2,0x0
+  b8:	ffc38393          	addi	t2,t2,-4 # b0 <begin_testcode+0x30>
+  bc:	40710133          	sub	sp,sp,t2
+  c0:	0022a423          	sw	sp,8(t0)
+  c4:	00001197          	auipc	gp,0x1
+  c8:	00000397          	auipc	t2,0x0
+  cc:	ffc38393          	addi	t2,t2,-4 # c4 <begin_testcode+0x44>
+  d0:	407181b3          	sub	gp,gp,t2
+  d4:	0032a623          	sw	gp,12(t0)
+  d8:	01234217          	auipc	tp,0x1234
+  dc:	00000397          	auipc	t2,0x0
+  e0:	ffc38393          	addi	t2,t2,-4 # d8 <begin_testcode+0x58>
+  e4:	40720233          	sub	tp,tp,t2
+  e8:	0042a823          	sw	tp,16(t0)
+  ec:	00002097          	auipc	ra,0x2
+  f0:	f2808093          	addi	ra,ra,-216 # 2014 <test_2_res>
+  f4:	80000297          	auipc	t0,0x80000
+  f8:	00000197          	auipc	gp,0x0
+  fc:	ffc18193          	addi	gp,gp,-4 # f4 <begin_testcode+0x74>
+ 100:	403282b3          	sub	t0,t0,gp
+ 104:	0050a023          	sw	t0,0(ra)
+ 108:	01234317          	auipc	t1,0x1234
+ 10c:	00000197          	auipc	gp,0x0
+ 110:	ffc18193          	addi	gp,gp,-4 # 108 <begin_testcode+0x88>
+ 114:	40330333          	sub	t1,t1,gp
+ 118:	0060a223          	sw	t1,4(ra)
+ 11c:	fffff397          	auipc	t2,0xfffff
+ 120:	00000197          	auipc	gp,0x0
+ 124:	ffc18193          	addi	gp,gp,-4 # 11c <begin_testcode+0x9c>
+ 128:	403383b3          	sub	t2,t2,gp
+ 12c:	0070a423          	sw	t2,8(ra)
+ 130:	00001417          	auipc	s0,0x1
+ 134:	00000197          	auipc	gp,0x0
+ 138:	ffc18193          	addi	gp,gp,-4 # 130 <begin_testcode+0xb0>
+ 13c:	40340433          	sub	s0,s0,gp
+ 140:	0080a623          	sw	s0,12(ra)
+ 144:	7ffff497          	auipc	s1,0x7ffff
+ 148:	00000197          	auipc	gp,0x0
+ 14c:	ffc18193          	addi	gp,gp,-4 # 144 <begin_testcode+0xc4>
+ 150:	403484b3          	sub	s1,s1,gp
+ 154:	0090a823          	sw	s1,16(ra)
+ 158:	00002097          	auipc	ra,0x2
+ 15c:	ed008093          	addi	ra,ra,-304 # 2028 <test_3_res>
+ 160:	54321517          	auipc	a0,0x54321
+ 164:	00000417          	auipc	s0,0x0
+ 168:	ffc40413          	addi	s0,s0,-4 # 160 <begin_testcode+0xe0>
+ 16c:	40850533          	sub	a0,a0,s0
+ 170:	00a0a023          	sw	a0,0(ra)
+ 174:	00800597          	auipc	a1,0x800
+ 178:	00000417          	auipc	s0,0x0
+ 17c:	ffc40413          	addi	s0,s0,-4 # 174 <begin_testcode+0xf4>
+ 180:	408585b3          	sub	a1,a1,s0
+ 184:	00b0a223          	sw	a1,4(ra)
+ 188:	00000617          	auipc	a2,0x0
+ 18c:	00000417          	auipc	s0,0x0
+ 190:	ffc40413          	addi	s0,s0,-4 # 188 <begin_testcode+0x108>
+ 194:	40860633          	sub	a2,a2,s0
+ 198:	00c0a423          	sw	a2,8(ra)
+ 19c:	007ff697          	auipc	a3,0x7ff
+ 1a0:	00000417          	auipc	s0,0x0
+ 1a4:	ffc40413          	addi	s0,s0,-4 # 19c <begin_testcode+0x11c>
+ 1a8:	408686b3          	sub	a3,a3,s0
+ 1ac:	00d0a623          	sw	a3,12(ra)
+ 1b0:	00000717          	auipc	a4,0x0
+ 1b4:	00000417          	auipc	s0,0x0
+ 1b8:	ffc40413          	addi	s0,s0,-4 # 1b0 <begin_testcode+0x130>
+ 1bc:	40870733          	sub	a4,a4,s0
+ 1c0:	00e0a823          	sw	a4,16(ra)
+ 1c4:	00002117          	auipc	sp,0x2
+ 1c8:	e7810113          	addi	sp,sp,-392 # 203c <test_4_res>
+ 1cc:	00001797          	auipc	a5,0x1
+ 1d0:	00000217          	auipc	tp,0x0
+ 1d4:	ffc20213          	addi	tp,tp,-4 # 1cc <begin_testcode+0x14c>
+ 1d8:	404787b3          	sub	a5,a5,tp
+ 1dc:	00f12023          	sw	a5,0(sp)
+ 1e0:	00000817          	auipc	a6,0x0
+ 1e4:	00000217          	auipc	tp,0x0
+ 1e8:	ffc20213          	addi	tp,tp,-4 # 1e0 <begin_testcode+0x160>
+ 1ec:	40480833          	sub	a6,a6,tp
+ 1f0:	01012223          	sw	a6,4(sp)
+ 1f4:	00000897          	auipc	a7,0x0
+ 1f8:	00000217          	auipc	tp,0x0
+ 1fc:	ffc20213          	addi	tp,tp,-4 # 1f4 <begin_testcode+0x174>
+ 200:	404888b3          	sub	a7,a7,tp
+ 204:	01112423          	sw	a7,8(sp)
+ 208:	007ff917          	auipc	s2,0x7ff
+ 20c:	00000217          	auipc	tp,0x0
+ 210:	ffc20213          	addi	tp,tp,-4 # 208 <begin_testcode+0x188>
+ 214:	40490933          	sub	s2,s2,tp
+ 218:	01212623          	sw	s2,12(sp)
+ 21c:	00001997          	auipc	s3,0x1
+ 220:	00000217          	auipc	tp,0x0
+ 224:	ffc20213          	addi	tp,tp,-4 # 21c <begin_testcode+0x19c>
+ 228:	404989b3          	sub	s3,s3,tp
+ 22c:	01312823          	sw	s3,16(sp)
+ 230:	00002097          	auipc	ra,0x2
+ 234:	e2008093          	addi	ra,ra,-480 # 2050 <test_5_res>
+ 238:	01234a17          	auipc	s4,0x1234
+ 23c:	00000197          	auipc	gp,0x0
+ 240:	ffc18193          	addi	gp,gp,-4 # 238 <begin_testcode+0x1b8>
+ 244:	403a0a33          	sub	s4,s4,gp
+ 248:	0140a023          	sw	s4,0(ra)
+ 24c:	80000a97          	auipc	s5,0x80000
+ 250:	00000197          	auipc	gp,0x0
+ 254:	ffc18193          	addi	gp,gp,-4 # 24c <begin_testcode+0x1cc>
+ 258:	403a8ab3          	sub	s5,s5,gp
+ 25c:	0150a223          	sw	s5,4(ra)
+ 260:	01234b17          	auipc	s6,0x1234
+ 264:	00000197          	auipc	gp,0x0
+ 268:	ffc18193          	addi	gp,gp,-4 # 260 <begin_testcode+0x1e0>
+ 26c:	403b0b33          	sub	s6,s6,gp
+ 270:	0160a423          	sw	s6,8(ra)
+ 274:	fffffb97          	auipc	s7,0xfffff
+ 278:	00000197          	auipc	gp,0x0
+ 27c:	ffc18193          	addi	gp,gp,-4 # 274 <begin_testcode+0x1f4>
+ 280:	403b8bb3          	sub	s7,s7,gp
+ 284:	0170a623          	sw	s7,12(ra)
+ 288:	00001c17          	auipc	s8,0x1
+ 28c:	00000197          	auipc	gp,0x0
+ 290:	ffc18193          	addi	gp,gp,-4 # 288 <begin_testcode+0x208>
+ 294:	403c0c33          	sub	s8,s8,gp
+ 298:	0180a823          	sw	s8,16(ra)
+ 29c:	00002097          	auipc	ra,0x2
+ 2a0:	dc808093          	addi	ra,ra,-568 # 2064 <test_6_res>
+ 2a4:	7ffffc97          	auipc	s9,0x7ffff
+ 2a8:	00000417          	auipc	s0,0x0
+ 2ac:	ffc40413          	addi	s0,s0,-4 # 2a4 <begin_testcode+0x224>
+ 2b0:	408c8cb3          	sub	s9,s9,s0
+ 2b4:	0190a023          	sw	s9,0(ra)
+ 2b8:	54321d17          	auipc	s10,0x54321
+ 2bc:	00000417          	auipc	s0,0x0
+ 2c0:	ffc40413          	addi	s0,s0,-4 # 2b8 <begin_testcode+0x238>
+ 2c4:	408d0d33          	sub	s10,s10,s0
+ 2c8:	01a0a223          	sw	s10,4(ra)
+ 2cc:	00800d97          	auipc	s11,0x800
+ 2d0:	00000417          	auipc	s0,0x0
+ 2d4:	ffc40413          	addi	s0,s0,-4 # 2cc <begin_testcode+0x24c>
+ 2d8:	408d8db3          	sub	s11,s11,s0
+ 2dc:	01b0a423          	sw	s11,8(ra)
+ 2e0:	00000e17          	auipc	t3,0x0
+ 2e4:	00000417          	auipc	s0,0x0
+ 2e8:	ffc40413          	addi	s0,s0,-4 # 2e0 <begin_testcode+0x260>
+ 2ec:	408e0e33          	sub	t3,t3,s0
+ 2f0:	01c0a623          	sw	t3,12(ra)
+ 2f4:	007ffe97          	auipc	t4,0x7ff
+ 2f8:	00000417          	auipc	s0,0x0
+ 2fc:	ffc40413          	addi	s0,s0,-4 # 2f4 <begin_testcode+0x274>
+ 300:	408e8eb3          	sub	t4,t4,s0
+ 304:	01d0a823          	sw	t4,16(ra)
+ 308:	00002117          	auipc	sp,0x2
+ 30c:	d7010113          	addi	sp,sp,-656 # 2078 <test_7_res>
+ 310:	00000f17          	auipc	t5,0x0
+ 314:	00000217          	auipc	tp,0x0
+ 318:	ffc20213          	addi	tp,tp,-4 # 310 <begin_testcode+0x290>
+ 31c:	404f0f33          	sub	t5,t5,tp
+ 320:	01e12023          	sw	t5,0(sp)
+ 324:	00001f97          	auipc	t6,0x1
+ 328:	00000217          	auipc	tp,0x0
+ 32c:	ffc20213          	addi	tp,tp,-4 # 324 <begin_testcode+0x2a4>
+ 330:	404f8fb3          	sub	t6,t6,tp
+ 334:	01f12223          	sw	t6,4(sp)
+ 338:	00002297          	auipc	t0,0x2
+ 33c:	cc828293          	addi	t0,t0,-824 # 2000 <begin_signature>
+ 340:	10000337          	lui	t1,0x10000
+ 344:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 348:	00532023          	sw	t0,0(t1)
+ 34c:	00002297          	auipc	t0,0x2
+ 350:	d4428293          	addi	t0,t0,-700 # 2090 <end_signature>
+ 354:	10000337          	lui	t1,0x10000
+ 358:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 35c:	00532023          	sw	t0,0(t1)
+ 360:	00100293          	li	t0,1
+ 364:	10000337          	lui	t1,0x10000
+ 368:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 36c:	00532023          	sw	t0,0(t1)
+ 370:	00000013          	nop
+ 374:	00100193          	li	gp,1
+ 378:	00000073          	ecall
+
+0000037c <end_testcode>:
+ 37c:	c0001073          	unimp
+ 380:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf
new file mode 100644
index 0000000..13ec124
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.bin
new file mode 100644
index 0000000..6310dad
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.objdump
new file mode 100644
index 0000000..67c2a1c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BEQ-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010f8663          	beq	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff0663          	beq	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feee86e3          	beq	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de0663          	beq	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cd8663          	beq	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd0663          	beq	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00ac8663          	beq	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c04e3          	beq	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008b8663          	beq	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b0663          	beq	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006a8663          	beq	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a0663          	beq	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe4984e3          	beq	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00390663          	beq	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	00288663          	beq	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00180663          	beq	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	00078663          	beqz	a5,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff706e3          	beq	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e68663          	beq	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d60663          	beq	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c58663          	beq	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b50663          	beq	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa484e3          	beq	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01940663          	beq	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	01838663          	beq	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01730663          	beq	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	01628663          	beq	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5206e3          	beq	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	01418663          	beq	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01310663          	beq	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	01208663          	beq	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01100663          	beq	zero,a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf
new file mode 100644
index 0000000..9145d4e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.bin
new file mode 100644
index 0000000..d6f1732
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.objdump
new file mode 100644
index 0000000..848a176
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BGE-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010fd663          	bge	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff5663          	bge	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feeed6e3          	bge	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de5663          	bge	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cdd663          	bge	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd5663          	bge	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00acd663          	bge	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c54e3          	bge	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008bd663          	bge	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b5663          	bge	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006ad663          	bge	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a5663          	bge	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe49d4e3          	bge	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00395663          	bge	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	0028d663          	bge	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00185663          	bge	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	0007d663          	bgez	a5,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff756e3          	bge	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e6d663          	bge	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d65663          	bge	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c5d663          	bge	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b55663          	bge	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa4d4e3          	bge	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01945663          	bge	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	0183d663          	bge	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01735663          	bge	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	0162d663          	bge	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5256e3          	bge	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	0141d663          	bge	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01315663          	bge	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	0120d663          	bge	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01105663          	blez	a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf
new file mode 100644
index 0000000..d7e57e4
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.bin
new file mode 100644
index 0000000..5164b87
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.objdump
new file mode 100644
index 0000000..9aaf132
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BGEU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010ff663          	bgeu	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff7663          	bgeu	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feeef6e3          	bgeu	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de7663          	bgeu	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cdf663          	bgeu	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd7663          	bgeu	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00acf663          	bgeu	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c74e3          	bgeu	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008bf663          	bgeu	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b7663          	bgeu	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006af663          	bgeu	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a7663          	bgeu	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe49f4e3          	bgeu	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00397663          	bgeu	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	0028f663          	bgeu	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00187663          	bgeu	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	0007f663          	bgeu	a5,zero,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff776e3          	bgeu	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e6f663          	bgeu	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d67663          	bgeu	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c5f663          	bgeu	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b57663          	bgeu	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa4f4e3          	bgeu	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01947663          	bgeu	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	0183f663          	bgeu	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01737663          	bgeu	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	0162f663          	bgeu	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5276e3          	bgeu	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	0141f663          	bgeu	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01317663          	bgeu	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	0120f663          	bgeu	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01107663          	bgeu	zero,a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf
new file mode 100644
index 0000000..ad2d801
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.bin
new file mode 100644
index 0000000..3ba7815
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.objdump
new file mode 100644
index 0000000..0245f22
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BLT-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010fc663          	blt	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff4663          	blt	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feeec6e3          	blt	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de4663          	blt	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cdc663          	blt	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd4663          	blt	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00acc663          	blt	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c44e3          	blt	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008bc663          	blt	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b4663          	blt	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006ac663          	blt	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a4663          	blt	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe49c4e3          	blt	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00394663          	blt	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	0028c663          	blt	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00184663          	blt	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	0007c663          	bltz	a5,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff746e3          	blt	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e6c663          	blt	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d64663          	blt	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c5c663          	blt	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b54663          	blt	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa4c4e3          	blt	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01944663          	blt	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	0183c663          	blt	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01734663          	blt	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	0162c663          	blt	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5246e3          	blt	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	0141c663          	blt	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01314663          	blt	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	0120c663          	blt	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01104663          	bgtz	a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf
new file mode 100644
index 0000000..9bce13f
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.bin
new file mode 100644
index 0000000..b79b5a3
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.objdump
new file mode 100644
index 0000000..8c41620
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BLTU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010fe663          	bltu	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff6663          	bltu	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feeee6e3          	bltu	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de6663          	bltu	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cde663          	bltu	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd6663          	bltu	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00ace663          	bltu	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c64e3          	bltu	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008be663          	bltu	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b6663          	bltu	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006ae663          	bltu	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a6663          	bltu	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe49e4e3          	bltu	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00396663          	bltu	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	0028e663          	bltu	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00186663          	bltu	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	0007e663          	bltu	a5,zero,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff766e3          	bltu	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e6e663          	bltu	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d66663          	bltu	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c5e663          	bltu	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b56663          	bltu	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa4e4e3          	bltu	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01946663          	bltu	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	0183e663          	bltu	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01736663          	bltu	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	0162e663          	bltu	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5266e3          	bltu	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	0141e663          	bltu	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01316663          	bltu	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	0120e663          	bltu	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01106663          	bltu	zero,a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf
new file mode 100644
index 0000000..1f23393
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.bin
new file mode 100644
index 0000000..4429bf3
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.objdump
new file mode 100644
index 0000000..ddaf1f8
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf.objdump
@@ -0,0 +1,480 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-BNE-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	0000d0b7          	lui	ra,0xd
+  8c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  90:	fff00f93          	li	t6,-1
+  94:	00000813          	li	a6,0
+  98:	010f9663          	bne	t6,a6,a4 <begin_testcode+0x24>
+  9c:	000120b7          	lui	ra,0x12
+  a0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  a4:	00112023          	sw	ra,0(sp)
+  a8:	0000d0b7          	lui	ra,0xd
+  ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  b0:	00100f13          	li	t5,1
+  b4:	80100793          	li	a5,-2047
+  b8:	00ff1663          	bne	t5,a5,c4 <begin_testcode+0x44>
+  bc:	000120b7          	lui	ra,0x12
+  c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  c4:	00112223          	sw	ra,4(sp)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000d0b7          	lui	ra,0xd
+  d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  d8:	00000e93          	li	t4,0
+  dc:	fff00713          	li	a4,-1
+  e0:	feee96e3          	bne	t4,a4,cc <begin_testcode+0x4c>
+  e4:	000120b7          	lui	ra,0x12
+  e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  ec:	00112423          	sw	ra,8(sp)
+  f0:	0000d0b7          	lui	ra,0xd
+  f4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  f8:	7ff00e13          	li	t3,2047
+  fc:	fffff6b7          	lui	a3,0xfffff
+ 100:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+ 104:	00de1663          	bne	t3,a3,110 <begin_testcode+0x90>
+ 108:	000120b7          	lui	ra,0x12
+ 10c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 110:	00112623          	sw	ra,12(sp)
+ 114:	0000d0b7          	lui	ra,0xd
+ 118:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 11c:	00000d93          	li	s11,0
+ 120:	80000637          	lui	a2,0x80000
+ 124:	00cd9663          	bne	s11,a2,130 <begin_testcode+0xb0>
+ 128:	000120b7          	lui	ra,0x12
+ 12c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 130:	00112823          	sw	ra,16(sp)
+ 134:	00002117          	auipc	sp,0x2
+ 138:	ee010113          	addi	sp,sp,-288 # 2014 <test_2_res>
+ 13c:	0000d0b7          	lui	ra,0xd
+ 140:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 144:	00001d37          	lui	s10,0x1
+ 148:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x284>
+ 14c:	000015b7          	lui	a1,0x1
+ 150:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+ 154:	00bd1663          	bne	s10,a1,160 <begin_testcode+0xe0>
+ 158:	000120b7          	lui	ra,0x12
+ 15c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 160:	00112023          	sw	ra,0(sp)
+ 164:	0000d0b7          	lui	ra,0xd
+ 168:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 16c:	07654cb7          	lui	s9,0x7654
+ 170:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 174:	fff00513          	li	a0,-1
+ 178:	00ac9663          	bne	s9,a0,184 <begin_testcode+0x104>
+ 17c:	000120b7          	lui	ra,0x12
+ 180:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 184:	00112223          	sw	ra,4(sp)
+ 188:	0080006f          	j	190 <begin_testcode+0x110>
+ 18c:	0240006f          	j	1b0 <begin_testcode+0x130>
+ 190:	0000d0b7          	lui	ra,0xd
+ 194:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 198:	80000c37          	lui	s8,0x80000
+ 19c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a0:	00100493          	li	s1,1
+ 1a4:	fe9c14e3          	bne	s8,s1,18c <begin_testcode+0x10c>
+ 1a8:	000120b7          	lui	ra,0x12
+ 1ac:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1b0:	00112423          	sw	ra,8(sp)
+ 1b4:	0000d0b7          	lui	ra,0xd
+ 1b8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1bc:	00100b93          	li	s7,1
+ 1c0:	80000437          	lui	s0,0x80000
+ 1c4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1c8:	008b9663          	bne	s7,s0,1d4 <begin_testcode+0x154>
+ 1cc:	000120b7          	lui	ra,0x12
+ 1d0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1d4:	00112623          	sw	ra,12(sp)
+ 1d8:	0000d0b7          	lui	ra,0xd
+ 1dc:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 1e0:	fff00b13          	li	s6,-1
+ 1e4:	076543b7          	lui	t2,0x7654
+ 1e8:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 1ec:	007b1663          	bne	s6,t2,1f8 <begin_testcode+0x178>
+ 1f0:	000120b7          	lui	ra,0x12
+ 1f4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 1f8:	00112823          	sw	ra,16(sp)
+ 1fc:	00002397          	auipc	t2,0x2
+ 200:	e2c38393          	addi	t2,t2,-468 # 2028 <test_3_res>
+ 204:	0000d0b7          	lui	ra,0xd
+ 208:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 20c:	00001ab7          	lui	s5,0x1
+ 210:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 214:	00001337          	lui	t1,0x1
+ 218:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x284>
+ 21c:	006a9663          	bne	s5,t1,228 <begin_testcode+0x1a8>
+ 220:	000120b7          	lui	ra,0x12
+ 224:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 228:	0013a023          	sw	ra,0(t2)
+ 22c:	0000d0b7          	lui	ra,0xd
+ 230:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 234:	80000a37          	lui	s4,0x80000
+ 238:	00000293          	li	t0,0
+ 23c:	005a1663          	bne	s4,t0,248 <begin_testcode+0x1c8>
+ 240:	000120b7          	lui	ra,0x12
+ 244:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 248:	0013a223          	sw	ra,4(t2)
+ 24c:	0080006f          	j	254 <begin_testcode+0x1d4>
+ 250:	0240006f          	j	274 <begin_testcode+0x1f4>
+ 254:	0000d0b7          	lui	ra,0xd
+ 258:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 25c:	fffff9b7          	lui	s3,0xfffff
+ 260:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 264:	7ff00213          	li	tp,2047
+ 268:	fe4994e3          	bne	s3,tp,250 <begin_testcode+0x1d0>
+ 26c:	000120b7          	lui	ra,0x12
+ 270:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 274:	0013a423          	sw	ra,8(t2)
+ 278:	0000d0b7          	lui	ra,0xd
+ 27c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 280:	fff00913          	li	s2,-1
+ 284:	fff00193          	li	gp,-1
+ 288:	00391663          	bne	s2,gp,294 <begin_testcode+0x214>
+ 28c:	000120b7          	lui	ra,0x12
+ 290:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 294:	0013a623          	sw	ra,12(t2)
+ 298:	0000d0b7          	lui	ra,0xd
+ 29c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2a0:	80100893          	li	a7,-2047
+ 2a4:	00100113          	li	sp,1
+ 2a8:	00289663          	bne	a7,sp,2b4 <begin_testcode+0x234>
+ 2ac:	000120b7          	lui	ra,0x12
+ 2b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2b4:	0013a823          	sw	ra,16(t2)
+ 2b8:	00002197          	auipc	gp,0x2
+ 2bc:	d8418193          	addi	gp,gp,-636 # 203c <test_4_res>
+ 2c0:	0000d137          	lui	sp,0xd
+ 2c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 2c8:	00000813          	li	a6,0
+ 2cc:	00000093          	li	ra,0
+ 2d0:	00181663          	bne	a6,ra,2dc <begin_testcode+0x25c>
+ 2d4:	00012137          	lui	sp,0x12
+ 2d8:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 2dc:	0021a023          	sw	sp,0(gp)
+ 2e0:	0000d0b7          	lui	ra,0xd
+ 2e4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 2e8:	fff00793          	li	a5,-1
+ 2ec:	00000013          	nop
+ 2f0:	00079663          	bnez	a5,2fc <begin_testcode+0x27c>
+ 2f4:	000120b7          	lui	ra,0x12
+ 2f8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 2fc:	0011a223          	sw	ra,4(gp)
+ 300:	0080006f          	j	308 <begin_testcode+0x288>
+ 304:	0200006f          	j	324 <begin_testcode+0x2a4>
+ 308:	0000d0b7          	lui	ra,0xd
+ 30c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 310:	00100713          	li	a4,1
+ 314:	80100f93          	li	t6,-2047
+ 318:	fff716e3          	bne	a4,t6,304 <begin_testcode+0x284>
+ 31c:	000120b7          	lui	ra,0x12
+ 320:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 324:	0011a423          	sw	ra,8(gp)
+ 328:	0000d0b7          	lui	ra,0xd
+ 32c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 330:	00000693          	li	a3,0
+ 334:	fff00f13          	li	t5,-1
+ 338:	01e69663          	bne	a3,t5,344 <begin_testcode+0x2c4>
+ 33c:	000120b7          	lui	ra,0x12
+ 340:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 344:	0011a623          	sw	ra,12(gp)
+ 348:	0000d0b7          	lui	ra,0xd
+ 34c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 350:	7ff00613          	li	a2,2047
+ 354:	fffffeb7          	lui	t4,0xfffff
+ 358:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 35c:	01d61663          	bne	a2,t4,368 <begin_testcode+0x2e8>
+ 360:	000120b7          	lui	ra,0x12
+ 364:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 368:	0011a823          	sw	ra,16(gp)
+ 36c:	00002117          	auipc	sp,0x2
+ 370:	ce410113          	addi	sp,sp,-796 # 2050 <test_5_res>
+ 374:	0000d0b7          	lui	ra,0xd
+ 378:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 37c:	00000593          	li	a1,0
+ 380:	80000e37          	lui	t3,0x80000
+ 384:	01c59663          	bne	a1,t3,390 <begin_testcode+0x310>
+ 388:	000120b7          	lui	ra,0x12
+ 38c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 390:	00112023          	sw	ra,0(sp)
+ 394:	0000d0b7          	lui	ra,0xd
+ 398:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 39c:	00001537          	lui	a0,0x1
+ 3a0:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x284>
+ 3a4:	00001db7          	lui	s11,0x1
+ 3a8:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 3ac:	01b51663          	bne	a0,s11,3b8 <begin_testcode+0x338>
+ 3b0:	000120b7          	lui	ra,0x12
+ 3b4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3b8:	00112223          	sw	ra,4(sp)
+ 3bc:	0080006f          	j	3c4 <begin_testcode+0x344>
+ 3c0:	0240006f          	j	3e4 <begin_testcode+0x364>
+ 3c4:	0000d0b7          	lui	ra,0xd
+ 3c8:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3cc:	076544b7          	lui	s1,0x7654
+ 3d0:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 3d4:	fff00d13          	li	s10,-1
+ 3d8:	ffa494e3          	bne	s1,s10,3c0 <begin_testcode+0x340>
+ 3dc:	000120b7          	lui	ra,0x12
+ 3e0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 3e4:	00112423          	sw	ra,8(sp)
+ 3e8:	0000d0b7          	lui	ra,0xd
+ 3ec:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 3f0:	80000437          	lui	s0,0x80000
+ 3f4:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 3f8:	00100c93          	li	s9,1
+ 3fc:	01941663          	bne	s0,s9,408 <begin_testcode+0x388>
+ 400:	000120b7          	lui	ra,0x12
+ 404:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 408:	00112623          	sw	ra,12(sp)
+ 40c:	0000d0b7          	lui	ra,0xd
+ 410:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 414:	00100393          	li	t2,1
+ 418:	80000c37          	lui	s8,0x80000
+ 41c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 420:	01839663          	bne	t2,s8,42c <begin_testcode+0x3ac>
+ 424:	000120b7          	lui	ra,0x12
+ 428:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 42c:	00112823          	sw	ra,16(sp)
+ 430:	00002397          	auipc	t2,0x2
+ 434:	c3438393          	addi	t2,t2,-972 # 2064 <test_6_res>
+ 438:	0000d0b7          	lui	ra,0xd
+ 43c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 440:	fff00313          	li	t1,-1
+ 444:	07654bb7          	lui	s7,0x7654
+ 448:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 44c:	01731663          	bne	t1,s7,458 <begin_testcode+0x3d8>
+ 450:	000120b7          	lui	ra,0x12
+ 454:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 458:	0013a023          	sw	ra,0(t2)
+ 45c:	0000d0b7          	lui	ra,0xd
+ 460:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 464:	000012b7          	lui	t0,0x1
+ 468:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 46c:	00001b37          	lui	s6,0x1
+ 470:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x284>
+ 474:	01629663          	bne	t0,s6,480 <begin_testcode+0x400>
+ 478:	000120b7          	lui	ra,0x12
+ 47c:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 480:	0013a223          	sw	ra,4(t2)
+ 484:	0080006f          	j	48c <begin_testcode+0x40c>
+ 488:	0200006f          	j	4a8 <begin_testcode+0x428>
+ 48c:	0000d0b7          	lui	ra,0xd
+ 490:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 494:	80000237          	lui	tp,0x80000
+ 498:	00000a93          	li	s5,0
+ 49c:	ff5216e3          	bne	tp,s5,488 <begin_testcode+0x408>
+ 4a0:	000120b7          	lui	ra,0x12
+ 4a4:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4a8:	0013a423          	sw	ra,8(t2)
+ 4ac:	0000d0b7          	lui	ra,0xd
+ 4b0:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b4:	fffff1b7          	lui	gp,0xfffff
+ 4b8:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 4bc:	7ff00a13          	li	s4,2047
+ 4c0:	01419663          	bne	gp,s4,4cc <begin_testcode+0x44c>
+ 4c4:	000120b7          	lui	ra,0x12
+ 4c8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4cc:	0013a623          	sw	ra,12(t2)
+ 4d0:	0000d0b7          	lui	ra,0xd
+ 4d4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4d8:	fff00113          	li	sp,-1
+ 4dc:	fff00993          	li	s3,-1
+ 4e0:	01311663          	bne	sp,s3,4ec <begin_testcode+0x46c>
+ 4e4:	000120b7          	lui	ra,0x12
+ 4e8:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4ec:	0013a823          	sw	ra,16(t2)
+ 4f0:	00002197          	auipc	gp,0x2
+ 4f4:	b8818193          	addi	gp,gp,-1144 # 2078 <test_7_res>
+ 4f8:	0000d137          	lui	sp,0xd
+ 4fc:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 500:	80100093          	li	ra,-2047
+ 504:	00100913          	li	s2,1
+ 508:	01209663          	bne	ra,s2,514 <begin_testcode+0x494>
+ 50c:	00012137          	lui	sp,0x12
+ 510:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 514:	0021a023          	sw	sp,0(gp)
+ 518:	0000d0b7          	lui	ra,0xd
+ 51c:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 520:	00000013          	nop
+ 524:	00000893          	li	a7,0
+ 528:	01101663          	bne	zero,a7,534 <begin_testcode+0x4b4>
+ 52c:	000120b7          	lui	ra,0x12
+ 530:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 534:	0011a223          	sw	ra,4(gp)
+ 538:	00002297          	auipc	t0,0x2
+ 53c:	ac828293          	addi	t0,t0,-1336 # 2000 <begin_signature>
+ 540:	10000337          	lui	t1,0x10000
+ 544:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 548:	00532023          	sw	t0,0(t1)
+ 54c:	00002297          	auipc	t0,0x2
+ 550:	b4428293          	addi	t0,t0,-1212 # 2090 <end_signature>
+ 554:	10000337          	lui	t1,0x10000
+ 558:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 55c:	00532023          	sw	t0,0(t1)
+ 560:	00100293          	li	t0,1
+ 564:	10000337          	lui	t1,0x10000
+ 568:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 56c:	00532023          	sw	t0,0(t1)
+ 570:	00000013          	nop
+ 574:	00100193          	li	gp,1
+ 578:	00000073          	ecall
+
+0000057c <end_testcode>:
+ 57c:	c0001073          	unimp
+ 580:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf
new file mode 100644
index 0000000..4709737
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.bin
new file mode 100644
index 0000000..b76ab6c
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.objdump
new file mode 100644
index 0000000..f3efe50
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf.objdump
@@ -0,0 +1,193 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-DELAY_SLOTS-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002097          	auipc	ra,0x2
+  84:	f8008093          	addi	ra,ra,-128 # 2000 <begin_signature>
+  88:	11111137          	lui	sp,0x11111
+  8c:	11110113          	addi	sp,sp,273 # 11111111 <_end+0x1110ef0d>
+  90:	0080006f          	j	98 <begin_testcode+0x18>
+  94:	00000113          	li	sp,0
+  98:	0020a023          	sw	sp,0(ra)
+  9c:	00002097          	auipc	ra,0x2
+  a0:	f6808093          	addi	ra,ra,-152 # 2004 <test_A2_res>
+  a4:	22222137          	lui	sp,0x22222
+  a8:	22210113          	addi	sp,sp,546 # 22222222 <_end+0x2222001e>
+  ac:	00000217          	auipc	tp,0x0
+  b0:	01020213          	addi	tp,tp,16 # bc <begin_testcode+0x3c>
+  b4:	00020067          	jr	tp # 0 <_start>
+  b8:	00000113          	li	sp,0
+  bc:	0020a023          	sw	sp,0(ra)
+  c0:	00002097          	auipc	ra,0x2
+  c4:	f4808093          	addi	ra,ra,-184 # 2008 <test_B1_res>
+  c8:	00500293          	li	t0,5
+  cc:	00600313          	li	t1,6
+  d0:	33333137          	lui	sp,0x33333
+  d4:	33310113          	addi	sp,sp,819 # 33333333 <_end+0x3333112f>
+  d8:	00528463          	beq	t0,t0,e0 <begin_testcode+0x60>
+  dc:	00000113          	li	sp,0
+  e0:	0020a023          	sw	sp,0(ra)
+  e4:	00002097          	auipc	ra,0x2
+  e8:	f2808093          	addi	ra,ra,-216 # 200c <test_B2_res>
+  ec:	00500293          	li	t0,5
+  f0:	00600313          	li	t1,6
+  f4:	44444137          	lui	sp,0x44444
+  f8:	44410113          	addi	sp,sp,1092 # 44444444 <_end+0x44442240>
+  fc:	00629463          	bne	t0,t1,104 <begin_testcode+0x84>
+ 100:	00000113          	li	sp,0
+ 104:	0020a023          	sw	sp,0(ra)
+ 108:	00002097          	auipc	ra,0x2
+ 10c:	f0808093          	addi	ra,ra,-248 # 2010 <test_B3_res>
+ 110:	00500293          	li	t0,5
+ 114:	00600313          	li	t1,6
+ 118:	55555137          	lui	sp,0x55555
+ 11c:	55510113          	addi	sp,sp,1365 # 55555555 <_end+0x55553351>
+ 120:	0062c463          	blt	t0,t1,128 <begin_testcode+0xa8>
+ 124:	00000113          	li	sp,0
+ 128:	0020a023          	sw	sp,0(ra)
+ 12c:	00002097          	auipc	ra,0x2
+ 130:	ee808093          	addi	ra,ra,-280 # 2014 <test_B4_res>
+ 134:	00500293          	li	t0,5
+ 138:	00600313          	li	t1,6
+ 13c:	66666137          	lui	sp,0x66666
+ 140:	66610113          	addi	sp,sp,1638 # 66666666 <_end+0x66664462>
+ 144:	0062e463          	bltu	t0,t1,14c <begin_testcode+0xcc>
+ 148:	00000113          	li	sp,0
+ 14c:	0020a023          	sw	sp,0(ra)
+ 150:	00002097          	auipc	ra,0x2
+ 154:	ec808093          	addi	ra,ra,-312 # 2018 <test_B5_res>
+ 158:	00500293          	li	t0,5
+ 15c:	00600313          	li	t1,6
+ 160:	77777137          	lui	sp,0x77777
+ 164:	77710113          	addi	sp,sp,1911 # 77777777 <_end+0x77775573>
+ 168:	00535463          	bge	t1,t0,170 <begin_testcode+0xf0>
+ 16c:	00000113          	li	sp,0
+ 170:	0020a023          	sw	sp,0(ra)
+ 174:	00002097          	auipc	ra,0x2
+ 178:	ea808093          	addi	ra,ra,-344 # 201c <test_B6_res>
+ 17c:	00500293          	li	t0,5
+ 180:	00600313          	li	t1,6
+ 184:	88889137          	lui	sp,0x88889
+ 188:	88810113          	addi	sp,sp,-1912 # 88888888 <_end+0x88886684>
+ 18c:	00537463          	bgeu	t1,t0,194 <begin_testcode+0x114>
+ 190:	00000113          	li	sp,0
+ 194:	0020a023          	sw	sp,0(ra)
+ 198:	00002297          	auipc	t0,0x2
+ 19c:	e6828293          	addi	t0,t0,-408 # 2000 <begin_signature>
+ 1a0:	10000337          	lui	t1,0x10000
+ 1a4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 1a8:	00532023          	sw	t0,0(t1)
+ 1ac:	00002297          	auipc	t0,0x2
+ 1b0:	e7428293          	addi	t0,t0,-396 # 2020 <end_signature>
+ 1b4:	10000337          	lui	t1,0x10000
+ 1b8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 1bc:	00532023          	sw	t0,0(t1)
+ 1c0:	00100293          	li	t0,1
+ 1c4:	10000337          	lui	t1,0x10000
+ 1c8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 1cc:	00532023          	sw	t0,0(t1)
+ 1d0:	00000013          	nop
+ 1d4:	00100193          	li	gp,1
+ 1d8:	00000073          	ecall
+
+000001dc <end_testcode>:
+ 1dc:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+
+00002004 <test_A2_res>:
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+
+00002008 <test_B1_res>:
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+
+0000200c <test_B2_res>:
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+
+00002010 <test_B3_res>:
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_B4_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_B5_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+
+0000201c <test_B6_res>:
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+
+00002020 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf
new file mode 100644
index 0000000..1bf1a26
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.bin
new file mode 100644
index 0000000..1e5ece9
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.objdump
new file mode 100644
index 0000000..bec9f00
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf.objdump
@@ -0,0 +1,125 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-EBREAK-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00000097          	auipc	ra,0x0
+  84:	02c08093          	addi	ra,ra,44 # ac <_trap_handler>
+  88:	30509ff3          	csrrw	t6,mtvec,ra
+  8c:	00002097          	auipc	ra,0x2
+  90:	f7408093          	addi	ra,ra,-140 # 2000 <begin_signature>
+  94:	11111137          	lui	sp,0x11111
+  98:	11110113          	addi	sp,sp,273 # 11111111 <_end+0x1110ef0d>
+  9c:	00100073          	ebreak
+  a0:	0000a023          	sw	zero,0(ra)
+  a4:	305f9073          	csrw	mtvec,t6
+  a8:	0280006f          	j	d0 <test_end>
+
+000000ac <_trap_handler>:
+  ac:	34102f73          	csrr	t5,mepc
+  b0:	004f0f13          	addi	t5,t5,4
+  b4:	341f1073          	csrw	mepc,t5
+  b8:	34202f73          	csrr	t5,mcause
+  bc:	01e0a023          	sw	t5,0(ra)
+  c0:	0020a223          	sw	sp,4(ra)
+  c4:	0000a423          	sw	zero,8(ra)
+  c8:	00c08093          	addi	ra,ra,12
+  cc:	30200073          	mret
+
+000000d0 <test_end>:
+  d0:	00002297          	auipc	t0,0x2
+  d4:	f3028293          	addi	t0,t0,-208 # 2000 <begin_signature>
+  d8:	10000337          	lui	t1,0x10000
+  dc:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+  e0:	00532023          	sw	t0,0(t1)
+  e4:	00002297          	auipc	t0,0x2
+  e8:	f2c28293          	addi	t0,t0,-212 # 2010 <end_signature>
+  ec:	10000337          	lui	t1,0x10000
+  f0:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+  f4:	00532023          	sw	t0,0(t1)
+  f8:	00100293          	li	t0,1
+  fc:	10000337          	lui	t1,0x10000
+ 100:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 104:	00532023          	sw	t0,0(t1)
+ 108:	00000013          	nop
+ 10c:	00100193          	li	gp,1
+ 110:	00000073          	ecall
+
+00000114 <end_testcode>:
+ 114:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+
+00002010 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf
new file mode 100644
index 0000000..ebd943c
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.bin
new file mode 100644
index 0000000..832273b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.objdump
new file mode 100644
index 0000000..8a94d90
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf.objdump
@@ -0,0 +1,125 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ECALL-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00000097          	auipc	ra,0x0
+  84:	02c08093          	addi	ra,ra,44 # ac <_trap_handler>
+  88:	30509ff3          	csrrw	t6,mtvec,ra
+  8c:	00002097          	auipc	ra,0x2
+  90:	f7408093          	addi	ra,ra,-140 # 2000 <begin_signature>
+  94:	11111137          	lui	sp,0x11111
+  98:	11110113          	addi	sp,sp,273 # 11111111 <_end+0x1110ef0d>
+  9c:	00000073          	ecall
+  a0:	0000a023          	sw	zero,0(ra)
+  a4:	305f9073          	csrw	mtvec,t6
+  a8:	0280006f          	j	d0 <test_end>
+
+000000ac <_trap_handler>:
+  ac:	34102f73          	csrr	t5,mepc
+  b0:	004f0f13          	addi	t5,t5,4
+  b4:	341f1073          	csrw	mepc,t5
+  b8:	34202f73          	csrr	t5,mcause
+  bc:	01e0a023          	sw	t5,0(ra)
+  c0:	0020a223          	sw	sp,4(ra)
+  c4:	0000a423          	sw	zero,8(ra)
+  c8:	00c08093          	addi	ra,ra,12
+  cc:	30200073          	mret
+
+000000d0 <test_end>:
+  d0:	00002297          	auipc	t0,0x2
+  d4:	f3028293          	addi	t0,t0,-208 # 2000 <begin_signature>
+  d8:	10000337          	lui	t1,0x10000
+  dc:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+  e0:	00532023          	sw	t0,0(t1)
+  e4:	00002297          	auipc	t0,0x2
+  e8:	f2c28293          	addi	t0,t0,-212 # 2010 <end_signature>
+  ec:	10000337          	lui	t1,0x10000
+  f0:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+  f4:	00532023          	sw	t0,0(t1)
+  f8:	00100293          	li	t0,1
+  fc:	10000337          	lui	t1,0x10000
+ 100:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 104:	00532023          	sw	t0,0(t1)
+ 108:	00000013          	nop
+ 10c:	00100193          	li	gp,1
+ 110:	00000073          	ecall
+
+00000114 <end_testcode>:
+ 114:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+
+00002010 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf
new file mode 100644
index 0000000..dc09faa
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.bin
new file mode 100644
index 0000000..9ad5324
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.objdump
new file mode 100644
index 0000000..023e7cd
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf.objdump
@@ -0,0 +1,136 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ENDIANESS-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002817          	auipc	a6,0x2
+  84:	f8480813          	addi	a6,a6,-124 # 2004 <test_A_data>
+  88:	00002897          	auipc	a7,0x2
+  8c:	f8888893          	addi	a7,a7,-120 # 2010 <begin_signature>
+  90:	00082083          	lw	ra,0(a6)
+  94:	00085103          	lhu	sp,0(a6)
+  98:	00285183          	lhu	gp,2(a6)
+  9c:	fff84203          	lbu	tp,-1(a6)
+  a0:	00084283          	lbu	t0,0(a6)
+  a4:	00184303          	lbu	t1,1(a6)
+  a8:	00284383          	lbu	t2,2(a6)
+  ac:	00384403          	lbu	s0,3(a6)
+  b0:	0018a023          	sw	ra,0(a7)
+  b4:	0028a223          	sw	sp,4(a7)
+  b8:	0038a423          	sw	gp,8(a7)
+  bc:	0048a623          	sw	tp,12(a7)
+  c0:	0058a823          	sw	t0,16(a7)
+  c4:	0068aa23          	sw	t1,20(a7)
+  c8:	0078ac23          	sw	t2,24(a7)
+  cc:	0088ae23          	sw	s0,28(a7)
+  d0:	00002297          	auipc	t0,0x2
+  d4:	f4028293          	addi	t0,t0,-192 # 2010 <begin_signature>
+  d8:	10000337          	lui	t1,0x10000
+  dc:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+  e0:	00532023          	sw	t0,0(t1)
+  e4:	00002297          	auipc	t0,0x2
+  e8:	f4c28293          	addi	t0,t0,-180 # 2030 <end_signature>
+  ec:	10000337          	lui	t1,0x10000
+  f0:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+  f4:	00532023          	sw	t0,0(t1)
+  f8:	00100293          	li	t0,1
+  fc:	10000337          	lui	t1,0x10000
+ 100:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 104:	00532023          	sw	t0,0(t1)
+ 108:	00000013          	nop
+ 10c:	00100193          	li	gp,1
+ 110:	00000073          	ecall
+
+00000114 <end_testcode>:
+ 114:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_A_data-0x4>:
+    2000:	89abcdef          	jal	s11,fffbe09a <_end+0xfffbbe96>
+
+00002004 <test_A_data>:
+    2004:	01234567          	0x1234567
+	...
+
+00002010 <begin_signature>:
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+
+00002030 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf
new file mode 100644
index 0000000..1e83698
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.bin
new file mode 100644
index 0000000..645a886
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.objdump
new file mode 100644
index 0000000..0215076
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf.objdump
@@ -0,0 +1,401 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-IO-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002097          	auipc	ra,0x2
+  84:	f8008093          	addi	ra,ra,-128 # 2000 <test_A1_data>
+  88:	00002117          	auipc	sp,0x2
+  8c:	fa810113          	addi	sp,sp,-88 # 2030 <begin_signature>
+  90:	0000a183          	lw	gp,0(ra)
+  94:	00000213          	li	tp,0
+  98:	00100293          	li	t0,1
+  9c:	fff00313          	li	t1,-1
+  a0:	800003b7          	lui	t2,0x80000
+  a4:	fff38393          	addi	t2,t2,-1 # 7fffffff <_end+0x7fffddfb>
+  a8:	80000437          	lui	s0,0x80000
+  ac:	00418233          	add	tp,gp,tp
+  b0:	005182b3          	add	t0,gp,t0
+  b4:	00618333          	add	t1,gp,t1
+  b8:	007183b3          	add	t2,gp,t2
+  bc:	00818433          	add	s0,gp,s0
+  c0:	00312023          	sw	gp,0(sp)
+  c4:	00412223          	sw	tp,4(sp)
+  c8:	00512423          	sw	t0,8(sp)
+  cc:	00612623          	sw	t1,12(sp)
+  d0:	00712823          	sw	t2,16(sp)
+  d4:	00812a23          	sw	s0,20(sp)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f2c08093          	addi	ra,ra,-212 # 2004 <test_A2_data>
+  e0:	00002117          	auipc	sp,0x2
+  e4:	f6810113          	addi	sp,sp,-152 # 2048 <test_A2_res>
+  e8:	0000a403          	lw	s0,0(ra)
+  ec:	00000493          	li	s1,0
+  f0:	00100513          	li	a0,1
+  f4:	fff00593          	li	a1,-1
+  f8:	80000637          	lui	a2,0x80000
+  fc:	fff60613          	addi	a2,a2,-1 # 7fffffff <_end+0x7fffddfb>
+ 100:	800006b7          	lui	a3,0x80000
+ 104:	009404b3          	add	s1,s0,s1
+ 108:	00a40533          	add	a0,s0,a0
+ 10c:	00b405b3          	add	a1,s0,a1
+ 110:	00c40633          	add	a2,s0,a2
+ 114:	00d406b3          	add	a3,s0,a3
+ 118:	00812023          	sw	s0,0(sp)
+ 11c:	00912223          	sw	s1,4(sp)
+ 120:	00a12423          	sw	a0,8(sp)
+ 124:	00b12623          	sw	a1,12(sp)
+ 128:	00c12823          	sw	a2,16(sp)
+ 12c:	00d12a23          	sw	a3,20(sp)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	ed808093          	addi	ra,ra,-296 # 2008 <test_A3_data>
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	f2810113          	addi	sp,sp,-216 # 2060 <test_A3_res>
+ 140:	0000a683          	lw	a3,0(ra)
+ 144:	00000713          	li	a4,0
+ 148:	00100793          	li	a5,1
+ 14c:	fff00813          	li	a6,-1
+ 150:	800008b7          	lui	a7,0x80000
+ 154:	fff88893          	addi	a7,a7,-1 # 7fffffff <_end+0x7fffddfb>
+ 158:	80000937          	lui	s2,0x80000
+ 15c:	00e68733          	add	a4,a3,a4
+ 160:	00f687b3          	add	a5,a3,a5
+ 164:	01068833          	add	a6,a3,a6
+ 168:	011688b3          	add	a7,a3,a7
+ 16c:	01268933          	add	s2,a3,s2
+ 170:	00d12023          	sw	a3,0(sp)
+ 174:	00e12223          	sw	a4,4(sp)
+ 178:	00f12423          	sw	a5,8(sp)
+ 17c:	01012623          	sw	a6,12(sp)
+ 180:	01112823          	sw	a7,16(sp)
+ 184:	01212a23          	sw	s2,20(sp)
+ 188:	00002097          	auipc	ra,0x2
+ 18c:	e8408093          	addi	ra,ra,-380 # 200c <test_A4_data>
+ 190:	00002117          	auipc	sp,0x2
+ 194:	ee810113          	addi	sp,sp,-280 # 2078 <test_A4_res>
+ 198:	0000a903          	lw	s2,0(ra)
+ 19c:	00000993          	li	s3,0
+ 1a0:	00100a13          	li	s4,1
+ 1a4:	fff00a93          	li	s5,-1
+ 1a8:	80000b37          	lui	s6,0x80000
+ 1ac:	fffb0b13          	addi	s6,s6,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b0:	80000bb7          	lui	s7,0x80000
+ 1b4:	013909b3          	add	s3,s2,s3
+ 1b8:	01490a33          	add	s4,s2,s4
+ 1bc:	01590ab3          	add	s5,s2,s5
+ 1c0:	01690b33          	add	s6,s2,s6
+ 1c4:	01790bb3          	add	s7,s2,s7
+ 1c8:	01212023          	sw	s2,0(sp)
+ 1cc:	01312223          	sw	s3,4(sp)
+ 1d0:	01412423          	sw	s4,8(sp)
+ 1d4:	01512623          	sw	s5,12(sp)
+ 1d8:	01612823          	sw	s6,16(sp)
+ 1dc:	01712a23          	sw	s7,20(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	e3008093          	addi	ra,ra,-464 # 2010 <test_A5_data>
+ 1e8:	00002117          	auipc	sp,0x2
+ 1ec:	ea810113          	addi	sp,sp,-344 # 2090 <test_A5_res>
+ 1f0:	0000ab83          	lw	s7,0(ra)
+ 1f4:	00000c13          	li	s8,0
+ 1f8:	00100c93          	li	s9,1
+ 1fc:	fff00d13          	li	s10,-1
+ 200:	80000db7          	lui	s11,0x80000
+ 204:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 208:	80000e37          	lui	t3,0x80000
+ 20c:	018b8c33          	add	s8,s7,s8
+ 210:	019b8cb3          	add	s9,s7,s9
+ 214:	01ab8d33          	add	s10,s7,s10
+ 218:	01bb8db3          	add	s11,s7,s11
+ 21c:	01cb8e33          	add	t3,s7,t3
+ 220:	01712023          	sw	s7,0(sp)
+ 224:	01812223          	sw	s8,4(sp)
+ 228:	01912423          	sw	s9,8(sp)
+ 22c:	01a12623          	sw	s10,12(sp)
+ 230:	01b12823          	sw	s11,16(sp)
+ 234:	01c12a23          	sw	t3,20(sp)
+ 238:	00002c97          	auipc	s9,0x2
+ 23c:	ddcc8c93          	addi	s9,s9,-548 # 2014 <test_B_data>
+ 240:	00002d17          	auipc	s10,0x2
+ 244:	e68d0d13          	addi	s10,s10,-408 # 20a8 <test_B_res>
+ 248:	000cae03          	lw	t3,0(s9)
+ 24c:	00100d93          	li	s11,1
+ 250:	01be0eb3          	add	t4,t3,s11
+ 254:	01be8f33          	add	t5,t4,s11
+ 258:	01bf0fb3          	add	t6,t5,s11
+ 25c:	01bf80b3          	add	ra,t6,s11
+ 260:	01b08133          	add	sp,ra,s11
+ 264:	01b101b3          	add	gp,sp,s11
+ 268:	01bd2023          	sw	s11,0(s10)
+ 26c:	01cd2223          	sw	t3,4(s10)
+ 270:	01dd2423          	sw	t4,8(s10)
+ 274:	01ed2623          	sw	t5,12(s10)
+ 278:	01fd2823          	sw	t6,16(s10)
+ 27c:	001d2a23          	sw	ra,20(s10)
+ 280:	002d2c23          	sw	sp,24(s10)
+ 284:	003d2e23          	sw	gp,28(s10)
+ 288:	00002097          	auipc	ra,0x2
+ 28c:	d9008093          	addi	ra,ra,-624 # 2018 <test_C_data>
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e3810113          	addi	sp,sp,-456 # 20c8 <test_C_res>
+ 298:	0000ae03          	lw	t3,0(ra)
+ 29c:	f7ff9db7          	lui	s11,0xf7ff9
+ 2a0:	818d8d93          	addi	s11,s11,-2024 # f7ff8818 <_end+0xf7ff6614>
+ 2a4:	01be0033          	add	zero,t3,s11
+ 2a8:	00012023          	sw	zero,0(sp)
+ 2ac:	00002097          	auipc	ra,0x2
+ 2b0:	d7008093          	addi	ra,ra,-656 # 201c <test_D_data>
+ 2b4:	00002117          	auipc	sp,0x2
+ 2b8:	e1810113          	addi	sp,sp,-488 # 20cc <test_D_res>
+ 2bc:	0000ae03          	lw	t3,0(ra)
+ 2c0:	f7ff9db7          	lui	s11,0xf7ff9
+ 2c4:	818d8d93          	addi	s11,s11,-2024 # f7ff8818 <_end+0xf7ff6614>
+ 2c8:	01be0033          	add	zero,t3,s11
+ 2cc:	000002b3          	add	t0,zero,zero
+ 2d0:	00012023          	sw	zero,0(sp)
+ 2d4:	00512223          	sw	t0,4(sp)
+ 2d8:	00002097          	auipc	ra,0x2
+ 2dc:	d4808093          	addi	ra,ra,-696 # 2020 <test_E_data>
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	df410113          	addi	sp,sp,-524 # 20d4 <test_E_res>
+ 2e8:	0000a183          	lw	gp,0(ra)
+ 2ec:	00018233          	add	tp,gp,zero
+ 2f0:	000202b3          	add	t0,tp,zero
+ 2f4:	00500333          	add	t1,zero,t0
+ 2f8:	00030733          	add	a4,t1,zero
+ 2fc:	000707b3          	add	a5,a4,zero
+ 300:	00078833          	add	a6,a5,zero
+ 304:	01000cb3          	add	s9,zero,a6
+ 308:	01900d33          	add	s10,zero,s9
+ 30c:	000d0db3          	add	s11,s10,zero
+ 310:	00412023          	sw	tp,0(sp)
+ 314:	01a12223          	sw	s10,4(sp)
+ 318:	01b12423          	sw	s11,8(sp)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d1428293          	addi	t0,t0,-748 # 2030 <begin_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00002297          	auipc	t0,0x2
+ 334:	db028293          	addi	t0,t0,-592 # 20e0 <end_signature>
+ 338:	10000337          	lui	t1,0x10000
+ 33c:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 340:	00532023          	sw	t0,0(t1)
+ 344:	00100293          	li	t0,1
+ 348:	10000337          	lui	t1,0x10000
+ 34c:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 350:	00532023          	sw	t0,0(t1)
+ 354:	00000013          	nop
+ 358:	00100193          	li	gp,1
+ 35c:	00000073          	ecall
+
+00000360 <end_testcode>:
+ 360:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_A1_data>:
+    2000:	0000                	unimp
+	...
+
+00002004 <test_A2_data>:
+    2004:	0001                	nop
+	...
+
+00002008 <test_A3_data>:
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+
+0000200c <test_A4_data>:
+    200c:	ffff                	0xffff
+    200e:	7fff                	0x7fff
+
+00002010 <test_A5_data>:
+    2010:	0000                	unimp
+    2012:	8000                	0x8000
+
+00002014 <test_B_data>:
+    2014:	abcd                	j	2606 <_end+0x402>
+	...
+
+00002018 <test_C_data>:
+    2018:	5678                	lw	a4,108(a2)
+    201a:	1234                	addi	a3,sp,296
+
+0000201c <test_D_data>:
+    201c:	ba98                	fsd	fa4,48(a3)
+    201e:	fedc                	fsw	fa5,60(a3)
+
+00002020 <test_E_data>:
+    2020:	5814                	lw	a3,48(s0)
+    2022:	3692                	fld	fa3,288(sp)
+	...
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+
+00002048 <test_A2_res>:
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+
+00002060 <test_A3_res>:
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_A4_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+
+00002090 <test_A5_res>:
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_B_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+
+000020c8 <test_C_res>:
+    20c8:	ffff                	0xffff
+    20ca:	ffff                	0xffff
+
+000020cc <test_D_res>:
+    20cc:	ffff                	0xffff
+    20ce:	ffff                	0xffff
+    20d0:	ffff                	0xffff
+    20d2:	ffff                	0xffff
+
+000020d4 <test_E_res>:
+    20d4:	ffff                	0xffff
+    20d6:	ffff                	0xffff
+    20d8:	ffff                	0xffff
+    20da:	ffff                	0xffff
+    20dc:	ffff                	0xffff
+    20de:	ffff                	0xffff
+
+000020e0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf
new file mode 100644
index 0000000..88e89c2
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.bin
new file mode 100644
index 0000000..a239275
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.objdump
new file mode 100644
index 0000000..c3d3fdf
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf.objdump
@@ -0,0 +1,395 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-JAL-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	0000d037          	lui	zero,0xd
+  8c:	ccc00013          	li	zero,-820
+  90:	00c00fef          	jal	t6,9c <begin_testcode+0x1c>
+  94:	00012037          	lui	zero,0x12
+  98:	3ab00013          	li	zero,939
+  9c:	0002a023          	sw	zero,0(t0)
+  a0:	0000d0b7          	lui	ra,0xd
+  a4:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+  a8:	00c00f6f          	jal	t5,b4 <begin_testcode+0x34>
+  ac:	000120b7          	lui	ra,0x12
+  b0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+  b4:	0012a223          	sw	ra,4(t0)
+  b8:	0080006f          	j	c0 <begin_testcode+0x40>
+  bc:	0180006f          	j	d4 <begin_testcode+0x54>
+  c0:	0000d137          	lui	sp,0xd
+  c4:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+  c8:	ff5ffeef          	jal	t4,bc <begin_testcode+0x3c>
+  cc:	00012137          	lui	sp,0x12
+  d0:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+  d4:	0022a423          	sw	sp,8(t0)
+  d8:	0000d1b7          	lui	gp,0xd
+  dc:	ccc18193          	addi	gp,gp,-820 # cccc <_end+0xaac8>
+  e0:	00c00e6f          	jal	t3,ec <begin_testcode+0x6c>
+  e4:	000121b7          	lui	gp,0x12
+  e8:	3ab18193          	addi	gp,gp,939 # 123ab <_end+0x101a7>
+  ec:	0032a623          	sw	gp,12(t0)
+  f0:	0000d237          	lui	tp,0xd
+  f4:	ccc20213          	addi	tp,tp,-820 # cccc <_end+0xaac8>
+  f8:	00c00def          	jal	s11,104 <begin_testcode+0x84>
+  fc:	00012237          	lui	tp,0x12
+ 100:	3ab20213          	addi	tp,tp,939 # 123ab <_end+0x101a7>
+ 104:	0042a823          	sw	tp,16(t0)
+ 108:	00002097          	auipc	ra,0x2
+ 10c:	f0c08093          	addi	ra,ra,-244 # 2014 <test_2_res>
+ 110:	0000d2b7          	lui	t0,0xd
+ 114:	ccc28293          	addi	t0,t0,-820 # cccc <_end+0xaac8>
+ 118:	00c00d6f          	jal	s10,124 <begin_testcode+0xa4>
+ 11c:	000122b7          	lui	t0,0x12
+ 120:	3ab28293          	addi	t0,t0,939 # 123ab <_end+0x101a7>
+ 124:	0050a023          	sw	t0,0(ra)
+ 128:	0000d337          	lui	t1,0xd
+ 12c:	ccc30313          	addi	t1,t1,-820 # cccc <_end+0xaac8>
+ 130:	00c00cef          	jal	s9,13c <begin_testcode+0xbc>
+ 134:	00012337          	lui	t1,0x12
+ 138:	3ab30313          	addi	t1,t1,939 # 123ab <_end+0x101a7>
+ 13c:	0060a223          	sw	t1,4(ra)
+ 140:	0080006f          	j	148 <begin_testcode+0xc8>
+ 144:	0180006f          	j	15c <begin_testcode+0xdc>
+ 148:	0000d3b7          	lui	t2,0xd
+ 14c:	ccc38393          	addi	t2,t2,-820 # cccc <_end+0xaac8>
+ 150:	ff5ffc6f          	jal	s8,144 <begin_testcode+0xc4>
+ 154:	000123b7          	lui	t2,0x12
+ 158:	3ab38393          	addi	t2,t2,939 # 123ab <_end+0x101a7>
+ 15c:	0070a423          	sw	t2,8(ra)
+ 160:	0000d437          	lui	s0,0xd
+ 164:	ccc40413          	addi	s0,s0,-820 # cccc <_end+0xaac8>
+ 168:	00c00bef          	jal	s7,174 <begin_testcode+0xf4>
+ 16c:	00012437          	lui	s0,0x12
+ 170:	3ab40413          	addi	s0,s0,939 # 123ab <_end+0x101a7>
+ 174:	0080a623          	sw	s0,12(ra)
+ 178:	0000d4b7          	lui	s1,0xd
+ 17c:	ccc48493          	addi	s1,s1,-820 # cccc <_end+0xaac8>
+ 180:	00c00b6f          	jal	s6,18c <begin_testcode+0x10c>
+ 184:	000124b7          	lui	s1,0x12
+ 188:	3ab48493          	addi	s1,s1,939 # 123ab <_end+0x101a7>
+ 18c:	0090a823          	sw	s1,16(ra)
+ 190:	00002097          	auipc	ra,0x2
+ 194:	e9808093          	addi	ra,ra,-360 # 2028 <test_3_res>
+ 198:	0000d537          	lui	a0,0xd
+ 19c:	ccc50513          	addi	a0,a0,-820 # cccc <_end+0xaac8>
+ 1a0:	00c00aef          	jal	s5,1ac <begin_testcode+0x12c>
+ 1a4:	00012537          	lui	a0,0x12
+ 1a8:	3ab50513          	addi	a0,a0,939 # 123ab <_end+0x101a7>
+ 1ac:	00a0a023          	sw	a0,0(ra)
+ 1b0:	0000d5b7          	lui	a1,0xd
+ 1b4:	ccc58593          	addi	a1,a1,-820 # cccc <_end+0xaac8>
+ 1b8:	00c00a6f          	jal	s4,1c4 <begin_testcode+0x144>
+ 1bc:	000125b7          	lui	a1,0x12
+ 1c0:	3ab58593          	addi	a1,a1,939 # 123ab <_end+0x101a7>
+ 1c4:	00b0a223          	sw	a1,4(ra)
+ 1c8:	0080006f          	j	1d0 <begin_testcode+0x150>
+ 1cc:	0180006f          	j	1e4 <begin_testcode+0x164>
+ 1d0:	0000d637          	lui	a2,0xd
+ 1d4:	ccc60613          	addi	a2,a2,-820 # cccc <_end+0xaac8>
+ 1d8:	ff5ff9ef          	jal	s3,1cc <begin_testcode+0x14c>
+ 1dc:	00012637          	lui	a2,0x12
+ 1e0:	3ab60613          	addi	a2,a2,939 # 123ab <_end+0x101a7>
+ 1e4:	00c0a423          	sw	a2,8(ra)
+ 1e8:	0000d6b7          	lui	a3,0xd
+ 1ec:	ccc68693          	addi	a3,a3,-820 # cccc <_end+0xaac8>
+ 1f0:	00c0096f          	jal	s2,1fc <begin_testcode+0x17c>
+ 1f4:	000126b7          	lui	a3,0x12
+ 1f8:	3ab68693          	addi	a3,a3,939 # 123ab <_end+0x101a7>
+ 1fc:	00d0a623          	sw	a3,12(ra)
+ 200:	0000d737          	lui	a4,0xd
+ 204:	ccc70713          	addi	a4,a4,-820 # cccc <_end+0xaac8>
+ 208:	00c008ef          	jal	a7,214 <begin_testcode+0x194>
+ 20c:	00012737          	lui	a4,0x12
+ 210:	3ab70713          	addi	a4,a4,939 # 123ab <_end+0x101a7>
+ 214:	00e0a823          	sw	a4,16(ra)
+ 218:	00002117          	auipc	sp,0x2
+ 21c:	e2410113          	addi	sp,sp,-476 # 203c <test_4_res>
+ 220:	0000d7b7          	lui	a5,0xd
+ 224:	ccc78793          	addi	a5,a5,-820 # cccc <_end+0xaac8>
+ 228:	00c0086f          	jal	a6,234 <begin_testcode+0x1b4>
+ 22c:	000127b7          	lui	a5,0x12
+ 230:	3ab78793          	addi	a5,a5,939 # 123ab <_end+0x101a7>
+ 234:	00f12023          	sw	a5,0(sp)
+ 238:	0000d837          	lui	a6,0xd
+ 23c:	ccc80813          	addi	a6,a6,-820 # cccc <_end+0xaac8>
+ 240:	00c007ef          	jal	a5,24c <begin_testcode+0x1cc>
+ 244:	00012837          	lui	a6,0x12
+ 248:	3ab80813          	addi	a6,a6,939 # 123ab <_end+0x101a7>
+ 24c:	01012223          	sw	a6,4(sp)
+ 250:	0080006f          	j	258 <begin_testcode+0x1d8>
+ 254:	0180006f          	j	26c <begin_testcode+0x1ec>
+ 258:	0000d8b7          	lui	a7,0xd
+ 25c:	ccc88893          	addi	a7,a7,-820 # cccc <_end+0xaac8>
+ 260:	ff5ff76f          	jal	a4,254 <begin_testcode+0x1d4>
+ 264:	000128b7          	lui	a7,0x12
+ 268:	3ab88893          	addi	a7,a7,939 # 123ab <_end+0x101a7>
+ 26c:	01112423          	sw	a7,8(sp)
+ 270:	0000d937          	lui	s2,0xd
+ 274:	ccc90913          	addi	s2,s2,-820 # cccc <_end+0xaac8>
+ 278:	00c006ef          	jal	a3,284 <begin_testcode+0x204>
+ 27c:	00012937          	lui	s2,0x12
+ 280:	3ab90913          	addi	s2,s2,939 # 123ab <_end+0x101a7>
+ 284:	01212623          	sw	s2,12(sp)
+ 288:	0000d9b7          	lui	s3,0xd
+ 28c:	ccc98993          	addi	s3,s3,-820 # cccc <_end+0xaac8>
+ 290:	00c0066f          	jal	a2,29c <begin_testcode+0x21c>
+ 294:	000129b7          	lui	s3,0x12
+ 298:	3ab98993          	addi	s3,s3,939 # 123ab <_end+0x101a7>
+ 29c:	01312823          	sw	s3,16(sp)
+ 2a0:	00002097          	auipc	ra,0x2
+ 2a4:	db008093          	addi	ra,ra,-592 # 2050 <test_5_res>
+ 2a8:	0000da37          	lui	s4,0xd
+ 2ac:	ccca0a13          	addi	s4,s4,-820 # cccc <_end+0xaac8>
+ 2b0:	00c005ef          	jal	a1,2bc <begin_testcode+0x23c>
+ 2b4:	00012a37          	lui	s4,0x12
+ 2b8:	3aba0a13          	addi	s4,s4,939 # 123ab <_end+0x101a7>
+ 2bc:	0140a023          	sw	s4,0(ra)
+ 2c0:	0000dab7          	lui	s5,0xd
+ 2c4:	ccca8a93          	addi	s5,s5,-820 # cccc <_end+0xaac8>
+ 2c8:	00c0056f          	jal	a0,2d4 <begin_testcode+0x254>
+ 2cc:	00012ab7          	lui	s5,0x12
+ 2d0:	3aba8a93          	addi	s5,s5,939 # 123ab <_end+0x101a7>
+ 2d4:	0150a223          	sw	s5,4(ra)
+ 2d8:	0080006f          	j	2e0 <begin_testcode+0x260>
+ 2dc:	0180006f          	j	2f4 <begin_testcode+0x274>
+ 2e0:	0000db37          	lui	s6,0xd
+ 2e4:	cccb0b13          	addi	s6,s6,-820 # cccc <_end+0xaac8>
+ 2e8:	ff5ff4ef          	jal	s1,2dc <begin_testcode+0x25c>
+ 2ec:	00012b37          	lui	s6,0x12
+ 2f0:	3abb0b13          	addi	s6,s6,939 # 123ab <_end+0x101a7>
+ 2f4:	0160a423          	sw	s6,8(ra)
+ 2f8:	0000dbb7          	lui	s7,0xd
+ 2fc:	cccb8b93          	addi	s7,s7,-820 # cccc <_end+0xaac8>
+ 300:	00c0046f          	jal	s0,30c <begin_testcode+0x28c>
+ 304:	00012bb7          	lui	s7,0x12
+ 308:	3abb8b93          	addi	s7,s7,939 # 123ab <_end+0x101a7>
+ 30c:	0170a623          	sw	s7,12(ra)
+ 310:	0000dc37          	lui	s8,0xd
+ 314:	cccc0c13          	addi	s8,s8,-820 # cccc <_end+0xaac8>
+ 318:	00c003ef          	jal	t2,324 <begin_testcode+0x2a4>
+ 31c:	00012c37          	lui	s8,0x12
+ 320:	3abc0c13          	addi	s8,s8,939 # 123ab <_end+0x101a7>
+ 324:	0180a823          	sw	s8,16(ra)
+ 328:	00002097          	auipc	ra,0x2
+ 32c:	d3c08093          	addi	ra,ra,-708 # 2064 <test_6_res>
+ 330:	0000dcb7          	lui	s9,0xd
+ 334:	cccc8c93          	addi	s9,s9,-820 # cccc <_end+0xaac8>
+ 338:	00c0036f          	jal	t1,344 <begin_testcode+0x2c4>
+ 33c:	00012cb7          	lui	s9,0x12
+ 340:	3abc8c93          	addi	s9,s9,939 # 123ab <_end+0x101a7>
+ 344:	0190a023          	sw	s9,0(ra)
+ 348:	0000dd37          	lui	s10,0xd
+ 34c:	cccd0d13          	addi	s10,s10,-820 # cccc <_end+0xaac8>
+ 350:	00c002ef          	jal	t0,35c <begin_testcode+0x2dc>
+ 354:	00012d37          	lui	s10,0x12
+ 358:	3abd0d13          	addi	s10,s10,939 # 123ab <_end+0x101a7>
+ 35c:	01a0a223          	sw	s10,4(ra)
+ 360:	0080006f          	j	368 <begin_testcode+0x2e8>
+ 364:	0180006f          	j	37c <begin_testcode+0x2fc>
+ 368:	0000ddb7          	lui	s11,0xd
+ 36c:	cccd8d93          	addi	s11,s11,-820 # cccc <_end+0xaac8>
+ 370:	ff5ff26f          	jal	tp,364 <begin_testcode+0x2e4>
+ 374:	00012db7          	lui	s11,0x12
+ 378:	3abd8d93          	addi	s11,s11,939 # 123ab <_end+0x101a7>
+ 37c:	01b0a423          	sw	s11,8(ra)
+ 380:	0000de37          	lui	t3,0xd
+ 384:	ccce0e13          	addi	t3,t3,-820 # cccc <_end+0xaac8>
+ 388:	00c001ef          	jal	gp,394 <begin_testcode+0x314>
+ 38c:	00012e37          	lui	t3,0x12
+ 390:	3abe0e13          	addi	t3,t3,939 # 123ab <_end+0x101a7>
+ 394:	01c0a623          	sw	t3,12(ra)
+ 398:	0000deb7          	lui	t4,0xd
+ 39c:	ccce8e93          	addi	t4,t4,-820 # cccc <_end+0xaac8>
+ 3a0:	00c0016f          	jal	sp,3ac <begin_testcode+0x32c>
+ 3a4:	00012eb7          	lui	t4,0x12
+ 3a8:	3abe8e93          	addi	t4,t4,939 # 123ab <_end+0x101a7>
+ 3ac:	01d0a823          	sw	t4,16(ra)
+ 3b0:	00002117          	auipc	sp,0x2
+ 3b4:	cc810113          	addi	sp,sp,-824 # 2078 <test_7_res>
+ 3b8:	0000df37          	lui	t5,0xd
+ 3bc:	cccf0f13          	addi	t5,t5,-820 # cccc <_end+0xaac8>
+ 3c0:	00c000ef          	jal	ra,3cc <begin_testcode+0x34c>
+ 3c4:	00012f37          	lui	t5,0x12
+ 3c8:	3abf0f13          	addi	t5,t5,939 # 123ab <_end+0x101a7>
+ 3cc:	01e12023          	sw	t5,0(sp)
+ 3d0:	0000dfb7          	lui	t6,0xd
+ 3d4:	cccf8f93          	addi	t6,t6,-820 # cccc <_end+0xaac8>
+ 3d8:	00c0006f          	j	3e4 <begin_testcode+0x364>
+ 3dc:	00012fb7          	lui	t6,0x12
+ 3e0:	3abf8f93          	addi	t6,t6,939 # 123ab <_end+0x101a7>
+ 3e4:	01f12223          	sw	t6,4(sp)
+ 3e8:	00002297          	auipc	t0,0x2
+ 3ec:	c1828293          	addi	t0,t0,-1000 # 2000 <begin_signature>
+ 3f0:	10000337          	lui	t1,0x10000
+ 3f4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 3f8:	00532023          	sw	t0,0(t1)
+ 3fc:	00002297          	auipc	t0,0x2
+ 400:	c9428293          	addi	t0,t0,-876 # 2090 <end_signature>
+ 404:	10000337          	lui	t1,0x10000
+ 408:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 40c:	00532023          	sw	t0,0(t1)
+ 410:	00100293          	li	t0,1
+ 414:	10000337          	lui	t1,0x10000
+ 418:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 41c:	00532023          	sw	t0,0(t1)
+ 420:	00000013          	nop
+ 424:	00100193          	li	gp,1
+ 428:	00000073          	ecall
+
+0000042c <end_testcode>:
+ 42c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf
new file mode 100644
index 0000000..136b657
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.bin
new file mode 100644
index 0000000..ce79725
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.objdump
new file mode 100644
index 0000000..c31feb5
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf.objdump
@@ -0,0 +1,459 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-JALR-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	0000dfb7          	lui	t6,0xd
+  8c:	cccf8f93          	addi	t6,t6,-820 # cccc <_end+0xaac8>
+  90:	00000817          	auipc	a6,0x0
+  94:	01480813          	addi	a6,a6,20 # a4 <begin_testcode+0x24>
+  98:	00080067          	jr	a6
+  9c:	00012fb7          	lui	t6,0x12
+  a0:	3abf8f93          	addi	t6,t6,939 # 123ab <_end+0x101a7>
+  a4:	01f2a023          	sw	t6,0(t0)
+  a8:	0000df37          	lui	t5,0xd
+  ac:	cccf0f13          	addi	t5,t5,-820 # cccc <_end+0xaac8>
+  b0:	00000797          	auipc	a5,0x0
+  b4:	01378793          	addi	a5,a5,19 # c3 <begin_testcode+0x43>
+  b8:	001780e7          	jalr	1(a5)
+  bc:	00012f37          	lui	t5,0x12
+  c0:	3abf0f13          	addi	t5,t5,939 # 123ab <_end+0x101a7>
+  c4:	01e2a223          	sw	t5,4(t0)
+  c8:	0080006f          	j	d0 <begin_testcode+0x50>
+  cc:	0200006f          	j	ec <begin_testcode+0x6c>
+  d0:	0000deb7          	lui	t4,0xd
+  d4:	ccce8e93          	addi	t4,t4,-820 # cccc <_end+0xaac8>
+  d8:	00000717          	auipc	a4,0x0
+  dc:	ff370713          	addi	a4,a4,-13 # cb <begin_testcode+0x4b>
+  e0:	00170167          	jalr	sp,1(a4)
+  e4:	00012eb7          	lui	t4,0x12
+  e8:	3abe8e93          	addi	t4,t4,939 # 123ab <_end+0x101a7>
+  ec:	01d2a423          	sw	t4,8(t0)
+  f0:	0000de37          	lui	t3,0xd
+  f4:	ccce0e13          	addi	t3,t3,-820 # cccc <_end+0xaac8>
+  f8:	00000697          	auipc	a3,0x0
+  fc:	01068693          	addi	a3,a3,16 # 108 <begin_testcode+0x88>
+ 100:	004681e7          	jalr	gp,4(a3)
+ 104:	00012e37          	lui	t3,0x12
+ 108:	3abe0e13          	addi	t3,t3,939 # 123ab <_end+0x101a7>
+ 10c:	01c2a623          	sw	t3,12(t0)
+ 110:	0000ddb7          	lui	s11,0xd
+ 114:	cccd8d93          	addi	s11,s11,-820 # cccc <_end+0xaac8>
+ 118:	00000617          	auipc	a2,0x0
+ 11c:	01260613          	addi	a2,a2,18 # 12a <begin_testcode+0xaa>
+ 120:	00260267          	jalr	tp,2(a2)
+ 124:	00012db7          	lui	s11,0x12
+ 128:	3abd8d93          	addi	s11,s11,939 # 123ab <_end+0x101a7>
+ 12c:	01b2a823          	sw	s11,16(t0)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	ee408093          	addi	ra,ra,-284 # 2014 <test_2_res>
+ 138:	0000dd37          	lui	s10,0xd
+ 13c:	cccd0d13          	addi	s10,s10,-820 # cccc <_end+0xaac8>
+ 140:	00000597          	auipc	a1,0x0
+ 144:	01058593          	addi	a1,a1,16 # 150 <begin_testcode+0xd0>
+ 148:	004582e7          	jalr	t0,4(a1)
+ 14c:	00012d37          	lui	s10,0x12
+ 150:	3abd0d13          	addi	s10,s10,939 # 123ab <_end+0x101a7>
+ 154:	01a0a023          	sw	s10,0(ra)
+ 158:	0000dcb7          	lui	s9,0xd
+ 15c:	cccc8c93          	addi	s9,s9,-820 # cccc <_end+0xaac8>
+ 160:	00000517          	auipc	a0,0x0
+ 164:	01150513          	addi	a0,a0,17 # 171 <begin_testcode+0xf1>
+ 168:	00350367          	jalr	t1,3(a0)
+ 16c:	00012cb7          	lui	s9,0x12
+ 170:	3abc8c93          	addi	s9,s9,939 # 123ab <_end+0x101a7>
+ 174:	0190a223          	sw	s9,4(ra)
+ 178:	0080006f          	j	180 <begin_testcode+0x100>
+ 17c:	0200006f          	j	19c <begin_testcode+0x11c>
+ 180:	0000dc37          	lui	s8,0xd
+ 184:	cccc0c13          	addi	s8,s8,-820 # cccc <_end+0xaac8>
+ 188:	00000497          	auipc	s1,0x0
+ 18c:	ff248493          	addi	s1,s1,-14 # 17a <begin_testcode+0xfa>
+ 190:	002483e7          	jalr	t2,2(s1)
+ 194:	00012c37          	lui	s8,0x12
+ 198:	3abc0c13          	addi	s8,s8,939 # 123ab <_end+0x101a7>
+ 19c:	0180a423          	sw	s8,8(ra)
+ 1a0:	0000dbb7          	lui	s7,0xd
+ 1a4:	cccb8b93          	addi	s7,s7,-820 # cccc <_end+0xaac8>
+ 1a8:	00000417          	auipc	s0,0x0
+ 1ac:	01440413          	addi	s0,s0,20 # 1bc <begin_testcode+0x13c>
+ 1b0:	00040467          	jalr	s0,s0
+ 1b4:	00012bb7          	lui	s7,0x12
+ 1b8:	3abb8b93          	addi	s7,s7,939 # 123ab <_end+0x101a7>
+ 1bc:	0170a623          	sw	s7,12(ra)
+ 1c0:	0000db37          	lui	s6,0xd
+ 1c4:	cccb0b13          	addi	s6,s6,-820 # cccc <_end+0xaac8>
+ 1c8:	00000397          	auipc	t2,0x0
+ 1cc:	01338393          	addi	t2,t2,19 # 1db <begin_testcode+0x15b>
+ 1d0:	001384e7          	jalr	s1,1(t2)
+ 1d4:	00012b37          	lui	s6,0x12
+ 1d8:	3abb0b13          	addi	s6,s6,939 # 123ab <_end+0x101a7>
+ 1dc:	0160a823          	sw	s6,16(ra)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	e4808093          	addi	ra,ra,-440 # 2028 <test_3_res>
+ 1e8:	0000dab7          	lui	s5,0xd
+ 1ec:	ccca8a93          	addi	s5,s5,-820 # cccc <_end+0xaac8>
+ 1f0:	00000317          	auipc	t1,0x0
+ 1f4:	01330313          	addi	t1,t1,19 # 203 <begin_testcode+0x183>
+ 1f8:	00130567          	jalr	a0,1(t1)
+ 1fc:	00012ab7          	lui	s5,0x12
+ 200:	3aba8a93          	addi	s5,s5,939 # 123ab <_end+0x101a7>
+ 204:	0150a023          	sw	s5,0(ra)
+ 208:	0000da37          	lui	s4,0xd
+ 20c:	ccca0a13          	addi	s4,s4,-820 # cccc <_end+0xaac8>
+ 210:	00000297          	auipc	t0,0x0
+ 214:	01028293          	addi	t0,t0,16 # 220 <begin_testcode+0x1a0>
+ 218:	004285e7          	jalr	a1,4(t0)
+ 21c:	00012a37          	lui	s4,0x12
+ 220:	3aba0a13          	addi	s4,s4,939 # 123ab <_end+0x101a7>
+ 224:	0140a223          	sw	s4,4(ra)
+ 228:	0080006f          	j	230 <begin_testcode+0x1b0>
+ 22c:	0200006f          	j	24c <begin_testcode+0x1cc>
+ 230:	0000d9b7          	lui	s3,0xd
+ 234:	ccc98993          	addi	s3,s3,-820 # cccc <_end+0xaac8>
+ 238:	00000217          	auipc	tp,0x0
+ 23c:	ff220213          	addi	tp,tp,-14 # 22a <begin_testcode+0x1aa>
+ 240:	00220667          	jalr	a2,2(tp) # 0 <_start>
+ 244:	000129b7          	lui	s3,0x12
+ 248:	3ab98993          	addi	s3,s3,939 # 123ab <_end+0x101a7>
+ 24c:	0130a423          	sw	s3,8(ra)
+ 250:	0000d937          	lui	s2,0xd
+ 254:	ccc90913          	addi	s2,s2,-820 # cccc <_end+0xaac8>
+ 258:	00000197          	auipc	gp,0x0
+ 25c:	01018193          	addi	gp,gp,16 # 268 <begin_testcode+0x1e8>
+ 260:	004186e7          	jalr	a3,4(gp)
+ 264:	00012937          	lui	s2,0x12
+ 268:	3ab90913          	addi	s2,s2,939 # 123ab <_end+0x101a7>
+ 26c:	0120a623          	sw	s2,12(ra)
+ 270:	0000d8b7          	lui	a7,0xd
+ 274:	ccc88893          	addi	a7,a7,-820 # cccc <_end+0xaac8>
+ 278:	00000117          	auipc	sp,0x0
+ 27c:	01110113          	addi	sp,sp,17 # 289 <begin_testcode+0x209>
+ 280:	00310767          	jalr	a4,3(sp)
+ 284:	000128b7          	lui	a7,0x12
+ 288:	3ab88893          	addi	a7,a7,939 # 123ab <_end+0x101a7>
+ 28c:	0110a823          	sw	a7,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	dac10113          	addi	sp,sp,-596 # 203c <test_4_res>
+ 298:	0000d837          	lui	a6,0xd
+ 29c:	ccc80813          	addi	a6,a6,-820 # cccc <_end+0xaac8>
+ 2a0:	00000097          	auipc	ra,0x0
+ 2a4:	01208093          	addi	ra,ra,18 # 2b2 <begin_testcode+0x232>
+ 2a8:	002087e7          	jalr	a5,2(ra)
+ 2ac:	00012837          	lui	a6,0x12
+ 2b0:	3ab80813          	addi	a6,a6,939 # 123ab <_end+0x101a7>
+ 2b4:	01012023          	sw	a6,0(sp)
+ 2b8:	0000d7b7          	lui	a5,0xd
+ 2bc:	ccc78793          	addi	a5,a5,-820 # cccc <_end+0xaac8>
+ 2c0:	00000097          	auipc	ra,0x0
+ 2c4:	01408093          	addi	ra,ra,20 # 2d4 <begin_testcode+0x254>
+ 2c8:	00008867          	jalr	a6,ra
+ 2cc:	000127b7          	lui	a5,0x12
+ 2d0:	3ab78793          	addi	a5,a5,939 # 123ab <_end+0x101a7>
+ 2d4:	00f12223          	sw	a5,4(sp)
+ 2d8:	0080006f          	j	2e0 <begin_testcode+0x260>
+ 2dc:	0200006f          	j	2fc <begin_testcode+0x27c>
+ 2e0:	0000d737          	lui	a4,0xd
+ 2e4:	ccc70713          	addi	a4,a4,-820 # cccc <_end+0xaac8>
+ 2e8:	00000f97          	auipc	t6,0x0
+ 2ec:	ff3f8f93          	addi	t6,t6,-13 # 2db <begin_testcode+0x25b>
+ 2f0:	001f88e7          	jalr	a7,1(t6)
+ 2f4:	00012737          	lui	a4,0x12
+ 2f8:	3ab70713          	addi	a4,a4,939 # 123ab <_end+0x101a7>
+ 2fc:	00e12423          	sw	a4,8(sp)
+ 300:	0000d6b7          	lui	a3,0xd
+ 304:	ccc68693          	addi	a3,a3,-820 # cccc <_end+0xaac8>
+ 308:	00000f17          	auipc	t5,0x0
+ 30c:	013f0f13          	addi	t5,t5,19 # 31b <begin_testcode+0x29b>
+ 310:	001f0967          	jalr	s2,1(t5)
+ 314:	000126b7          	lui	a3,0x12
+ 318:	3ab68693          	addi	a3,a3,939 # 123ab <_end+0x101a7>
+ 31c:	00d12623          	sw	a3,12(sp)
+ 320:	0000d637          	lui	a2,0xd
+ 324:	ccc60613          	addi	a2,a2,-820 # cccc <_end+0xaac8>
+ 328:	00000e97          	auipc	t4,0x0
+ 32c:	010e8e93          	addi	t4,t4,16 # 338 <begin_testcode+0x2b8>
+ 330:	004e89e7          	jalr	s3,4(t4)
+ 334:	00012637          	lui	a2,0x12
+ 338:	3ab60613          	addi	a2,a2,939 # 123ab <_end+0x101a7>
+ 33c:	00c12823          	sw	a2,16(sp)
+ 340:	00002097          	auipc	ra,0x2
+ 344:	d1008093          	addi	ra,ra,-752 # 2050 <test_5_res>
+ 348:	0000d5b7          	lui	a1,0xd
+ 34c:	ccc58593          	addi	a1,a1,-820 # cccc <_end+0xaac8>
+ 350:	00000e17          	auipc	t3,0x0
+ 354:	012e0e13          	addi	t3,t3,18 # 362 <begin_testcode+0x2e2>
+ 358:	002e0a67          	jalr	s4,2(t3)
+ 35c:	000125b7          	lui	a1,0x12
+ 360:	3ab58593          	addi	a1,a1,939 # 123ab <_end+0x101a7>
+ 364:	00b0a023          	sw	a1,0(ra)
+ 368:	0000d537          	lui	a0,0xd
+ 36c:	ccc50513          	addi	a0,a0,-820 # cccc <_end+0xaac8>
+ 370:	00000d97          	auipc	s11,0x0
+ 374:	010d8d93          	addi	s11,s11,16 # 380 <begin_testcode+0x300>
+ 378:	004d8ae7          	jalr	s5,4(s11)
+ 37c:	00012537          	lui	a0,0x12
+ 380:	3ab50513          	addi	a0,a0,939 # 123ab <_end+0x101a7>
+ 384:	00a0a223          	sw	a0,4(ra)
+ 388:	0080006f          	j	390 <begin_testcode+0x310>
+ 38c:	0200006f          	j	3ac <begin_testcode+0x32c>
+ 390:	0000d4b7          	lui	s1,0xd
+ 394:	ccc48493          	addi	s1,s1,-820 # cccc <_end+0xaac8>
+ 398:	00000d17          	auipc	s10,0x0
+ 39c:	ff1d0d13          	addi	s10,s10,-15 # 389 <begin_testcode+0x309>
+ 3a0:	003d0b67          	jalr	s6,3(s10)
+ 3a4:	000124b7          	lui	s1,0x12
+ 3a8:	3ab48493          	addi	s1,s1,939 # 123ab <_end+0x101a7>
+ 3ac:	0090a423          	sw	s1,8(ra)
+ 3b0:	0000d437          	lui	s0,0xd
+ 3b4:	ccc40413          	addi	s0,s0,-820 # cccc <_end+0xaac8>
+ 3b8:	00000c97          	auipc	s9,0x0
+ 3bc:	012c8c93          	addi	s9,s9,18 # 3ca <begin_testcode+0x34a>
+ 3c0:	002c8be7          	jalr	s7,2(s9)
+ 3c4:	00012437          	lui	s0,0x12
+ 3c8:	3ab40413          	addi	s0,s0,939 # 123ab <_end+0x101a7>
+ 3cc:	0080a623          	sw	s0,12(ra)
+ 3d0:	0000d3b7          	lui	t2,0xd
+ 3d4:	ccc38393          	addi	t2,t2,-820 # cccc <_end+0xaac8>
+ 3d8:	00000c17          	auipc	s8,0x0
+ 3dc:	014c0c13          	addi	s8,s8,20 # 3ec <begin_testcode+0x36c>
+ 3e0:	000c0c67          	jalr	s8,s8
+ 3e4:	000123b7          	lui	t2,0x12
+ 3e8:	3ab38393          	addi	t2,t2,939 # 123ab <_end+0x101a7>
+ 3ec:	0070a823          	sw	t2,16(ra)
+ 3f0:	00002097          	auipc	ra,0x2
+ 3f4:	c7408093          	addi	ra,ra,-908 # 2064 <test_6_res>
+ 3f8:	0000d337          	lui	t1,0xd
+ 3fc:	ccc30313          	addi	t1,t1,-820 # cccc <_end+0xaac8>
+ 400:	00000b97          	auipc	s7,0x0
+ 404:	013b8b93          	addi	s7,s7,19 # 413 <begin_testcode+0x393>
+ 408:	001b8ce7          	jalr	s9,1(s7)
+ 40c:	00012337          	lui	t1,0x12
+ 410:	3ab30313          	addi	t1,t1,939 # 123ab <_end+0x101a7>
+ 414:	0060a023          	sw	t1,0(ra)
+ 418:	0000d2b7          	lui	t0,0xd
+ 41c:	ccc28293          	addi	t0,t0,-820 # cccc <_end+0xaac8>
+ 420:	00000b17          	auipc	s6,0x0
+ 424:	013b0b13          	addi	s6,s6,19 # 433 <begin_testcode+0x3b3>
+ 428:	001b0d67          	jalr	s10,1(s6)
+ 42c:	000122b7          	lui	t0,0x12
+ 430:	3ab28293          	addi	t0,t0,939 # 123ab <_end+0x101a7>
+ 434:	0050a223          	sw	t0,4(ra)
+ 438:	0080006f          	j	440 <begin_testcode+0x3c0>
+ 43c:	0200006f          	j	45c <begin_testcode+0x3dc>
+ 440:	0000d237          	lui	tp,0xd
+ 444:	ccc20213          	addi	tp,tp,-820 # cccc <_end+0xaac8>
+ 448:	00000a97          	auipc	s5,0x0
+ 44c:	ff0a8a93          	addi	s5,s5,-16 # 438 <begin_testcode+0x3b8>
+ 450:	004a8de7          	jalr	s11,4(s5)
+ 454:	00012237          	lui	tp,0x12
+ 458:	3ab20213          	addi	tp,tp,939 # 123ab <_end+0x101a7>
+ 45c:	0040a423          	sw	tp,8(ra)
+ 460:	0000d1b7          	lui	gp,0xd
+ 464:	ccc18193          	addi	gp,gp,-820 # cccc <_end+0xaac8>
+ 468:	00000a17          	auipc	s4,0x0
+ 46c:	012a0a13          	addi	s4,s4,18 # 47a <begin_testcode+0x3fa>
+ 470:	002a0e67          	jalr	t3,2(s4)
+ 474:	000121b7          	lui	gp,0x12
+ 478:	3ab18193          	addi	gp,gp,939 # 123ab <_end+0x101a7>
+ 47c:	0030a623          	sw	gp,12(ra)
+ 480:	0000d137          	lui	sp,0xd
+ 484:	ccc10113          	addi	sp,sp,-820 # cccc <_end+0xaac8>
+ 488:	00000997          	auipc	s3,0x0
+ 48c:	01098993          	addi	s3,s3,16 # 498 <begin_testcode+0x418>
+ 490:	00498ee7          	jalr	t4,4(s3)
+ 494:	00012137          	lui	sp,0x12
+ 498:	3ab10113          	addi	sp,sp,939 # 123ab <_end+0x101a7>
+ 49c:	0020a823          	sw	sp,16(ra)
+ 4a0:	00002117          	auipc	sp,0x2
+ 4a4:	bd810113          	addi	sp,sp,-1064 # 2078 <test_7_res>
+ 4a8:	0000d0b7          	lui	ra,0xd
+ 4ac:	ccc08093          	addi	ra,ra,-820 # cccc <_end+0xaac8>
+ 4b0:	00000917          	auipc	s2,0x0
+ 4b4:	01190913          	addi	s2,s2,17 # 4c1 <begin_testcode+0x441>
+ 4b8:	00390f67          	jalr	t5,3(s2)
+ 4bc:	000120b7          	lui	ra,0x12
+ 4c0:	3ab08093          	addi	ra,ra,939 # 123ab <_end+0x101a7>
+ 4c4:	00112023          	sw	ra,0(sp)
+ 4c8:	0000d037          	lui	zero,0xd
+ 4cc:	ccc00013          	li	zero,-820
+ 4d0:	00000897          	auipc	a7,0x0
+ 4d4:	01288893          	addi	a7,a7,18 # 4e2 <begin_testcode+0x462>
+ 4d8:	00288fe7          	jalr	t6,2(a7)
+ 4dc:	00012037          	lui	zero,0x12
+ 4e0:	3ab00013          	li	zero,939
+ 4e4:	00012223          	sw	zero,4(sp)
+ 4e8:	00002297          	auipc	t0,0x2
+ 4ec:	b1828293          	addi	t0,t0,-1256 # 2000 <begin_signature>
+ 4f0:	10000337          	lui	t1,0x10000
+ 4f4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 4f8:	00532023          	sw	t0,0(t1)
+ 4fc:	00002297          	auipc	t0,0x2
+ 500:	b9428293          	addi	t0,t0,-1132 # 2090 <end_signature>
+ 504:	10000337          	lui	t1,0x10000
+ 508:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 50c:	00532023          	sw	t0,0(t1)
+ 510:	00100293          	li	t0,1
+ 514:	10000337          	lui	t1,0x10000
+ 518:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 51c:	00532023          	sw	t0,0(t1)
+ 520:	00000013          	nop
+ 524:	00100193          	li	gp,1
+ 528:	00000073          	ecall
+
+0000052c <end_testcode>:
+ 52c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf
new file mode 100644
index 0000000..2b922bc
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.bin
new file mode 100644
index 0000000..3885015
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.objdump
new file mode 100644
index 0000000..30e89e3
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf.objdump
@@ -0,0 +1,346 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LB-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	fb028293          	addi	t0,t0,-80 # 2030 <begin_signature>
+  88:	00002f97          	auipc	t6,0x2
+  8c:	f90f8f93          	addi	t6,t6,-112 # 2018 <test_data>
+  90:	000f8003          	lb	zero,0(t6)
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00002f17          	auipc	t5,0x2
+  9c:	f80f0f13          	addi	t5,t5,-128 # 2018 <test_data>
+  a0:	ffef0083          	lb	ra,-2(t5)
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00002e97          	auipc	t4,0x2
+  ac:	f70e8e93          	addi	t4,t4,-144 # 2018 <test_data>
+  b0:	003e8103          	lb	sp,3(t4)
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	00002e17          	auipc	t3,0x2
+  bc:	f60e0e13          	addi	t3,t3,-160 # 2018 <test_data>
+  c0:	ffce0183          	lb	gp,-4(t3)
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00002d97          	auipc	s11,0x2
+  cc:	f50d8d93          	addi	s11,s11,-176 # 2018 <test_data>
+  d0:	002d8203          	lb	tp,2(s11)
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f6c08093          	addi	ra,ra,-148 # 2044 <test_2_res>
+  e0:	00002d17          	auipc	s10,0x2
+  e4:	f38d0d13          	addi	s10,s10,-200 # 2018 <test_data>
+  e8:	004d0283          	lb	t0,4(s10)
+  ec:	0050a023          	sw	t0,0(ra)
+  f0:	00002c97          	auipc	s9,0x2
+  f4:	f28c8c93          	addi	s9,s9,-216 # 2018 <test_data>
+  f8:	fffc8303          	lb	t1,-1(s9)
+  fc:	0060a223          	sw	t1,4(ra)
+ 100:	00002c17          	auipc	s8,0x2
+ 104:	f18c0c13          	addi	s8,s8,-232 # 2018 <test_data>
+ 108:	001c0383          	lb	t2,1(s8)
+ 10c:	0070a423          	sw	t2,8(ra)
+ 110:	00002b97          	auipc	s7,0x2
+ 114:	f08b8b93          	addi	s7,s7,-248 # 2018 <test_data>
+ 118:	000b8403          	lb	s0,0(s7)
+ 11c:	0080a623          	sw	s0,12(ra)
+ 120:	00002b17          	auipc	s6,0x2
+ 124:	ef8b0b13          	addi	s6,s6,-264 # 2018 <test_data>
+ 128:	ffeb0483          	lb	s1,-2(s6)
+ 12c:	0090a823          	sw	s1,16(ra)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	f2808093          	addi	ra,ra,-216 # 2058 <test_3_res>
+ 138:	00002a97          	auipc	s5,0x2
+ 13c:	ee0a8a93          	addi	s5,s5,-288 # 2018 <test_data>
+ 140:	003a8503          	lb	a0,3(s5)
+ 144:	00a0a023          	sw	a0,0(ra)
+ 148:	00002a17          	auipc	s4,0x2
+ 14c:	ed0a0a13          	addi	s4,s4,-304 # 2018 <test_data>
+ 150:	ffca0583          	lb	a1,-4(s4)
+ 154:	00b0a223          	sw	a1,4(ra)
+ 158:	00002997          	auipc	s3,0x2
+ 15c:	ec098993          	addi	s3,s3,-320 # 2018 <test_data>
+ 160:	00298603          	lb	a2,2(s3)
+ 164:	00c0a423          	sw	a2,8(ra)
+ 168:	00002917          	auipc	s2,0x2
+ 16c:	eb090913          	addi	s2,s2,-336 # 2018 <test_data>
+ 170:	00490683          	lb	a3,4(s2)
+ 174:	00d0a623          	sw	a3,12(ra)
+ 178:	00002897          	auipc	a7,0x2
+ 17c:	ea088893          	addi	a7,a7,-352 # 2018 <test_data>
+ 180:	fff88703          	lb	a4,-1(a7)
+ 184:	00e0a823          	sw	a4,16(ra)
+ 188:	00002117          	auipc	sp,0x2
+ 18c:	ee410113          	addi	sp,sp,-284 # 206c <test_4_res>
+ 190:	00002817          	auipc	a6,0x2
+ 194:	e8880813          	addi	a6,a6,-376 # 2018 <test_data>
+ 198:	00180783          	lb	a5,1(a6)
+ 19c:	00f12023          	sw	a5,0(sp)
+ 1a0:	00002797          	auipc	a5,0x2
+ 1a4:	e7878793          	addi	a5,a5,-392 # 2018 <test_data>
+ 1a8:	00078803          	lb	a6,0(a5)
+ 1ac:	01012223          	sw	a6,4(sp)
+ 1b0:	00002717          	auipc	a4,0x2
+ 1b4:	e6870713          	addi	a4,a4,-408 # 2018 <test_data>
+ 1b8:	ffe70883          	lb	a7,-2(a4)
+ 1bc:	01112423          	sw	a7,8(sp)
+ 1c0:	00002697          	auipc	a3,0x2
+ 1c4:	e5868693          	addi	a3,a3,-424 # 2018 <test_data>
+ 1c8:	00368903          	lb	s2,3(a3)
+ 1cc:	01212623          	sw	s2,12(sp)
+ 1d0:	00002617          	auipc	a2,0x2
+ 1d4:	e4860613          	addi	a2,a2,-440 # 2018 <test_data>
+ 1d8:	ffc60983          	lb	s3,-4(a2)
+ 1dc:	01312823          	sw	s3,16(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	ea008093          	addi	ra,ra,-352 # 2080 <test_5_res>
+ 1e8:	00002597          	auipc	a1,0x2
+ 1ec:	e3058593          	addi	a1,a1,-464 # 2018 <test_data>
+ 1f0:	00258a03          	lb	s4,2(a1)
+ 1f4:	0140a023          	sw	s4,0(ra)
+ 1f8:	00002517          	auipc	a0,0x2
+ 1fc:	e2050513          	addi	a0,a0,-480 # 2018 <test_data>
+ 200:	00450a83          	lb	s5,4(a0)
+ 204:	0150a223          	sw	s5,4(ra)
+ 208:	00002497          	auipc	s1,0x2
+ 20c:	e1048493          	addi	s1,s1,-496 # 2018 <test_data>
+ 210:	fff48b03          	lb	s6,-1(s1)
+ 214:	0160a423          	sw	s6,8(ra)
+ 218:	00002417          	auipc	s0,0x2
+ 21c:	e0040413          	addi	s0,s0,-512 # 2018 <test_data>
+ 220:	00140b83          	lb	s7,1(s0)
+ 224:	0170a623          	sw	s7,12(ra)
+ 228:	00002397          	auipc	t2,0x2
+ 22c:	df038393          	addi	t2,t2,-528 # 2018 <test_data>
+ 230:	00038c03          	lb	s8,0(t2)
+ 234:	0180a823          	sw	s8,16(ra)
+ 238:	00002097          	auipc	ra,0x2
+ 23c:	e5c08093          	addi	ra,ra,-420 # 2094 <test_6_res>
+ 240:	00002317          	auipc	t1,0x2
+ 244:	dd830313          	addi	t1,t1,-552 # 2018 <test_data>
+ 248:	ffe30c83          	lb	s9,-2(t1)
+ 24c:	0190a023          	sw	s9,0(ra)
+ 250:	00002297          	auipc	t0,0x2
+ 254:	dc828293          	addi	t0,t0,-568 # 2018 <test_data>
+ 258:	00328d03          	lb	s10,3(t0)
+ 25c:	01a0a223          	sw	s10,4(ra)
+ 260:	00002217          	auipc	tp,0x2
+ 264:	db820213          	addi	tp,tp,-584 # 2018 <test_data>
+ 268:	ffc20d83          	lb	s11,-4(tp) # fffffffc <_end+0xffffddf8>
+ 26c:	01b0a423          	sw	s11,8(ra)
+ 270:	00002197          	auipc	gp,0x2
+ 274:	da818193          	addi	gp,gp,-600 # 2018 <test_data>
+ 278:	00218e03          	lb	t3,2(gp)
+ 27c:	01c0a623          	sw	t3,12(ra)
+ 280:	00002117          	auipc	sp,0x2
+ 284:	d9810113          	addi	sp,sp,-616 # 2018 <test_data>
+ 288:	00410e83          	lb	t4,4(sp)
+ 28c:	01d0a823          	sw	t4,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e1810113          	addi	sp,sp,-488 # 20a8 <test_7_res>
+ 298:	00002097          	auipc	ra,0x2
+ 29c:	d8008093          	addi	ra,ra,-640 # 2018 <test_data>
+ 2a0:	fff08f03          	lb	t5,-1(ra)
+ 2a4:	01e12023          	sw	t5,0(sp)
+ 2a8:	00002097          	auipc	ra,0x2
+ 2ac:	d7008093          	addi	ra,ra,-656 # 2018 <test_data>
+ 2b0:	00108f83          	lb	t6,1(ra)
+ 2b4:	01f12223          	sw	t6,4(sp)
+ 2b8:	00002297          	auipc	t0,0x2
+ 2bc:	d7828293          	addi	t0,t0,-648 # 2030 <begin_signature>
+ 2c0:	10000337          	lui	t1,0x10000
+ 2c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c8:	00532023          	sw	t0,0(t1)
+ 2cc:	00002297          	auipc	t0,0x2
+ 2d0:	df428293          	addi	t0,t0,-524 # 20c0 <end_signature>
+ 2d4:	10000337          	lui	t1,0x10000
+ 2d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2dc:	00532023          	sw	t0,0(t1)
+ 2e0:	00100293          	li	t0,1
+ 2e4:	10000337          	lui	t1,0x10000
+ 2e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2ec:	00532023          	sw	t0,0(t1)
+ 2f0:	00000013          	nop
+ 2f4:	00100193          	li	gp,1
+ 2f8:	00000073          	ecall
+
+000002fc <end_testcode>:
+ 2fc:	c0001073          	unimp
+ 300:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_data_start>:
+    2000:	f222                	fsw	fs0,36(sp)
+    2002:	11f1                	addi	gp,gp,-4
+    2004:	44f4                	lw	a3,76(s1)
+    2006:	f666f333          	0xf666f333
+    200a:	55f5                	li	a1,-3
+    200c:	88f8                	0x88f8
+    200e:	0aaaf777          	0xaaaf777
+    2012:	9909                	andi	a0,a0,-30
+    2014:	cc0c                	sw	a1,24(s0)
+    2016:	          	0xeee0bbb
+
+00002018 <test_data>:
+    2018:	0eee                	slli	t4,t4,0x1b
+    201a:	dd0d                	beqz	a0,1f54 <fromhost+0xe54>
+    201c:	00f0                	addi	a2,sp,76
+    201e:	0fff                	0xfff
+    2020:	5678                	lw	a4,108(a2)
+    2022:	1234                	addi	a3,sp,296
+    2024:	def0                	sw	a2,124(a3)
+    2026:	9abc                	0x9abc
+    2028:	3210                	fld	fa2,32(a2)
+    202a:	7654                	flw	fa3,44(a2)
+    202c:	ba98                	fsd	fa4,48(a3)
+    202e:	fedc                	fsw	fa5,60(a3)
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_2_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_3_res>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_4_res>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_5_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+
+00002094 <test_6_res>:
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_7_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	0000                	unimp
+	...
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf
new file mode 100644
index 0000000..2d9a9fe
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.bin
new file mode 100644
index 0000000..c8f25aa
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.objdump
new file mode 100644
index 0000000..23de5f4
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf.objdump
@@ -0,0 +1,346 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LBU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	fb028293          	addi	t0,t0,-80 # 2030 <begin_signature>
+  88:	00002f97          	auipc	t6,0x2
+  8c:	f90f8f93          	addi	t6,t6,-112 # 2018 <test_data>
+  90:	000fc003          	lbu	zero,0(t6)
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00002f17          	auipc	t5,0x2
+  9c:	f80f0f13          	addi	t5,t5,-128 # 2018 <test_data>
+  a0:	ffef4083          	lbu	ra,-2(t5)
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00002e97          	auipc	t4,0x2
+  ac:	f70e8e93          	addi	t4,t4,-144 # 2018 <test_data>
+  b0:	003ec103          	lbu	sp,3(t4)
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	00002e17          	auipc	t3,0x2
+  bc:	f60e0e13          	addi	t3,t3,-160 # 2018 <test_data>
+  c0:	ffce4183          	lbu	gp,-4(t3)
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00002d97          	auipc	s11,0x2
+  cc:	f50d8d93          	addi	s11,s11,-176 # 2018 <test_data>
+  d0:	002dc203          	lbu	tp,2(s11)
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f6c08093          	addi	ra,ra,-148 # 2044 <test_2_res>
+  e0:	00002d17          	auipc	s10,0x2
+  e4:	f38d0d13          	addi	s10,s10,-200 # 2018 <test_data>
+  e8:	004d4283          	lbu	t0,4(s10)
+  ec:	0050a023          	sw	t0,0(ra)
+  f0:	00002c97          	auipc	s9,0x2
+  f4:	f28c8c93          	addi	s9,s9,-216 # 2018 <test_data>
+  f8:	fffcc303          	lbu	t1,-1(s9)
+  fc:	0060a223          	sw	t1,4(ra)
+ 100:	00002c17          	auipc	s8,0x2
+ 104:	f18c0c13          	addi	s8,s8,-232 # 2018 <test_data>
+ 108:	001c4383          	lbu	t2,1(s8)
+ 10c:	0070a423          	sw	t2,8(ra)
+ 110:	00002b97          	auipc	s7,0x2
+ 114:	f08b8b93          	addi	s7,s7,-248 # 2018 <test_data>
+ 118:	000bc403          	lbu	s0,0(s7)
+ 11c:	0080a623          	sw	s0,12(ra)
+ 120:	00002b17          	auipc	s6,0x2
+ 124:	ef8b0b13          	addi	s6,s6,-264 # 2018 <test_data>
+ 128:	ffeb4483          	lbu	s1,-2(s6)
+ 12c:	0090a823          	sw	s1,16(ra)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	f2808093          	addi	ra,ra,-216 # 2058 <test_3_res>
+ 138:	00002a97          	auipc	s5,0x2
+ 13c:	ee0a8a93          	addi	s5,s5,-288 # 2018 <test_data>
+ 140:	003ac503          	lbu	a0,3(s5)
+ 144:	00a0a023          	sw	a0,0(ra)
+ 148:	00002a17          	auipc	s4,0x2
+ 14c:	ed0a0a13          	addi	s4,s4,-304 # 2018 <test_data>
+ 150:	ffca4583          	lbu	a1,-4(s4)
+ 154:	00b0a223          	sw	a1,4(ra)
+ 158:	00002997          	auipc	s3,0x2
+ 15c:	ec098993          	addi	s3,s3,-320 # 2018 <test_data>
+ 160:	0029c603          	lbu	a2,2(s3)
+ 164:	00c0a423          	sw	a2,8(ra)
+ 168:	00002917          	auipc	s2,0x2
+ 16c:	eb090913          	addi	s2,s2,-336 # 2018 <test_data>
+ 170:	00494683          	lbu	a3,4(s2)
+ 174:	00d0a623          	sw	a3,12(ra)
+ 178:	00002897          	auipc	a7,0x2
+ 17c:	ea088893          	addi	a7,a7,-352 # 2018 <test_data>
+ 180:	fff8c703          	lbu	a4,-1(a7)
+ 184:	00e0a823          	sw	a4,16(ra)
+ 188:	00002117          	auipc	sp,0x2
+ 18c:	ee410113          	addi	sp,sp,-284 # 206c <test_4_res>
+ 190:	00002817          	auipc	a6,0x2
+ 194:	e8880813          	addi	a6,a6,-376 # 2018 <test_data>
+ 198:	00184783          	lbu	a5,1(a6)
+ 19c:	00f12023          	sw	a5,0(sp)
+ 1a0:	00002797          	auipc	a5,0x2
+ 1a4:	e7878793          	addi	a5,a5,-392 # 2018 <test_data>
+ 1a8:	0007c803          	lbu	a6,0(a5)
+ 1ac:	01012223          	sw	a6,4(sp)
+ 1b0:	00002717          	auipc	a4,0x2
+ 1b4:	e6870713          	addi	a4,a4,-408 # 2018 <test_data>
+ 1b8:	ffe74883          	lbu	a7,-2(a4)
+ 1bc:	01112423          	sw	a7,8(sp)
+ 1c0:	00002697          	auipc	a3,0x2
+ 1c4:	e5868693          	addi	a3,a3,-424 # 2018 <test_data>
+ 1c8:	0036c903          	lbu	s2,3(a3)
+ 1cc:	01212623          	sw	s2,12(sp)
+ 1d0:	00002617          	auipc	a2,0x2
+ 1d4:	e4860613          	addi	a2,a2,-440 # 2018 <test_data>
+ 1d8:	ffc64983          	lbu	s3,-4(a2)
+ 1dc:	01312823          	sw	s3,16(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	ea008093          	addi	ra,ra,-352 # 2080 <test_5_res>
+ 1e8:	00002597          	auipc	a1,0x2
+ 1ec:	e3058593          	addi	a1,a1,-464 # 2018 <test_data>
+ 1f0:	0025ca03          	lbu	s4,2(a1)
+ 1f4:	0140a023          	sw	s4,0(ra)
+ 1f8:	00002517          	auipc	a0,0x2
+ 1fc:	e2050513          	addi	a0,a0,-480 # 2018 <test_data>
+ 200:	00454a83          	lbu	s5,4(a0)
+ 204:	0150a223          	sw	s5,4(ra)
+ 208:	00002497          	auipc	s1,0x2
+ 20c:	e1048493          	addi	s1,s1,-496 # 2018 <test_data>
+ 210:	fff4cb03          	lbu	s6,-1(s1)
+ 214:	0160a423          	sw	s6,8(ra)
+ 218:	00002417          	auipc	s0,0x2
+ 21c:	e0040413          	addi	s0,s0,-512 # 2018 <test_data>
+ 220:	00144b83          	lbu	s7,1(s0)
+ 224:	0170a623          	sw	s7,12(ra)
+ 228:	00002397          	auipc	t2,0x2
+ 22c:	df038393          	addi	t2,t2,-528 # 2018 <test_data>
+ 230:	0003cc03          	lbu	s8,0(t2)
+ 234:	0180a823          	sw	s8,16(ra)
+ 238:	00002097          	auipc	ra,0x2
+ 23c:	e5c08093          	addi	ra,ra,-420 # 2094 <test_6_res>
+ 240:	00002317          	auipc	t1,0x2
+ 244:	dd830313          	addi	t1,t1,-552 # 2018 <test_data>
+ 248:	ffe34c83          	lbu	s9,-2(t1)
+ 24c:	0190a023          	sw	s9,0(ra)
+ 250:	00002297          	auipc	t0,0x2
+ 254:	dc828293          	addi	t0,t0,-568 # 2018 <test_data>
+ 258:	0032cd03          	lbu	s10,3(t0)
+ 25c:	01a0a223          	sw	s10,4(ra)
+ 260:	00002217          	auipc	tp,0x2
+ 264:	db820213          	addi	tp,tp,-584 # 2018 <test_data>
+ 268:	ffc24d83          	lbu	s11,-4(tp) # fffffffc <_end+0xffffddf8>
+ 26c:	01b0a423          	sw	s11,8(ra)
+ 270:	00002197          	auipc	gp,0x2
+ 274:	da818193          	addi	gp,gp,-600 # 2018 <test_data>
+ 278:	0021ce03          	lbu	t3,2(gp)
+ 27c:	01c0a623          	sw	t3,12(ra)
+ 280:	00002117          	auipc	sp,0x2
+ 284:	d9810113          	addi	sp,sp,-616 # 2018 <test_data>
+ 288:	00414e83          	lbu	t4,4(sp)
+ 28c:	01d0a823          	sw	t4,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e1810113          	addi	sp,sp,-488 # 20a8 <test_7_res>
+ 298:	00002097          	auipc	ra,0x2
+ 29c:	d8008093          	addi	ra,ra,-640 # 2018 <test_data>
+ 2a0:	fff0cf03          	lbu	t5,-1(ra)
+ 2a4:	01e12023          	sw	t5,0(sp)
+ 2a8:	00002097          	auipc	ra,0x2
+ 2ac:	d7008093          	addi	ra,ra,-656 # 2018 <test_data>
+ 2b0:	0010cf83          	lbu	t6,1(ra)
+ 2b4:	01f12223          	sw	t6,4(sp)
+ 2b8:	00002297          	auipc	t0,0x2
+ 2bc:	d7828293          	addi	t0,t0,-648 # 2030 <begin_signature>
+ 2c0:	10000337          	lui	t1,0x10000
+ 2c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c8:	00532023          	sw	t0,0(t1)
+ 2cc:	00002297          	auipc	t0,0x2
+ 2d0:	df428293          	addi	t0,t0,-524 # 20c0 <end_signature>
+ 2d4:	10000337          	lui	t1,0x10000
+ 2d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2dc:	00532023          	sw	t0,0(t1)
+ 2e0:	00100293          	li	t0,1
+ 2e4:	10000337          	lui	t1,0x10000
+ 2e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2ec:	00532023          	sw	t0,0(t1)
+ 2f0:	00000013          	nop
+ 2f4:	00100193          	li	gp,1
+ 2f8:	00000073          	ecall
+
+000002fc <end_testcode>:
+ 2fc:	c0001073          	unimp
+ 300:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_data_start>:
+    2000:	f222                	fsw	fs0,36(sp)
+    2002:	11f1                	addi	gp,gp,-4
+    2004:	44f4                	lw	a3,76(s1)
+    2006:	f666f333          	0xf666f333
+    200a:	55f5                	li	a1,-3
+    200c:	88f8                	0x88f8
+    200e:	0aaaf777          	0xaaaf777
+    2012:	9909                	andi	a0,a0,-30
+    2014:	cc0c                	sw	a1,24(s0)
+    2016:	          	0xeee0bbb
+
+00002018 <test_data>:
+    2018:	0eee                	slli	t4,t4,0x1b
+    201a:	dd0d                	beqz	a0,1f54 <fromhost+0xe54>
+    201c:	00f0                	addi	a2,sp,76
+    201e:	0fff                	0xfff
+    2020:	5678                	lw	a4,108(a2)
+    2022:	1234                	addi	a3,sp,296
+    2024:	def0                	sw	a2,124(a3)
+    2026:	9abc                	0x9abc
+    2028:	3210                	fld	fa2,32(a2)
+    202a:	7654                	flw	fa3,44(a2)
+    202c:	ba98                	fsd	fa4,48(a3)
+    202e:	fedc                	fsw	fa5,60(a3)
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_2_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_3_res>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_4_res>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_5_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+
+00002094 <test_6_res>:
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_7_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	0000                	unimp
+	...
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf
new file mode 100644
index 0000000..7de6df3
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.bin
new file mode 100644
index 0000000..bd9e7ae
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.objdump
new file mode 100644
index 0000000..5be7d7f
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf.objdump
@@ -0,0 +1,346 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LH-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	fb028293          	addi	t0,t0,-80 # 2030 <begin_signature>
+  88:	00002f97          	auipc	t6,0x2
+  8c:	f90f8f93          	addi	t6,t6,-112 # 2018 <test_data>
+  90:	000f9003          	lh	zero,0(t6)
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00002f17          	auipc	t5,0x2
+  9c:	f80f0f13          	addi	t5,t5,-128 # 2018 <test_data>
+  a0:	ffef1083          	lh	ra,-2(t5)
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00002e97          	auipc	t4,0x2
+  ac:	f70e8e93          	addi	t4,t4,-144 # 2018 <test_data>
+  b0:	002e9103          	lh	sp,2(t4)
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	00002e17          	auipc	t3,0x2
+  bc:	f60e0e13          	addi	t3,t3,-160 # 2018 <test_data>
+  c0:	ffce1183          	lh	gp,-4(t3)
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00002d97          	auipc	s11,0x2
+  cc:	f50d8d93          	addi	s11,s11,-176 # 2018 <test_data>
+  d0:	002d9203          	lh	tp,2(s11)
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f6c08093          	addi	ra,ra,-148 # 2044 <test_2_res>
+  e0:	00002d17          	auipc	s10,0x2
+  e4:	f38d0d13          	addi	s10,s10,-200 # 2018 <test_data>
+  e8:	004d1283          	lh	t0,4(s10)
+  ec:	0050a023          	sw	t0,0(ra)
+  f0:	00002c97          	auipc	s9,0x2
+  f4:	f28c8c93          	addi	s9,s9,-216 # 2018 <test_data>
+  f8:	000c9303          	lh	t1,0(s9)
+  fc:	0060a223          	sw	t1,4(ra)
+ 100:	00002c17          	auipc	s8,0x2
+ 104:	f18c0c13          	addi	s8,s8,-232 # 2018 <test_data>
+ 108:	000c1383          	lh	t2,0(s8)
+ 10c:	0070a423          	sw	t2,8(ra)
+ 110:	00002b97          	auipc	s7,0x2
+ 114:	f08b8b93          	addi	s7,s7,-248 # 2018 <test_data>
+ 118:	000b9403          	lh	s0,0(s7)
+ 11c:	0080a623          	sw	s0,12(ra)
+ 120:	00002b17          	auipc	s6,0x2
+ 124:	ef8b0b13          	addi	s6,s6,-264 # 2018 <test_data>
+ 128:	ffeb1483          	lh	s1,-2(s6)
+ 12c:	0090a823          	sw	s1,16(ra)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	f2808093          	addi	ra,ra,-216 # 2058 <test_3_res>
+ 138:	00002a97          	auipc	s5,0x2
+ 13c:	ee0a8a93          	addi	s5,s5,-288 # 2018 <test_data>
+ 140:	002a9503          	lh	a0,2(s5)
+ 144:	00a0a023          	sw	a0,0(ra)
+ 148:	00002a17          	auipc	s4,0x2
+ 14c:	ed0a0a13          	addi	s4,s4,-304 # 2018 <test_data>
+ 150:	ffca1583          	lh	a1,-4(s4)
+ 154:	00b0a223          	sw	a1,4(ra)
+ 158:	00002997          	auipc	s3,0x2
+ 15c:	ec098993          	addi	s3,s3,-320 # 2018 <test_data>
+ 160:	00299603          	lh	a2,2(s3)
+ 164:	00c0a423          	sw	a2,8(ra)
+ 168:	00002917          	auipc	s2,0x2
+ 16c:	eb090913          	addi	s2,s2,-336 # 2018 <test_data>
+ 170:	00491683          	lh	a3,4(s2)
+ 174:	00d0a623          	sw	a3,12(ra)
+ 178:	00002897          	auipc	a7,0x2
+ 17c:	ea088893          	addi	a7,a7,-352 # 2018 <test_data>
+ 180:	00089703          	lh	a4,0(a7)
+ 184:	00e0a823          	sw	a4,16(ra)
+ 188:	00002117          	auipc	sp,0x2
+ 18c:	ee410113          	addi	sp,sp,-284 # 206c <test_4_res>
+ 190:	00002817          	auipc	a6,0x2
+ 194:	e8880813          	addi	a6,a6,-376 # 2018 <test_data>
+ 198:	00081783          	lh	a5,0(a6)
+ 19c:	00f12023          	sw	a5,0(sp)
+ 1a0:	00002797          	auipc	a5,0x2
+ 1a4:	e7878793          	addi	a5,a5,-392 # 2018 <test_data>
+ 1a8:	00079803          	lh	a6,0(a5)
+ 1ac:	01012223          	sw	a6,4(sp)
+ 1b0:	00002717          	auipc	a4,0x2
+ 1b4:	e6870713          	addi	a4,a4,-408 # 2018 <test_data>
+ 1b8:	ffe71883          	lh	a7,-2(a4)
+ 1bc:	01112423          	sw	a7,8(sp)
+ 1c0:	00002697          	auipc	a3,0x2
+ 1c4:	e5868693          	addi	a3,a3,-424 # 2018 <test_data>
+ 1c8:	00269903          	lh	s2,2(a3)
+ 1cc:	01212623          	sw	s2,12(sp)
+ 1d0:	00002617          	auipc	a2,0x2
+ 1d4:	e4860613          	addi	a2,a2,-440 # 2018 <test_data>
+ 1d8:	ffc61983          	lh	s3,-4(a2)
+ 1dc:	01312823          	sw	s3,16(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	ea008093          	addi	ra,ra,-352 # 2080 <test_5_res>
+ 1e8:	00002597          	auipc	a1,0x2
+ 1ec:	e3058593          	addi	a1,a1,-464 # 2018 <test_data>
+ 1f0:	00259a03          	lh	s4,2(a1)
+ 1f4:	0140a023          	sw	s4,0(ra)
+ 1f8:	00002517          	auipc	a0,0x2
+ 1fc:	e2050513          	addi	a0,a0,-480 # 2018 <test_data>
+ 200:	00451a83          	lh	s5,4(a0)
+ 204:	0150a223          	sw	s5,4(ra)
+ 208:	00002497          	auipc	s1,0x2
+ 20c:	e1048493          	addi	s1,s1,-496 # 2018 <test_data>
+ 210:	00049b03          	lh	s6,0(s1)
+ 214:	0160a423          	sw	s6,8(ra)
+ 218:	00002417          	auipc	s0,0x2
+ 21c:	e0040413          	addi	s0,s0,-512 # 2018 <test_data>
+ 220:	00041b83          	lh	s7,0(s0)
+ 224:	0170a623          	sw	s7,12(ra)
+ 228:	00002397          	auipc	t2,0x2
+ 22c:	df038393          	addi	t2,t2,-528 # 2018 <test_data>
+ 230:	00039c03          	lh	s8,0(t2)
+ 234:	0180a823          	sw	s8,16(ra)
+ 238:	00002097          	auipc	ra,0x2
+ 23c:	e5c08093          	addi	ra,ra,-420 # 2094 <test_6_res>
+ 240:	00002317          	auipc	t1,0x2
+ 244:	dd830313          	addi	t1,t1,-552 # 2018 <test_data>
+ 248:	ffe31c83          	lh	s9,-2(t1)
+ 24c:	0190a023          	sw	s9,0(ra)
+ 250:	00002297          	auipc	t0,0x2
+ 254:	dc828293          	addi	t0,t0,-568 # 2018 <test_data>
+ 258:	00229d03          	lh	s10,2(t0)
+ 25c:	01a0a223          	sw	s10,4(ra)
+ 260:	00002217          	auipc	tp,0x2
+ 264:	db820213          	addi	tp,tp,-584 # 2018 <test_data>
+ 268:	ffc21d83          	lh	s11,-4(tp) # fffffffc <_end+0xffffddf8>
+ 26c:	01b0a423          	sw	s11,8(ra)
+ 270:	00002197          	auipc	gp,0x2
+ 274:	da818193          	addi	gp,gp,-600 # 2018 <test_data>
+ 278:	00219e03          	lh	t3,2(gp)
+ 27c:	01c0a623          	sw	t3,12(ra)
+ 280:	00002117          	auipc	sp,0x2
+ 284:	d9810113          	addi	sp,sp,-616 # 2018 <test_data>
+ 288:	00411e83          	lh	t4,4(sp)
+ 28c:	01d0a823          	sw	t4,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e1810113          	addi	sp,sp,-488 # 20a8 <test_7_res>
+ 298:	00002097          	auipc	ra,0x2
+ 29c:	d8008093          	addi	ra,ra,-640 # 2018 <test_data>
+ 2a0:	00009f03          	lh	t5,0(ra)
+ 2a4:	01e12023          	sw	t5,0(sp)
+ 2a8:	00002097          	auipc	ra,0x2
+ 2ac:	d7008093          	addi	ra,ra,-656 # 2018 <test_data>
+ 2b0:	00009f83          	lh	t6,0(ra)
+ 2b4:	01f12223          	sw	t6,4(sp)
+ 2b8:	00002297          	auipc	t0,0x2
+ 2bc:	d7828293          	addi	t0,t0,-648 # 2030 <begin_signature>
+ 2c0:	10000337          	lui	t1,0x10000
+ 2c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c8:	00532023          	sw	t0,0(t1)
+ 2cc:	00002297          	auipc	t0,0x2
+ 2d0:	df428293          	addi	t0,t0,-524 # 20c0 <end_signature>
+ 2d4:	10000337          	lui	t1,0x10000
+ 2d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2dc:	00532023          	sw	t0,0(t1)
+ 2e0:	00100293          	li	t0,1
+ 2e4:	10000337          	lui	t1,0x10000
+ 2e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2ec:	00532023          	sw	t0,0(t1)
+ 2f0:	00000013          	nop
+ 2f4:	00100193          	li	gp,1
+ 2f8:	00000073          	ecall
+
+000002fc <end_testcode>:
+ 2fc:	c0001073          	unimp
+ 300:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_data_start>:
+    2000:	f222                	fsw	fs0,36(sp)
+    2002:	11f1                	addi	gp,gp,-4
+    2004:	44f4                	lw	a3,76(s1)
+    2006:	f666f333          	0xf666f333
+    200a:	55f5                	li	a1,-3
+    200c:	88f8                	0x88f8
+    200e:	0aaaf777          	0xaaaf777
+    2012:	9909                	andi	a0,a0,-30
+    2014:	cc0c                	sw	a1,24(s0)
+    2016:	          	0xeee0bbb
+
+00002018 <test_data>:
+    2018:	0eee                	slli	t4,t4,0x1b
+    201a:	dd0d                	beqz	a0,1f54 <fromhost+0xe54>
+    201c:	00f0                	addi	a2,sp,76
+    201e:	0fff                	0xfff
+    2020:	5678                	lw	a4,108(a2)
+    2022:	1234                	addi	a3,sp,296
+    2024:	def0                	sw	a2,124(a3)
+    2026:	9abc                	0x9abc
+    2028:	3210                	fld	fa2,32(a2)
+    202a:	7654                	flw	fa3,44(a2)
+    202c:	ba98                	fsd	fa4,48(a3)
+    202e:	fedc                	fsw	fa5,60(a3)
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_2_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_3_res>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_4_res>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_5_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+
+00002094 <test_6_res>:
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_7_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	0000                	unimp
+	...
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf
new file mode 100644
index 0000000..157db8b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.bin
new file mode 100644
index 0000000..8ff9fd6
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.objdump
new file mode 100644
index 0000000..a3a7604
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf.objdump
@@ -0,0 +1,346 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LHU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	fb028293          	addi	t0,t0,-80 # 2030 <begin_signature>
+  88:	00002f97          	auipc	t6,0x2
+  8c:	f90f8f93          	addi	t6,t6,-112 # 2018 <test_data>
+  90:	000fd003          	lhu	zero,0(t6)
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00002f17          	auipc	t5,0x2
+  9c:	f80f0f13          	addi	t5,t5,-128 # 2018 <test_data>
+  a0:	ffef5083          	lhu	ra,-2(t5)
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00002e97          	auipc	t4,0x2
+  ac:	f70e8e93          	addi	t4,t4,-144 # 2018 <test_data>
+  b0:	002ed103          	lhu	sp,2(t4)
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	00002e17          	auipc	t3,0x2
+  bc:	f60e0e13          	addi	t3,t3,-160 # 2018 <test_data>
+  c0:	ffce5183          	lhu	gp,-4(t3)
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00002d97          	auipc	s11,0x2
+  cc:	f50d8d93          	addi	s11,s11,-176 # 2018 <test_data>
+  d0:	002dd203          	lhu	tp,2(s11)
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f6c08093          	addi	ra,ra,-148 # 2044 <test_2_res>
+  e0:	00002d17          	auipc	s10,0x2
+  e4:	f38d0d13          	addi	s10,s10,-200 # 2018 <test_data>
+  e8:	004d5283          	lhu	t0,4(s10)
+  ec:	0050a023          	sw	t0,0(ra)
+  f0:	00002c97          	auipc	s9,0x2
+  f4:	f28c8c93          	addi	s9,s9,-216 # 2018 <test_data>
+  f8:	000cd303          	lhu	t1,0(s9)
+  fc:	0060a223          	sw	t1,4(ra)
+ 100:	00002c17          	auipc	s8,0x2
+ 104:	f18c0c13          	addi	s8,s8,-232 # 2018 <test_data>
+ 108:	000c5383          	lhu	t2,0(s8)
+ 10c:	0070a423          	sw	t2,8(ra)
+ 110:	00002b97          	auipc	s7,0x2
+ 114:	f08b8b93          	addi	s7,s7,-248 # 2018 <test_data>
+ 118:	000bd403          	lhu	s0,0(s7)
+ 11c:	0080a623          	sw	s0,12(ra)
+ 120:	00002b17          	auipc	s6,0x2
+ 124:	ef8b0b13          	addi	s6,s6,-264 # 2018 <test_data>
+ 128:	ffeb5483          	lhu	s1,-2(s6)
+ 12c:	0090a823          	sw	s1,16(ra)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	f2808093          	addi	ra,ra,-216 # 2058 <test_3_res>
+ 138:	00002a97          	auipc	s5,0x2
+ 13c:	ee0a8a93          	addi	s5,s5,-288 # 2018 <test_data>
+ 140:	002ad503          	lhu	a0,2(s5)
+ 144:	00a0a023          	sw	a0,0(ra)
+ 148:	00002a17          	auipc	s4,0x2
+ 14c:	ed0a0a13          	addi	s4,s4,-304 # 2018 <test_data>
+ 150:	ffca5583          	lhu	a1,-4(s4)
+ 154:	00b0a223          	sw	a1,4(ra)
+ 158:	00002997          	auipc	s3,0x2
+ 15c:	ec098993          	addi	s3,s3,-320 # 2018 <test_data>
+ 160:	0029d603          	lhu	a2,2(s3)
+ 164:	00c0a423          	sw	a2,8(ra)
+ 168:	00002917          	auipc	s2,0x2
+ 16c:	eb090913          	addi	s2,s2,-336 # 2018 <test_data>
+ 170:	00495683          	lhu	a3,4(s2)
+ 174:	00d0a623          	sw	a3,12(ra)
+ 178:	00002897          	auipc	a7,0x2
+ 17c:	ea088893          	addi	a7,a7,-352 # 2018 <test_data>
+ 180:	0008d703          	lhu	a4,0(a7)
+ 184:	00e0a823          	sw	a4,16(ra)
+ 188:	00002117          	auipc	sp,0x2
+ 18c:	ee410113          	addi	sp,sp,-284 # 206c <test_4_res>
+ 190:	00002817          	auipc	a6,0x2
+ 194:	e8880813          	addi	a6,a6,-376 # 2018 <test_data>
+ 198:	00085783          	lhu	a5,0(a6)
+ 19c:	00f12023          	sw	a5,0(sp)
+ 1a0:	00002797          	auipc	a5,0x2
+ 1a4:	e7878793          	addi	a5,a5,-392 # 2018 <test_data>
+ 1a8:	0007d803          	lhu	a6,0(a5)
+ 1ac:	01012223          	sw	a6,4(sp)
+ 1b0:	00002717          	auipc	a4,0x2
+ 1b4:	e6870713          	addi	a4,a4,-408 # 2018 <test_data>
+ 1b8:	ffe75883          	lhu	a7,-2(a4)
+ 1bc:	01112423          	sw	a7,8(sp)
+ 1c0:	00002697          	auipc	a3,0x2
+ 1c4:	e5868693          	addi	a3,a3,-424 # 2018 <test_data>
+ 1c8:	0026d903          	lhu	s2,2(a3)
+ 1cc:	01212623          	sw	s2,12(sp)
+ 1d0:	00002617          	auipc	a2,0x2
+ 1d4:	e4860613          	addi	a2,a2,-440 # 2018 <test_data>
+ 1d8:	ffc65983          	lhu	s3,-4(a2)
+ 1dc:	01312823          	sw	s3,16(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	ea008093          	addi	ra,ra,-352 # 2080 <test_5_res>
+ 1e8:	00002597          	auipc	a1,0x2
+ 1ec:	e3058593          	addi	a1,a1,-464 # 2018 <test_data>
+ 1f0:	0025da03          	lhu	s4,2(a1)
+ 1f4:	0140a023          	sw	s4,0(ra)
+ 1f8:	00002517          	auipc	a0,0x2
+ 1fc:	e2050513          	addi	a0,a0,-480 # 2018 <test_data>
+ 200:	00455a83          	lhu	s5,4(a0)
+ 204:	0150a223          	sw	s5,4(ra)
+ 208:	00002497          	auipc	s1,0x2
+ 20c:	e1048493          	addi	s1,s1,-496 # 2018 <test_data>
+ 210:	0004db03          	lhu	s6,0(s1)
+ 214:	0160a423          	sw	s6,8(ra)
+ 218:	00002417          	auipc	s0,0x2
+ 21c:	e0040413          	addi	s0,s0,-512 # 2018 <test_data>
+ 220:	00045b83          	lhu	s7,0(s0)
+ 224:	0170a623          	sw	s7,12(ra)
+ 228:	00002397          	auipc	t2,0x2
+ 22c:	df038393          	addi	t2,t2,-528 # 2018 <test_data>
+ 230:	0003dc03          	lhu	s8,0(t2)
+ 234:	0180a823          	sw	s8,16(ra)
+ 238:	00002097          	auipc	ra,0x2
+ 23c:	e5c08093          	addi	ra,ra,-420 # 2094 <test_6_res>
+ 240:	00002317          	auipc	t1,0x2
+ 244:	dd830313          	addi	t1,t1,-552 # 2018 <test_data>
+ 248:	ffe35c83          	lhu	s9,-2(t1)
+ 24c:	0190a023          	sw	s9,0(ra)
+ 250:	00002297          	auipc	t0,0x2
+ 254:	dc828293          	addi	t0,t0,-568 # 2018 <test_data>
+ 258:	0022dd03          	lhu	s10,2(t0)
+ 25c:	01a0a223          	sw	s10,4(ra)
+ 260:	00002217          	auipc	tp,0x2
+ 264:	db820213          	addi	tp,tp,-584 # 2018 <test_data>
+ 268:	ffc25d83          	lhu	s11,-4(tp) # fffffffc <_end+0xffffddf8>
+ 26c:	01b0a423          	sw	s11,8(ra)
+ 270:	00002197          	auipc	gp,0x2
+ 274:	da818193          	addi	gp,gp,-600 # 2018 <test_data>
+ 278:	0021de03          	lhu	t3,2(gp)
+ 27c:	01c0a623          	sw	t3,12(ra)
+ 280:	00002117          	auipc	sp,0x2
+ 284:	d9810113          	addi	sp,sp,-616 # 2018 <test_data>
+ 288:	00415e83          	lhu	t4,4(sp)
+ 28c:	01d0a823          	sw	t4,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e1810113          	addi	sp,sp,-488 # 20a8 <test_7_res>
+ 298:	00002097          	auipc	ra,0x2
+ 29c:	d8008093          	addi	ra,ra,-640 # 2018 <test_data>
+ 2a0:	0000df03          	lhu	t5,0(ra)
+ 2a4:	01e12023          	sw	t5,0(sp)
+ 2a8:	00002097          	auipc	ra,0x2
+ 2ac:	d7008093          	addi	ra,ra,-656 # 2018 <test_data>
+ 2b0:	0000df83          	lhu	t6,0(ra)
+ 2b4:	01f12223          	sw	t6,4(sp)
+ 2b8:	00002297          	auipc	t0,0x2
+ 2bc:	d7828293          	addi	t0,t0,-648 # 2030 <begin_signature>
+ 2c0:	10000337          	lui	t1,0x10000
+ 2c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c8:	00532023          	sw	t0,0(t1)
+ 2cc:	00002297          	auipc	t0,0x2
+ 2d0:	df428293          	addi	t0,t0,-524 # 20c0 <end_signature>
+ 2d4:	10000337          	lui	t1,0x10000
+ 2d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2dc:	00532023          	sw	t0,0(t1)
+ 2e0:	00100293          	li	t0,1
+ 2e4:	10000337          	lui	t1,0x10000
+ 2e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2ec:	00532023          	sw	t0,0(t1)
+ 2f0:	00000013          	nop
+ 2f4:	00100193          	li	gp,1
+ 2f8:	00000073          	ecall
+
+000002fc <end_testcode>:
+ 2fc:	c0001073          	unimp
+ 300:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_data_start>:
+    2000:	f222                	fsw	fs0,36(sp)
+    2002:	11f1                	addi	gp,gp,-4
+    2004:	44f4                	lw	a3,76(s1)
+    2006:	f666f333          	0xf666f333
+    200a:	55f5                	li	a1,-3
+    200c:	88f8                	0x88f8
+    200e:	0aaaf777          	0xaaaf777
+    2012:	9909                	andi	a0,a0,-30
+    2014:	cc0c                	sw	a1,24(s0)
+    2016:	          	0xeee0bbb
+
+00002018 <test_data>:
+    2018:	0eee                	slli	t4,t4,0x1b
+    201a:	dd0d                	beqz	a0,1f54 <fromhost+0xe54>
+    201c:	00f0                	addi	a2,sp,76
+    201e:	0fff                	0xfff
+    2020:	5678                	lw	a4,108(a2)
+    2022:	1234                	addi	a3,sp,296
+    2024:	def0                	sw	a2,124(a3)
+    2026:	9abc                	0x9abc
+    2028:	3210                	fld	fa2,32(a2)
+    202a:	7654                	flw	fa3,44(a2)
+    202c:	ba98                	fsd	fa4,48(a3)
+    202e:	fedc                	fsw	fa5,60(a3)
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_2_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_3_res>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_4_res>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_5_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+
+00002094 <test_6_res>:
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_7_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	0000                	unimp
+	...
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf
new file mode 100644
index 0000000..5de9a20
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.bin
new file mode 100644
index 0000000..764af96
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.objdump
new file mode 100644
index 0000000..ed421fa
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf.objdump
@@ -0,0 +1,256 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LUI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	00000037          	lui	zero,0x0
+  8c:	0002a023          	sw	zero,0(t0)
+  90:	000000b7          	lui	ra,0x0
+  94:	0012a223          	sw	ra,4(t0)
+  98:	007ff137          	lui	sp,0x7ff
+  9c:	0022a423          	sw	sp,8(t0)
+  a0:	000011b7          	lui	gp,0x1
+  a4:	0032a623          	sw	gp,12(t0)
+  a8:	01234237          	lui	tp,0x1234
+  ac:	0042a823          	sw	tp,16(t0)
+  b0:	00002097          	auipc	ra,0x2
+  b4:	f6408093          	addi	ra,ra,-156 # 2014 <test_2_res>
+  b8:	800002b7          	lui	t0,0x80000
+  bc:	0050a023          	sw	t0,0(ra)
+  c0:	01234337          	lui	t1,0x1234
+  c4:	0060a223          	sw	t1,4(ra)
+  c8:	fffff3b7          	lui	t2,0xfffff
+  cc:	0070a423          	sw	t2,8(ra)
+  d0:	00001437          	lui	s0,0x1
+  d4:	0080a623          	sw	s0,12(ra)
+  d8:	7ffff4b7          	lui	s1,0x7ffff
+  dc:	0090a823          	sw	s1,16(ra)
+  e0:	00002097          	auipc	ra,0x2
+  e4:	f4808093          	addi	ra,ra,-184 # 2028 <test_3_res>
+  e8:	54321537          	lui	a0,0x54321
+  ec:	00a0a023          	sw	a0,0(ra)
+  f0:	008005b7          	lui	a1,0x800
+  f4:	00b0a223          	sw	a1,4(ra)
+  f8:	00000637          	lui	a2,0x0
+  fc:	00c0a423          	sw	a2,8(ra)
+ 100:	007ff6b7          	lui	a3,0x7ff
+ 104:	00d0a623          	sw	a3,12(ra)
+ 108:	00000737          	lui	a4,0x0
+ 10c:	00e0a823          	sw	a4,16(ra)
+ 110:	00002117          	auipc	sp,0x2
+ 114:	f2c10113          	addi	sp,sp,-212 # 203c <test_4_res>
+ 118:	000017b7          	lui	a5,0x1
+ 11c:	00f12023          	sw	a5,0(sp)
+ 120:	00000837          	lui	a6,0x0
+ 124:	01012223          	sw	a6,4(sp)
+ 128:	000008b7          	lui	a7,0x0
+ 12c:	01112423          	sw	a7,8(sp)
+ 130:	007ff937          	lui	s2,0x7ff
+ 134:	01212623          	sw	s2,12(sp)
+ 138:	000019b7          	lui	s3,0x1
+ 13c:	01312823          	sw	s3,16(sp)
+ 140:	00002097          	auipc	ra,0x2
+ 144:	f1008093          	addi	ra,ra,-240 # 2050 <test_5_res>
+ 148:	01234a37          	lui	s4,0x1234
+ 14c:	0140a023          	sw	s4,0(ra)
+ 150:	80000ab7          	lui	s5,0x80000
+ 154:	0150a223          	sw	s5,4(ra)
+ 158:	01234b37          	lui	s6,0x1234
+ 15c:	0160a423          	sw	s6,8(ra)
+ 160:	fffffbb7          	lui	s7,0xfffff
+ 164:	0170a623          	sw	s7,12(ra)
+ 168:	00001c37          	lui	s8,0x1
+ 16c:	0180a823          	sw	s8,16(ra)
+ 170:	00002097          	auipc	ra,0x2
+ 174:	ef408093          	addi	ra,ra,-268 # 2064 <test_6_res>
+ 178:	7ffffcb7          	lui	s9,0x7ffff
+ 17c:	0190a023          	sw	s9,0(ra)
+ 180:	54321d37          	lui	s10,0x54321
+ 184:	01a0a223          	sw	s10,4(ra)
+ 188:	00800db7          	lui	s11,0x800
+ 18c:	01b0a423          	sw	s11,8(ra)
+ 190:	00000e37          	lui	t3,0x0
+ 194:	01c0a623          	sw	t3,12(ra)
+ 198:	007ffeb7          	lui	t4,0x7ff
+ 19c:	01d0a823          	sw	t4,16(ra)
+ 1a0:	00002117          	auipc	sp,0x2
+ 1a4:	ed810113          	addi	sp,sp,-296 # 2078 <test_7_res>
+ 1a8:	00000f37          	lui	t5,0x0
+ 1ac:	01e12023          	sw	t5,0(sp)
+ 1b0:	00001fb7          	lui	t6,0x1
+ 1b4:	01f12223          	sw	t6,4(sp)
+ 1b8:	00002297          	auipc	t0,0x2
+ 1bc:	e4828293          	addi	t0,t0,-440 # 2000 <begin_signature>
+ 1c0:	10000337          	lui	t1,0x10000
+ 1c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 1c8:	00532023          	sw	t0,0(t1)
+ 1cc:	00002297          	auipc	t0,0x2
+ 1d0:	ec428293          	addi	t0,t0,-316 # 2090 <end_signature>
+ 1d4:	10000337          	lui	t1,0x10000
+ 1d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 1dc:	00532023          	sw	t0,0(t1)
+ 1e0:	00100293          	li	t0,1
+ 1e4:	10000337          	lui	t1,0x10000
+ 1e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 1ec:	00532023          	sw	t0,0(t1)
+ 1f0:	00000013          	nop
+ 1f4:	00100193          	li	gp,1
+ 1f8:	00000073          	ecall
+
+000001fc <end_testcode>:
+ 1fc:	c0001073          	unimp
+ 200:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf
new file mode 100644
index 0000000..6fdd964
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.bin
new file mode 100644
index 0000000..f3936c7
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.objdump
new file mode 100644
index 0000000..85790ca
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf.objdump
@@ -0,0 +1,346 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-LW-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	fb028293          	addi	t0,t0,-80 # 2030 <begin_signature>
+  88:	00002f97          	auipc	t6,0x2
+  8c:	f90f8f93          	addi	t6,t6,-112 # 2018 <test_data>
+  90:	000fa003          	lw	zero,0(t6)
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00002f17          	auipc	t5,0x2
+  9c:	f80f0f13          	addi	t5,t5,-128 # 2018 <test_data>
+  a0:	000f2083          	lw	ra,0(t5)
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00002e97          	auipc	t4,0x2
+  ac:	f70e8e93          	addi	t4,t4,-144 # 2018 <test_data>
+  b0:	000ea103          	lw	sp,0(t4)
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	00002e17          	auipc	t3,0x2
+  bc:	f60e0e13          	addi	t3,t3,-160 # 2018 <test_data>
+  c0:	ffce2183          	lw	gp,-4(t3)
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00002d97          	auipc	s11,0x2
+  cc:	f50d8d93          	addi	s11,s11,-176 # 2018 <test_data>
+  d0:	000da203          	lw	tp,0(s11)
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f6c08093          	addi	ra,ra,-148 # 2044 <test_2_res>
+  e0:	00002d17          	auipc	s10,0x2
+  e4:	f38d0d13          	addi	s10,s10,-200 # 2018 <test_data>
+  e8:	004d2283          	lw	t0,4(s10)
+  ec:	0050a023          	sw	t0,0(ra)
+  f0:	00002c97          	auipc	s9,0x2
+  f4:	f28c8c93          	addi	s9,s9,-216 # 2018 <test_data>
+  f8:	000ca303          	lw	t1,0(s9)
+  fc:	0060a223          	sw	t1,4(ra)
+ 100:	00002c17          	auipc	s8,0x2
+ 104:	f18c0c13          	addi	s8,s8,-232 # 2018 <test_data>
+ 108:	000c2383          	lw	t2,0(s8)
+ 10c:	0070a423          	sw	t2,8(ra)
+ 110:	00002b97          	auipc	s7,0x2
+ 114:	f08b8b93          	addi	s7,s7,-248 # 2018 <test_data>
+ 118:	000ba403          	lw	s0,0(s7)
+ 11c:	0080a623          	sw	s0,12(ra)
+ 120:	00002b17          	auipc	s6,0x2
+ 124:	ef8b0b13          	addi	s6,s6,-264 # 2018 <test_data>
+ 128:	000b2483          	lw	s1,0(s6)
+ 12c:	0090a823          	sw	s1,16(ra)
+ 130:	00002097          	auipc	ra,0x2
+ 134:	f2808093          	addi	ra,ra,-216 # 2058 <test_3_res>
+ 138:	00002a97          	auipc	s5,0x2
+ 13c:	ee0a8a93          	addi	s5,s5,-288 # 2018 <test_data>
+ 140:	000aa503          	lw	a0,0(s5)
+ 144:	00a0a023          	sw	a0,0(ra)
+ 148:	00002a17          	auipc	s4,0x2
+ 14c:	ed0a0a13          	addi	s4,s4,-304 # 2018 <test_data>
+ 150:	ffca2583          	lw	a1,-4(s4)
+ 154:	00b0a223          	sw	a1,4(ra)
+ 158:	00002997          	auipc	s3,0x2
+ 15c:	ec098993          	addi	s3,s3,-320 # 2018 <test_data>
+ 160:	0009a603          	lw	a2,0(s3)
+ 164:	00c0a423          	sw	a2,8(ra)
+ 168:	00002917          	auipc	s2,0x2
+ 16c:	eb090913          	addi	s2,s2,-336 # 2018 <test_data>
+ 170:	00492683          	lw	a3,4(s2)
+ 174:	00d0a623          	sw	a3,12(ra)
+ 178:	00002897          	auipc	a7,0x2
+ 17c:	ea088893          	addi	a7,a7,-352 # 2018 <test_data>
+ 180:	0008a703          	lw	a4,0(a7)
+ 184:	00e0a823          	sw	a4,16(ra)
+ 188:	00002117          	auipc	sp,0x2
+ 18c:	ee410113          	addi	sp,sp,-284 # 206c <test_4_res>
+ 190:	00002817          	auipc	a6,0x2
+ 194:	e8880813          	addi	a6,a6,-376 # 2018 <test_data>
+ 198:	00082783          	lw	a5,0(a6)
+ 19c:	00f12023          	sw	a5,0(sp)
+ 1a0:	00002797          	auipc	a5,0x2
+ 1a4:	e7878793          	addi	a5,a5,-392 # 2018 <test_data>
+ 1a8:	0007a803          	lw	a6,0(a5)
+ 1ac:	01012223          	sw	a6,4(sp)
+ 1b0:	00002717          	auipc	a4,0x2
+ 1b4:	e6870713          	addi	a4,a4,-408 # 2018 <test_data>
+ 1b8:	00072883          	lw	a7,0(a4)
+ 1bc:	01112423          	sw	a7,8(sp)
+ 1c0:	00002697          	auipc	a3,0x2
+ 1c4:	e5868693          	addi	a3,a3,-424 # 2018 <test_data>
+ 1c8:	0006a903          	lw	s2,0(a3)
+ 1cc:	01212623          	sw	s2,12(sp)
+ 1d0:	00002617          	auipc	a2,0x2
+ 1d4:	e4860613          	addi	a2,a2,-440 # 2018 <test_data>
+ 1d8:	ffc62983          	lw	s3,-4(a2)
+ 1dc:	01312823          	sw	s3,16(sp)
+ 1e0:	00002097          	auipc	ra,0x2
+ 1e4:	ea008093          	addi	ra,ra,-352 # 2080 <test_5_res>
+ 1e8:	00002597          	auipc	a1,0x2
+ 1ec:	e3058593          	addi	a1,a1,-464 # 2018 <test_data>
+ 1f0:	0005aa03          	lw	s4,0(a1)
+ 1f4:	0140a023          	sw	s4,0(ra)
+ 1f8:	00002517          	auipc	a0,0x2
+ 1fc:	e2050513          	addi	a0,a0,-480 # 2018 <test_data>
+ 200:	00452a83          	lw	s5,4(a0)
+ 204:	0150a223          	sw	s5,4(ra)
+ 208:	00002497          	auipc	s1,0x2
+ 20c:	e1048493          	addi	s1,s1,-496 # 2018 <test_data>
+ 210:	0004ab03          	lw	s6,0(s1)
+ 214:	0160a423          	sw	s6,8(ra)
+ 218:	00002417          	auipc	s0,0x2
+ 21c:	e0040413          	addi	s0,s0,-512 # 2018 <test_data>
+ 220:	00042b83          	lw	s7,0(s0)
+ 224:	0170a623          	sw	s7,12(ra)
+ 228:	00002397          	auipc	t2,0x2
+ 22c:	df038393          	addi	t2,t2,-528 # 2018 <test_data>
+ 230:	0003ac03          	lw	s8,0(t2)
+ 234:	0180a823          	sw	s8,16(ra)
+ 238:	00002097          	auipc	ra,0x2
+ 23c:	e5c08093          	addi	ra,ra,-420 # 2094 <test_6_res>
+ 240:	00002317          	auipc	t1,0x2
+ 244:	dd830313          	addi	t1,t1,-552 # 2018 <test_data>
+ 248:	00032c83          	lw	s9,0(t1)
+ 24c:	0190a023          	sw	s9,0(ra)
+ 250:	00002297          	auipc	t0,0x2
+ 254:	dc828293          	addi	t0,t0,-568 # 2018 <test_data>
+ 258:	0002ad03          	lw	s10,0(t0)
+ 25c:	01a0a223          	sw	s10,4(ra)
+ 260:	00002217          	auipc	tp,0x2
+ 264:	db820213          	addi	tp,tp,-584 # 2018 <test_data>
+ 268:	ffc22d83          	lw	s11,-4(tp) # fffffffc <_end+0xffffddf8>
+ 26c:	01b0a423          	sw	s11,8(ra)
+ 270:	00002197          	auipc	gp,0x2
+ 274:	da818193          	addi	gp,gp,-600 # 2018 <test_data>
+ 278:	0001ae03          	lw	t3,0(gp)
+ 27c:	01c0a623          	sw	t3,12(ra)
+ 280:	00002117          	auipc	sp,0x2
+ 284:	d9810113          	addi	sp,sp,-616 # 2018 <test_data>
+ 288:	00412e83          	lw	t4,4(sp)
+ 28c:	01d0a823          	sw	t4,16(ra)
+ 290:	00002117          	auipc	sp,0x2
+ 294:	e1810113          	addi	sp,sp,-488 # 20a8 <test_7_res>
+ 298:	00002097          	auipc	ra,0x2
+ 29c:	d8008093          	addi	ra,ra,-640 # 2018 <test_data>
+ 2a0:	0000af03          	lw	t5,0(ra)
+ 2a4:	01e12023          	sw	t5,0(sp)
+ 2a8:	00002097          	auipc	ra,0x2
+ 2ac:	d7008093          	addi	ra,ra,-656 # 2018 <test_data>
+ 2b0:	0000af83          	lw	t6,0(ra)
+ 2b4:	01f12223          	sw	t6,4(sp)
+ 2b8:	00002297          	auipc	t0,0x2
+ 2bc:	d7828293          	addi	t0,t0,-648 # 2030 <begin_signature>
+ 2c0:	10000337          	lui	t1,0x10000
+ 2c4:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c8:	00532023          	sw	t0,0(t1)
+ 2cc:	00002297          	auipc	t0,0x2
+ 2d0:	df428293          	addi	t0,t0,-524 # 20c0 <end_signature>
+ 2d4:	10000337          	lui	t1,0x10000
+ 2d8:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2dc:	00532023          	sw	t0,0(t1)
+ 2e0:	00100293          	li	t0,1
+ 2e4:	10000337          	lui	t1,0x10000
+ 2e8:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2ec:	00532023          	sw	t0,0(t1)
+ 2f0:	00000013          	nop
+ 2f4:	00100193          	li	gp,1
+ 2f8:	00000073          	ecall
+
+000002fc <end_testcode>:
+ 2fc:	c0001073          	unimp
+ 300:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_data_start>:
+    2000:	f222                	fsw	fs0,36(sp)
+    2002:	11f1                	addi	gp,gp,-4
+    2004:	44f4                	lw	a3,76(s1)
+    2006:	f666f333          	0xf666f333
+    200a:	55f5                	li	a1,-3
+    200c:	88f8                	0x88f8
+    200e:	0aaaf777          	0xaaaf777
+    2012:	9909                	andi	a0,a0,-30
+    2014:	cc0c                	sw	a1,24(s0)
+    2016:	          	0xeee0bbb
+
+00002018 <test_data>:
+    2018:	0eee                	slli	t4,t4,0x1b
+    201a:	dd0d                	beqz	a0,1f54 <fromhost+0xe54>
+    201c:	00f0                	addi	a2,sp,76
+    201e:	0fff                	0xfff
+    2020:	5678                	lw	a4,108(a2)
+    2022:	1234                	addi	a3,sp,296
+    2024:	def0                	sw	a2,124(a3)
+    2026:	9abc                	0x9abc
+    2028:	3210                	fld	fa2,32(a2)
+    202a:	7654                	flw	fa3,44(a2)
+    202c:	ba98                	fsd	fa4,48(a3)
+    202e:	fedc                	fsw	fa5,60(a3)
+
+00002030 <begin_signature>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+
+00002044 <test_2_res>:
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_3_res>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_4_res>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_5_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+
+00002094 <test_6_res>:
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+
+000020a8 <test_7_res>:
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	0000                	unimp
+	...
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf
new file mode 100644
index 0000000..1b85a61
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.bin
new file mode 100644
index 0000000..8e1ad2a
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.objdump
new file mode 100644
index 0000000..b172d88
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf.objdump
@@ -0,0 +1,326 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_JMP-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00000097          	auipc	ra,0x0
+  84:	20808093          	addi	ra,ra,520 # 288 <_trap_handler>
+  88:	30509ff3          	csrrw	t6,mtvec,ra
+  8c:	30127073          	csrci	misa,4
+  90:	00002097          	auipc	ra,0x2
+  94:	f7008093          	addi	ra,ra,-144 # 2000 <begin_signature>
+  98:	11111137          	lui	sp,0x11111
+  9c:	11110113          	addi	sp,sp,273 # 11111111 <_end+0x1110ef0d>
+  a0:	00a0006f          	j	aa <begin_testcode+0x2a>
+  a4:	00000113          	li	sp,0
+  a8:	00002097          	auipc	ra,0x2
+  ac:	f6408093          	addi	ra,ra,-156 # 200c <test_A2_res>
+  b0:	22222137          	lui	sp,0x22222
+  b4:	22210113          	addi	sp,sp,546 # 22222222 <_end+0x2222001e>
+  b8:	00000217          	auipc	tp,0x0
+  bc:	01120213          	addi	tp,tp,17 # c9 <begin_testcode+0x49>
+  c0:	00020067          	jr	tp # 0 <_start>
+  c4:	00000113          	li	sp,0
+  c8:	0020a023          	sw	sp,0(ra)
+  cc:	00408093          	addi	ra,ra,4
+  d0:	33333137          	lui	sp,0x33333
+  d4:	33310113          	addi	sp,sp,819 # 33333333 <_end+0x3333112f>
+  d8:	00000217          	auipc	tp,0x0
+  dc:	01020213          	addi	tp,tp,16 # e8 <begin_testcode+0x68>
+  e0:	00120067          	jr	1(tp) # 0 <_start>
+  e4:	00000113          	li	sp,0
+  e8:	0020a023          	sw	sp,0(ra)
+  ec:	00408093          	addi	ra,ra,4
+  f0:	44444137          	lui	sp,0x44444
+  f4:	44410113          	addi	sp,sp,1092 # 44444444 <_end+0x44442240>
+  f8:	00000217          	auipc	tp,0x0
+  fc:	01420213          	addi	tp,tp,20 # 10c <begin_testcode+0x8c>
+ 100:	ffd20067          	jr	-3(tp) # 0 <_start>
+ 104:	00000113          	li	sp,0
+ 108:	0020a023          	sw	sp,0(ra)
+ 10c:	00408093          	addi	ra,ra,4
+ 110:	00002097          	auipc	ra,0x2
+ 114:	f0808093          	addi	ra,ra,-248 # 2018 <test_A3_res_exc>
+ 118:	55555137          	lui	sp,0x55555
+ 11c:	55510113          	addi	sp,sp,1365 # 55555555 <_end+0x55553351>
+ 120:	00000217          	auipc	tp,0x0
+ 124:	01220213          	addi	tp,tp,18 # 132 <begin_testcode+0xb2>
+ 128:	00020067          	jr	tp # 0 <_start>
+ 12c:	00000113          	li	sp,0
+ 130:	66666137          	lui	sp,0x66666
+ 134:	66610113          	addi	sp,sp,1638 # 66666666 <_end+0x66664462>
+ 138:	00000217          	auipc	tp,0x0
+ 13c:	01320213          	addi	tp,tp,19 # 14b <begin_testcode+0xcb>
+ 140:	00020067          	jr	tp # 0 <_start>
+ 144:	00000113          	li	sp,0
+ 148:	77777137          	lui	sp,0x77777
+ 14c:	77710113          	addi	sp,sp,1911 # 77777777 <_end+0x77775573>
+ 150:	00000217          	auipc	tp,0x0
+ 154:	01020213          	addi	tp,tp,16 # 160 <begin_testcode+0xe0>
+ 158:	00220067          	jr	2(tp) # 0 <_start>
+ 15c:	00000113          	li	sp,0
+ 160:	88889137          	lui	sp,0x88889
+ 164:	88810113          	addi	sp,sp,-1912 # 88888888 <_end+0x88886684>
+ 168:	00000217          	auipc	tp,0x0
+ 16c:	01020213          	addi	tp,tp,16 # 178 <begin_testcode+0xf8>
+ 170:	00320067          	jr	3(tp) # 0 <_start>
+ 174:	00000113          	li	sp,0
+ 178:	00002097          	auipc	ra,0x2
+ 17c:	ed008093          	addi	ra,ra,-304 # 2048 <test_B1_res_exc>
+ 180:	00500293          	li	t0,5
+ 184:	00600313          	li	t1,6
+ 188:	00628763          	beq	t0,t1,196 <begin_testcode+0x116>
+ 18c:	9999a137          	lui	sp,0x9999a
+ 190:	99910113          	addi	sp,sp,-1639 # 99999999 <_end+0x99997795>
+ 194:	00000013          	nop
+ 198:	00000013          	nop
+ 19c:	00528563          	beq	t0,t0,1a6 <begin_testcode+0x126>
+ 1a0:	00000113          	li	sp,0
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eb008093          	addi	ra,ra,-336 # 2054 <test_B2_res_exc>
+ 1ac:	00500293          	li	t0,5
+ 1b0:	00600313          	li	t1,6
+ 1b4:	00529763          	bne	t0,t0,1c2 <begin_testcode+0x142>
+ 1b8:	aaaab137          	lui	sp,0xaaaab
+ 1bc:	aaa10113          	addi	sp,sp,-1366 # aaaaaaaa <_end+0xaaaa88a6>
+ 1c0:	00000013          	nop
+ 1c4:	00000013          	nop
+ 1c8:	00629563          	bne	t0,t1,1d2 <begin_testcode+0x152>
+ 1cc:	00000113          	li	sp,0
+ 1d0:	00002097          	auipc	ra,0x2
+ 1d4:	e9008093          	addi	ra,ra,-368 # 2060 <test_B3_res_exc>
+ 1d8:	00500293          	li	t0,5
+ 1dc:	00600313          	li	t1,6
+ 1e0:	00534763          	blt	t1,t0,1ee <begin_testcode+0x16e>
+ 1e4:	bbbbc137          	lui	sp,0xbbbbc
+ 1e8:	bbb10113          	addi	sp,sp,-1093 # bbbbbbbb <_end+0xbbbb99b7>
+ 1ec:	00000013          	nop
+ 1f0:	00000013          	nop
+ 1f4:	0062c563          	blt	t0,t1,1fe <begin_testcode+0x17e>
+ 1f8:	00000113          	li	sp,0
+ 1fc:	00002097          	auipc	ra,0x2
+ 200:	e7008093          	addi	ra,ra,-400 # 206c <test_B4_res_exc>
+ 204:	00500293          	li	t0,5
+ 208:	00600313          	li	t1,6
+ 20c:	00536763          	bltu	t1,t0,21a <begin_testcode+0x19a>
+ 210:	ccccd137          	lui	sp,0xccccd
+ 214:	ccc10113          	addi	sp,sp,-820 # cccccccc <_end+0xccccaac8>
+ 218:	00000013          	nop
+ 21c:	00000013          	nop
+ 220:	0062e563          	bltu	t0,t1,22a <begin_testcode+0x1aa>
+ 224:	00000113          	li	sp,0
+ 228:	00002097          	auipc	ra,0x2
+ 22c:	e5008093          	addi	ra,ra,-432 # 2078 <test_B5_res_exc>
+ 230:	00500293          	li	t0,5
+ 234:	00600313          	li	t1,6
+ 238:	0062d763          	bge	t0,t1,246 <begin_testcode+0x1c6>
+ 23c:	dddde137          	lui	sp,0xdddde
+ 240:	ddd10113          	addi	sp,sp,-547 # dddddddd <_end+0xddddbbd9>
+ 244:	00000013          	nop
+ 248:	00000013          	nop
+ 24c:	00535563          	bge	t1,t0,256 <begin_testcode+0x1d6>
+ 250:	00000113          	li	sp,0
+ 254:	00002097          	auipc	ra,0x2
+ 258:	e3008093          	addi	ra,ra,-464 # 2084 <test_B6_res_exc>
+ 25c:	00500293          	li	t0,5
+ 260:	00600313          	li	t1,6
+ 264:	0062f763          	bgeu	t0,t1,272 <begin_testcode+0x1f2>
+ 268:	eeeef137          	lui	sp,0xeeeef
+ 26c:	eee10113          	addi	sp,sp,-274 # eeeeeeee <_end+0xeeeeccea>
+ 270:	00000013          	nop
+ 274:	00000013          	nop
+ 278:	00537563          	bgeu	t1,t0,282 <begin_testcode+0x202>
+ 27c:	00000113          	li	sp,0
+ 280:	305f9073          	csrw	mtvec,t6
+ 284:	0300006f          	j	2b4 <test_end>
+
+00000288 <_trap_handler>:
+ 288:	34302f73          	csrr	t5,mtval
+ 28c:	ffef0f13          	addi	t5,t5,-2
+ 290:	341f1073          	csrw	mepc,t5
+ 294:	34302f73          	csrr	t5,mtval
+ 298:	003f7f13          	andi	t5,t5,3
+ 29c:	01e0a023          	sw	t5,0(ra)
+ 2a0:	34202f73          	csrr	t5,mcause
+ 2a4:	01e0a223          	sw	t5,4(ra)
+ 2a8:	0020a423          	sw	sp,8(ra)
+ 2ac:	00c08093          	addi	ra,ra,12
+ 2b0:	30200073          	mret
+
+000002b4 <test_end>:
+ 2b4:	00002297          	auipc	t0,0x2
+ 2b8:	d4c28293          	addi	t0,t0,-692 # 2000 <begin_signature>
+ 2bc:	10000337          	lui	t1,0x10000
+ 2c0:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2c4:	00532023          	sw	t0,0(t1)
+ 2c8:	00002297          	auipc	t0,0x2
+ 2cc:	dc828293          	addi	t0,t0,-568 # 2090 <end_signature>
+ 2d0:	10000337          	lui	t1,0x10000
+ 2d4:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 2d8:	00532023          	sw	t0,0(t1)
+ 2dc:	00100293          	li	t0,1
+ 2e0:	10000337          	lui	t1,0x10000
+ 2e4:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 2e8:	00532023          	sw	t0,0(t1)
+ 2ec:	00000013          	nop
+ 2f0:	00100193          	li	gp,1
+ 2f4:	00000073          	ecall
+
+000002f8 <end_testcode>:
+ 2f8:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+
+0000200c <test_A2_res>:
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_A3_res_exc>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+
+00002048 <test_B1_res_exc>:
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+
+00002054 <test_B2_res_exc>:
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+
+00002060 <test_B3_res_exc>:
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+
+0000206c <test_B4_res_exc>:
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_B5_res_exc>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+
+00002084 <test_B6_res_exc>:
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf
new file mode 100644
index 0000000..a300a6e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.bin
new file mode 100644
index 0000000..69ad42e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.objdump
new file mode 100644
index 0000000..d914ea4
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf.objdump
@@ -0,0 +1,299 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-MISALIGN_LDST-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00000097          	auipc	ra,0x0
+  84:	14408093          	addi	ra,ra,324 # 1c4 <_trap_handler>
+  88:	30509ff3          	csrrw	t6,mtvec,ra
+  8c:	00002197          	auipc	gp,0x2
+  90:	f7418193          	addi	gp,gp,-140 # 2000 <test_A1_data>
+  94:	00002117          	auipc	sp,0x2
+  98:	f7c10113          	addi	sp,sp,-132 # 2010 <begin_signature>
+  9c:	00002097          	auipc	ra,0x2
+  a0:	f8408093          	addi	ra,ra,-124 # 2020 <test_A1_res_exc>
+  a4:	00500293          	li	t0,5
+  a8:	00600313          	li	t1,6
+  ac:	0001a203          	lw	tp,0(gp)
+  b0:	00412023          	sw	tp,0(sp)
+  b4:	0011a203          	lw	tp,1(gp)
+  b8:	00412223          	sw	tp,4(sp)
+  bc:	0021a203          	lw	tp,2(gp)
+  c0:	00412423          	sw	tp,8(sp)
+  c4:	0031a203          	lw	tp,3(gp)
+  c8:	00412623          	sw	tp,12(sp)
+  cc:	00002197          	auipc	gp,0x2
+  d0:	f3818193          	addi	gp,gp,-200 # 2004 <test_A2_data>
+  d4:	00002117          	auipc	sp,0x2
+  d8:	f6410113          	addi	sp,sp,-156 # 2038 <test_A2_res>
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f7c08093          	addi	ra,ra,-132 # 2058 <test_A2_res_exc>
+  e4:	00500293          	li	t0,5
+  e8:	00600313          	li	t1,6
+  ec:	00019203          	lh	tp,0(gp)
+  f0:	00412023          	sw	tp,0(sp)
+  f4:	00119203          	lh	tp,1(gp)
+  f8:	00412223          	sw	tp,4(sp)
+  fc:	00219203          	lh	tp,2(gp)
+ 100:	00412423          	sw	tp,8(sp)
+ 104:	00319203          	lh	tp,3(gp)
+ 108:	00412623          	sw	tp,12(sp)
+ 10c:	0001d203          	lhu	tp,0(gp)
+ 110:	00412823          	sw	tp,16(sp)
+ 114:	0011d203          	lhu	tp,1(gp)
+ 118:	00412a23          	sw	tp,20(sp)
+ 11c:	0021d203          	lhu	tp,2(gp)
+ 120:	00412c23          	sw	tp,24(sp)
+ 124:	0031d203          	lhu	tp,3(gp)
+ 128:	00412e23          	sw	tp,28(sp)
+ 12c:	00002117          	auipc	sp,0x2
+ 130:	f4c10113          	addi	sp,sp,-180 # 2078 <test_B1_res>
+ 134:	00002097          	auipc	ra,0x2
+ 138:	f5408093          	addi	ra,ra,-172 # 2088 <test_B1_res_exc>
+ 13c:	00000313          	li	t1,0
+ 140:	9999a2b7          	lui	t0,0x9999a
+ 144:	99928293          	addi	t0,t0,-1639 # 99999999 <_end+0x99997795>
+ 148:	00512023          	sw	t0,0(sp)
+ 14c:	00512223          	sw	t0,4(sp)
+ 150:	00512423          	sw	t0,8(sp)
+ 154:	00512623          	sw	t0,12(sp)
+ 158:	00612023          	sw	t1,0(sp)
+ 15c:	00410113          	addi	sp,sp,4
+ 160:	006120a3          	sw	t1,1(sp)
+ 164:	00410113          	addi	sp,sp,4
+ 168:	00612123          	sw	t1,2(sp)
+ 16c:	00410113          	addi	sp,sp,4
+ 170:	006121a3          	sw	t1,3(sp)
+ 174:	00002117          	auipc	sp,0x2
+ 178:	f2c10113          	addi	sp,sp,-212 # 20a0 <test_B2_res>
+ 17c:	00002097          	auipc	ra,0x2
+ 180:	f3408093          	addi	ra,ra,-204 # 20b0 <test_B2_res_exc>
+ 184:	00000313          	li	t1,0
+ 188:	9999a2b7          	lui	t0,0x9999a
+ 18c:	99928293          	addi	t0,t0,-1639 # 99999999 <_end+0x99997795>
+ 190:	00512023          	sw	t0,0(sp)
+ 194:	00512223          	sw	t0,4(sp)
+ 198:	00512423          	sw	t0,8(sp)
+ 19c:	00512623          	sw	t0,12(sp)
+ 1a0:	00611023          	sh	t1,0(sp)
+ 1a4:	00410113          	addi	sp,sp,4
+ 1a8:	006110a3          	sh	t1,1(sp)
+ 1ac:	00410113          	addi	sp,sp,4
+ 1b0:	00611123          	sh	t1,2(sp)
+ 1b4:	00410113          	addi	sp,sp,4
+ 1b8:	006111a3          	sh	t1,3(sp)
+ 1bc:	305f9073          	csrw	mtvec,t6
+ 1c0:	02c0006f          	j	1ec <test_end>
+
+000001c4 <_trap_handler>:
+ 1c4:	34102f73          	csrr	t5,mepc
+ 1c8:	004f0f13          	addi	t5,t5,4
+ 1cc:	341f1073          	csrw	mepc,t5
+ 1d0:	34302f73          	csrr	t5,mtval
+ 1d4:	003f7f13          	andi	t5,t5,3
+ 1d8:	01e0a023          	sw	t5,0(ra)
+ 1dc:	34202f73          	csrr	t5,mcause
+ 1e0:	01e0a223          	sw	t5,4(ra)
+ 1e4:	00808093          	addi	ra,ra,8
+ 1e8:	30200073          	mret
+
+000001ec <test_end>:
+ 1ec:	00002297          	auipc	t0,0x2
+ 1f0:	e2428293          	addi	t0,t0,-476 # 2010 <begin_signature>
+ 1f4:	10000337          	lui	t1,0x10000
+ 1f8:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 1fc:	00532023          	sw	t0,0(t1)
+ 200:	00002297          	auipc	t0,0x2
+ 204:	ec028293          	addi	t0,t0,-320 # 20c0 <end_signature>
+ 208:	10000337          	lui	t1,0x10000
+ 20c:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 210:	00532023          	sw	t0,0(t1)
+ 214:	00100293          	li	t0,1
+ 218:	10000337          	lui	t1,0x10000
+ 21c:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 220:	00532023          	sw	t0,0(t1)
+ 224:	00000013          	nop
+ 228:	00100193          	li	gp,1
+ 22c:	00000073          	ecall
+
+00000230 <end_testcode>:
+ 230:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_A1_data>:
+    2000:	b1c1                	j	1cc0 <fromhost+0xbc0>
+    2002:	91a1                	srli	a1,a1,0x28
+
+00002004 <test_A2_data>:
+    2004:	f202                	fsw	ft0,36(sp)
+    2006:	d2e2                	sw	s8,100(sp)
+	...
+
+00002010 <begin_signature>:
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+
+00002020 <test_A1_res_exc>:
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+
+00002038 <test_A2_res>:
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+
+00002058 <test_A2_res_exc>:
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_B1_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+
+00002088 <test_B1_res_exc>:
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_B2_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+
+000020b0 <test_B2_res_exc>:
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+
+000020c0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf
new file mode 100644
index 0000000..5e2bde1
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.bin
new file mode 100644
index 0000000..4bbf5d0
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.objdump
new file mode 100644
index 0000000..4c6631c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf.objdump
@@ -0,0 +1,239 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-NOP-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002097          	auipc	ra,0x2
+  84:	f8008093          	addi	ra,ra,-128 # 2000 <begin_signature>
+  88:	00200113          	li	sp,2
+  8c:	00300193          	li	gp,3
+  90:	00400213          	li	tp,4
+  94:	00500293          	li	t0,5
+  98:	00600313          	li	t1,6
+  9c:	00700393          	li	t2,7
+  a0:	00800413          	li	s0,8
+  a4:	00900493          	li	s1,9
+  a8:	00a00513          	li	a0,10
+  ac:	00b00593          	li	a1,11
+  b0:	00c00613          	li	a2,12
+  b4:	00d00693          	li	a3,13
+  b8:	00e00713          	li	a4,14
+  bc:	00f00793          	li	a5,15
+  c0:	01000813          	li	a6,16
+  c4:	01100893          	li	a7,17
+  c8:	01200913          	li	s2,18
+  cc:	01300993          	li	s3,19
+  d0:	01400a13          	li	s4,20
+  d4:	01500a93          	li	s5,21
+  d8:	01600b13          	li	s6,22
+  dc:	01700b93          	li	s7,23
+  e0:	01800c13          	li	s8,24
+  e4:	01900c93          	li	s9,25
+  e8:	01a00d13          	li	s10,26
+  ec:	01b00d93          	li	s11,27
+  f0:	01c00e13          	li	t3,28
+  f4:	01d00e93          	li	t4,29
+  f8:	01e00f13          	li	t5,30
+  fc:	01f00f93          	li	t6,31
+ 100:	00000013          	nop
+ 104:	00000013          	nop
+ 108:	00000013          	nop
+ 10c:	00000013          	nop
+ 110:	00000013          	nop
+ 114:	00000013          	nop
+ 118:	0000a023          	sw	zero,0(ra)
+ 11c:	0020a223          	sw	sp,4(ra)
+ 120:	0030a423          	sw	gp,8(ra)
+ 124:	0040a623          	sw	tp,12(ra)
+ 128:	0050a823          	sw	t0,16(ra)
+ 12c:	0060aa23          	sw	t1,20(ra)
+ 130:	0070ac23          	sw	t2,24(ra)
+ 134:	0080ae23          	sw	s0,28(ra)
+ 138:	0290a023          	sw	s1,32(ra)
+ 13c:	02a0a223          	sw	a0,36(ra)
+ 140:	02b0a423          	sw	a1,40(ra)
+ 144:	02c0a623          	sw	a2,44(ra)
+ 148:	02d0a823          	sw	a3,48(ra)
+ 14c:	02e0aa23          	sw	a4,52(ra)
+ 150:	02f0ac23          	sw	a5,56(ra)
+ 154:	0300ae23          	sw	a6,60(ra)
+ 158:	0510a023          	sw	a7,64(ra)
+ 15c:	0520a223          	sw	s2,68(ra)
+ 160:	0530a423          	sw	s3,72(ra)
+ 164:	0540a623          	sw	s4,76(ra)
+ 168:	0550a823          	sw	s5,80(ra)
+ 16c:	0560aa23          	sw	s6,84(ra)
+ 170:	0570ac23          	sw	s7,88(ra)
+ 174:	0580ae23          	sw	s8,92(ra)
+ 178:	0790a023          	sw	s9,96(ra)
+ 17c:	07a0a223          	sw	s10,100(ra)
+ 180:	07b0a423          	sw	s11,104(ra)
+ 184:	07c0a623          	sw	t3,108(ra)
+ 188:	07d0a823          	sw	t4,112(ra)
+ 18c:	07e0aa23          	sw	t5,116(ra)
+ 190:	07f0ac23          	sw	t6,120(ra)
+ 194:	00002197          	auipc	gp,0x2
+ 198:	ee818193          	addi	gp,gp,-280 # 207c <test_A2_res>
+ 19c:	00000417          	auipc	s0,0x0
+ 1a0:	00000013          	nop
+ 1a4:	00000013          	nop
+ 1a8:	00000013          	nop
+ 1ac:	00000013          	nop
+ 1b0:	00000013          	nop
+ 1b4:	00000497          	auipc	s1,0x0
+ 1b8:	408484b3          	sub	s1,s1,s0
+ 1bc:	0091a023          	sw	s1,0(gp)
+ 1c0:	00002297          	auipc	t0,0x2
+ 1c4:	e4028293          	addi	t0,t0,-448 # 2000 <begin_signature>
+ 1c8:	10000337          	lui	t1,0x10000
+ 1cc:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 1d0:	00532023          	sw	t0,0(t1)
+ 1d4:	00002297          	auipc	t0,0x2
+ 1d8:	eac28293          	addi	t0,t0,-340 # 2080 <end_signature>
+ 1dc:	10000337          	lui	t1,0x10000
+ 1e0:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 1e4:	00532023          	sw	t0,0(t1)
+ 1e8:	00100293          	li	t0,1
+ 1ec:	10000337          	lui	t1,0x10000
+ 1f0:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 1f4:	00532023          	sw	t0,0(t1)
+ 1f8:	00000013          	nop
+ 1fc:	00100193          	li	gp,1
+ 200:	00000073          	ecall
+
+00000204 <end_testcode>:
+ 204:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+
+0000207c <test_A2_res>:
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf
new file mode 100644
index 0000000..0dc2259
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.bin
new file mode 100644
index 0000000..a732dc0
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.objdump
new file mode 100644
index 0000000..96cac74
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-OR-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010fe033          	or	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff60b3          	or	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00eee133          	or	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de61b3          	or	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cde233          	or	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd62b3          	or	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00ace333          	or	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c63b3          	or	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008be433          	or	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b64b3          	or	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006ae533          	or	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a65b3          	or	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	0049e633          	or	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003966b3          	or	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	0028e733          	or	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001867b3          	or	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	0007e833          	or	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f768b3          	or	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e6e933          	or	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d669b3          	or	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c5ea33          	or	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b56ab3          	or	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a4eb33          	or	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01946bb3          	or	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	0183ec33          	or	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01736cb3          	or	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	0162ed33          	or	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01526db3          	or	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	0141ee33          	or	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01316eb3          	or	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	0120ef33          	or	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01106fb3          	or	t6,zero,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf
new file mode 100644
index 0000000..bfeea17
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.bin
new file mode 100644
index 0000000..b903be2
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.objdump
new file mode 100644
index 0000000..87cc3bb
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-ORI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000fe013          	ori	zero,t6,0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f6093          	ori	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffee113          	ori	sp,t4,-1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e6193          	ori	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800de213          	ori	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d6293          	ori	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800ce313          	ori	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c6393          	ori	t2,s8,1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800be413          	ori	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b6493          	ori	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800ae513          	ori	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a6593          	ori	a1,s4,0
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff9e613          	ori	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff96693          	ori	a3,s2,-1
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0018e713          	ori	a4,a7,1
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00086793          	ori	a5,a6,0
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007e813          	ori	a6,a5,0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80176893          	ori	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff6e913          	ori	s2,a3,-1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80066993          	ori	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	8005ea13          	ori	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80056a93          	ori	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	8004eb13          	ori	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00146b93          	ori	s7,s0,1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	8003ec13          	ori	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80036c93          	ori	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	8002ed13          	ori	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00026d93          	ori	s11,tp,0
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff1ee13          	ori	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff16e93          	ori	t4,sp,-1
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0010ef13          	ori	t5,ra,1
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00006f93          	ori	t6,zero,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf
new file mode 100644
index 0000000..a2f1e2f
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.bin
new file mode 100644
index 0000000..a874744
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.objdump
new file mode 100644
index 0000000..6b67a4a
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf.objdump
@@ -0,0 +1,275 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-RF_size-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002817          	auipc	a6,0x2
+  84:	f8080813          	addi	a6,a6,-128 # 2000 <begin_signature>
+  88:	42727037          	lui	zero,0x42727
+  8c:	e6f00013          	li	zero,-401
+  90:	563330b7          	lui	ra,0x56333
+  94:	24908093          	addi	ra,ra,585 # 56333249 <_end+0x56331045>
+  98:	2d562137          	lui	sp,0x2d562
+  9c:	05210113          	addi	sp,sp,82 # 2d562052 <_end+0x2d55fe4e>
+  a0:	526971b7          	lui	gp,0x52697
+  a4:	36318193          	addi	gp,gp,867 # 52697363 <_end+0x5269515f>
+  a8:	736b8237          	lui	tp,0x736b8
+  ac:	92020213          	addi	tp,tp,-1760 # 736b7920 <_end+0x736b571c>
+  b0:	737462b7          	lui	t0,0x73746
+  b4:	57228293          	addi	t0,t0,1394 # 73746572 <_end+0x7374436e>
+  b8:	6e205337          	lui	t1,0x6e205
+  bc:	e6f30313          	addi	t1,t1,-401 # 6e204e6f <_end+0x6e202c6b>
+  c0:	4d6973b7          	lui	t2,0x4d697
+  c4:	c6138393          	addi	t2,t2,-927 # 4d696c61 <_end+0x4d694a5d>
+  c8:	6f646437          	lui	s0,0x6f646
+  cc:	17340413          	addi	s0,s0,371 # 6f646173 <_end+0x6f643f6f>
+  d0:	6b7944b7          	lui	s1,0x6b794
+  d4:	06348493          	addi	s1,s1,99 # 6b794063 <_end+0x6b791e5f>
+  d8:	74657537          	lui	a0,0x74657
+  dc:	27350513          	addi	a0,a0,627 # 74657273 <_end+0x7465506f>
+  e0:	286e75b7          	lui	a1,0x286e7
+  e4:	f7358593          	addi	a1,a1,-141 # 286e6f73 <_end+0x286e4d6f>
+  e8:	656b2637          	lui	a2,0x656b2
+  ec:	04860613          	addi	a2,a2,72 # 656b2048 <_end+0x656afe44>
+  f0:	205266b7          	lui	a3,0x20526
+  f4:	16468693          	addi	a3,a3,356 # 20526164 <_end+0x20523f60>
+  f8:	6f6d3737          	lui	a4,0x6f6d3
+  fc:	92c70713          	addi	a4,a4,-1748 # 6f6d292c <_end+0x6f6d0728>
+ 100:	697037b7          	lui	a5,0x69703
+ 104:	e6378793          	addi	a5,a5,-413 # 69702e63 <_end+0x69700c5f>
+ 108:	00082023          	sw	zero,0(a6)
+ 10c:	00182223          	sw	ra,4(a6)
+ 110:	00282423          	sw	sp,8(a6)
+ 114:	00382623          	sw	gp,12(a6)
+ 118:	00482823          	sw	tp,16(a6)
+ 11c:	00582a23          	sw	t0,20(a6)
+ 120:	00682c23          	sw	t1,24(a6)
+ 124:	00782e23          	sw	t2,28(a6)
+ 128:	02882023          	sw	s0,32(a6)
+ 12c:	02982223          	sw	s1,36(a6)
+ 130:	02a82423          	sw	a0,40(a6)
+ 134:	02b82623          	sw	a1,44(a6)
+ 138:	02c82823          	sw	a2,48(a6)
+ 13c:	02d82a23          	sw	a3,52(a6)
+ 140:	02e82c23          	sw	a4,56(a6)
+ 144:	02f82e23          	sw	a5,60(a6)
+ 148:	00002217          	auipc	tp,0x2
+ 14c:	ef820213          	addi	tp,tp,-264 # 2040 <test_A2_res>
+ 150:	636f6837          	lui	a6,0x636f6
+ 154:	46180813          	addi	a6,a6,1121 # 636f6461 <_end+0x636f425d>
+ 158:	6a6578b7          	lui	a7,0x6a657
+ 15c:	b4088893          	addi	a7,a7,-1216 # 6a656b40 <_end+0x6a65493c>
+ 160:	20287937          	lui	s2,0x20287
+ 164:	86190913          	addi	s2,s2,-1951 # 20286861 <_end+0x2028465d>
+ 168:	616a69b7          	lui	s3,0x616a6
+ 16c:	56b98993          	addi	s3,s3,1387 # 616a656b <_end+0x616a4367>
+ 170:	61766a37          	lui	s4,0x61766
+ 174:	520a0a13          	addi	s4,s4,1312 # 61766520 <_end+0x6176431c>
+ 178:	2e205ab7          	lui	s5,0x2e205
+ 17c:	c65a8a93          	addi	s5,s5,-923 # 2e204c65 <_end+0x2e202a61>
+ 180:	636f7b37          	lui	s6,0x636f7
+ 184:	d29b0b13          	addi	s6,s6,-727 # 636f6d29 <_end+0x636f4b25>
+ 188:	73697bb7          	lui	s7,0x73697
+ 18c:	02eb8b93          	addi	s7,s7,46 # 7369702e <_end+0x73694e2a>
+ 190:	66208c37          	lui	s8,0x66208
+ 194:	96fc0c13          	addi	s8,s8,-1681 # 6620796f <_end+0x6620576b>
+ 198:	67652cb7          	lui	s9,0x67652
+ 19c:	069c8c93          	addi	s9,s9,105 # 67652069 <_end+0x6764fe65>
+ 1a0:	65737d37          	lui	s10,0x65737
+ 1a4:	361d0d13          	addi	s10,s10,865 # 65737361 <_end+0x6573515d>
+ 1a8:	75732db7          	lui	s11,0x75732
+ 1ac:	06dd8d93          	addi	s11,s11,109 # 7573206d <_end+0x7572fe69>
+ 1b0:	3a291e37          	lui	t3,0x3a291
+ 1b4:	d0ae0e13          	addi	t3,t3,-758 # 3a290d0a <_end+0x3a28eb06>
+ 1b8:	68697eb7          	lui	t4,0x68697
+ 1bc:	320e8e93          	addi	t4,t4,800 # 68697320 <_end+0x6869511c>
+ 1c0:	61642f37          	lui	t5,0x61642
+ 1c4:	074f0f13          	addi	t5,t5,116 # 61642074 <_end+0x6163fe70>
+ 1c8:	75207fb7          	lui	t6,0x75207
+ 1cc:	265f8f93          	addi	t6,t6,613 # 75207265 <_end+0x75205061>
+ 1d0:	01022023          	sw	a6,0(tp) # 0 <_start>
+ 1d4:	01122223          	sw	a7,4(tp) # 4 <trap_vector>
+ 1d8:	01222423          	sw	s2,8(tp) # 8 <trap_vector+0x4>
+ 1dc:	01322623          	sw	s3,12(tp) # c <trap_vector+0x8>
+ 1e0:	01422823          	sw	s4,16(tp) # 10 <trap_vector+0xc>
+ 1e4:	01522a23          	sw	s5,20(tp) # 14 <trap_vector+0x10>
+ 1e8:	01622c23          	sw	s6,24(tp) # 18 <trap_vector+0x14>
+ 1ec:	01722e23          	sw	s7,28(tp) # 1c <trap_vector+0x18>
+ 1f0:	03822023          	sw	s8,32(tp) # 20 <trap_vector+0x1c>
+ 1f4:	03922223          	sw	s9,36(tp) # 24 <trap_vector+0x20>
+ 1f8:	03a22423          	sw	s10,40(tp) # 28 <trap_vector+0x24>
+ 1fc:	03b22623          	sw	s11,44(tp) # 2c <trap_vector+0x28>
+ 200:	03c22823          	sw	t3,48(tp) # 30 <trap_vector+0x2c>
+ 204:	03d22a23          	sw	t4,52(tp) # 34 <trap_vector+0x30>
+ 208:	03e22c23          	sw	t5,56(tp) # 38 <trap_vector+0x34>
+ 20c:	03f22e23          	sw	t6,60(tp) # 3c <handle_exception>
+ 210:	00002217          	auipc	tp,0x2
+ 214:	e7020213          	addi	tp,tp,-400 # 2080 <test_A3_res>
+ 218:	00022023          	sw	zero,0(tp) # 0 <_start>
+ 21c:	00122223          	sw	ra,4(tp) # 4 <trap_vector>
+ 220:	00222423          	sw	sp,8(tp) # 8 <trap_vector+0x4>
+ 224:	00322623          	sw	gp,12(tp) # c <trap_vector+0x8>
+ 228:	00002297          	auipc	t0,0x2
+ 22c:	dd828293          	addi	t0,t0,-552 # 2000 <begin_signature>
+ 230:	10000337          	lui	t1,0x10000
+ 234:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 238:	00532023          	sw	t0,0(t1)
+ 23c:	00002297          	auipc	t0,0x2
+ 240:	e5428293          	addi	t0,t0,-428 # 2090 <end_signature>
+ 244:	10000337          	lui	t1,0x10000
+ 248:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 24c:	00532023          	sw	t0,0(t1)
+ 250:	00100293          	li	t0,1
+ 254:	10000337          	lui	t1,0x10000
+ 258:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 25c:	00532023          	sw	t0,0(t1)
+ 260:	00000013          	nop
+ 264:	00100193          	li	gp,1
+ 268:	00000073          	ecall
+
+0000026c <end_testcode>:
+ 26c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <test_A2_res>:
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <test_A3_res>:
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf
new file mode 100644
index 0000000..85ac614
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.bin
new file mode 100644
index 0000000..4bf0c82
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.objdump
new file mode 100644
index 0000000..8b49647
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf.objdump
@@ -0,0 +1,320 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-RF_width-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002817          	auipc	a6,0x2
+  84:	f8080813          	addi	a6,a6,-128 # 2000 <begin_signature>
+  88:	00100013          	li	zero,1
+  8c:	00100093          	li	ra,1
+  90:	00100113          	li	sp,1
+  94:	00100193          	li	gp,1
+  98:	00100213          	li	tp,1
+  9c:	00100293          	li	t0,1
+  a0:	00100313          	li	t1,1
+  a4:	00100393          	li	t2,1
+  a8:	00100413          	li	s0,1
+  ac:	00100493          	li	s1,1
+  b0:	00100513          	li	a0,1
+  b4:	00100593          	li	a1,1
+  b8:	00100613          	li	a2,1
+  bc:	00100693          	li	a3,1
+  c0:	00100713          	li	a4,1
+  c4:	00100793          	li	a5,1
+  c8:	01f09093          	slli	ra,ra,0x1f
+  cc:	0000c463          	bltz	ra,d4 <begin_testcode+0x54>
+  d0:	00000093          	li	ra,0
+  d4:	01f11113          	slli	sp,sp,0x1f
+  d8:	00014463          	bltz	sp,e0 <begin_testcode+0x60>
+  dc:	00000113          	li	sp,0
+  e0:	01f19193          	slli	gp,gp,0x1f
+  e4:	0001c463          	bltz	gp,ec <begin_testcode+0x6c>
+  e8:	00000193          	li	gp,0
+  ec:	01f21213          	slli	tp,tp,0x1f
+  f0:	00024463          	bltz	tp,f8 <begin_testcode+0x78>
+  f4:	00000213          	li	tp,0
+  f8:	01f29293          	slli	t0,t0,0x1f
+  fc:	0002c463          	bltz	t0,104 <begin_testcode+0x84>
+ 100:	00000293          	li	t0,0
+ 104:	01f31313          	slli	t1,t1,0x1f
+ 108:	00034463          	bltz	t1,110 <begin_testcode+0x90>
+ 10c:	00000313          	li	t1,0
+ 110:	01f39393          	slli	t2,t2,0x1f
+ 114:	0003c463          	bltz	t2,11c <begin_testcode+0x9c>
+ 118:	00000393          	li	t2,0
+ 11c:	01f41413          	slli	s0,s0,0x1f
+ 120:	00044463          	bltz	s0,128 <begin_testcode+0xa8>
+ 124:	00000413          	li	s0,0
+ 128:	01f49493          	slli	s1,s1,0x1f
+ 12c:	0004c463          	bltz	s1,134 <begin_testcode+0xb4>
+ 130:	00000493          	li	s1,0
+ 134:	01f51513          	slli	a0,a0,0x1f
+ 138:	00054463          	bltz	a0,140 <begin_testcode+0xc0>
+ 13c:	00000513          	li	a0,0
+ 140:	01f59593          	slli	a1,a1,0x1f
+ 144:	0005c463          	bltz	a1,14c <begin_testcode+0xcc>
+ 148:	00000593          	li	a1,0
+ 14c:	01f61613          	slli	a2,a2,0x1f
+ 150:	00064463          	bltz	a2,158 <begin_testcode+0xd8>
+ 154:	00000613          	li	a2,0
+ 158:	01f69693          	slli	a3,a3,0x1f
+ 15c:	0006c463          	bltz	a3,164 <begin_testcode+0xe4>
+ 160:	00000693          	li	a3,0
+ 164:	01f71713          	slli	a4,a4,0x1f
+ 168:	00074463          	bltz	a4,170 <begin_testcode+0xf0>
+ 16c:	00000713          	li	a4,0
+ 170:	01f79793          	slli	a5,a5,0x1f
+ 174:	0007c463          	bltz	a5,17c <begin_testcode+0xfc>
+ 178:	00000793          	li	a5,0
+ 17c:	00082023          	sw	zero,0(a6)
+ 180:	00182223          	sw	ra,4(a6)
+ 184:	00282423          	sw	sp,8(a6)
+ 188:	00382623          	sw	gp,12(a6)
+ 18c:	00482823          	sw	tp,16(a6)
+ 190:	00582a23          	sw	t0,20(a6)
+ 194:	00682c23          	sw	t1,24(a6)
+ 198:	00782e23          	sw	t2,28(a6)
+ 19c:	02882023          	sw	s0,32(a6)
+ 1a0:	02982223          	sw	s1,36(a6)
+ 1a4:	02a82423          	sw	a0,40(a6)
+ 1a8:	02b82623          	sw	a1,44(a6)
+ 1ac:	02c82823          	sw	a2,48(a6)
+ 1b0:	02d82a23          	sw	a3,52(a6)
+ 1b4:	02e82c23          	sw	a4,56(a6)
+ 1b8:	02f82e23          	sw	a5,60(a6)
+ 1bc:	00002097          	auipc	ra,0x2
+ 1c0:	e8408093          	addi	ra,ra,-380 # 2040 <test_A2_res>
+ 1c4:	00100813          	li	a6,1
+ 1c8:	00100893          	li	a7,1
+ 1cc:	00100913          	li	s2,1
+ 1d0:	00100993          	li	s3,1
+ 1d4:	00100a13          	li	s4,1
+ 1d8:	00100a93          	li	s5,1
+ 1dc:	00100b13          	li	s6,1
+ 1e0:	00100b93          	li	s7,1
+ 1e4:	00100c13          	li	s8,1
+ 1e8:	00100c93          	li	s9,1
+ 1ec:	00100d13          	li	s10,1
+ 1f0:	00100d93          	li	s11,1
+ 1f4:	00100e13          	li	t3,1
+ 1f8:	00100e93          	li	t4,1
+ 1fc:	00100f13          	li	t5,1
+ 200:	00100f93          	li	t6,1
+ 204:	01f81813          	slli	a6,a6,0x1f
+ 208:	00084463          	bltz	a6,210 <begin_testcode+0x190>
+ 20c:	00000813          	li	a6,0
+ 210:	01f89893          	slli	a7,a7,0x1f
+ 214:	0008c463          	bltz	a7,21c <begin_testcode+0x19c>
+ 218:	00000893          	li	a7,0
+ 21c:	01f91913          	slli	s2,s2,0x1f
+ 220:	00094463          	bltz	s2,228 <begin_testcode+0x1a8>
+ 224:	00000913          	li	s2,0
+ 228:	01f99993          	slli	s3,s3,0x1f
+ 22c:	0009c463          	bltz	s3,234 <begin_testcode+0x1b4>
+ 230:	00000993          	li	s3,0
+ 234:	01fa1a13          	slli	s4,s4,0x1f
+ 238:	000a4463          	bltz	s4,240 <begin_testcode+0x1c0>
+ 23c:	00000a13          	li	s4,0
+ 240:	01fa9a93          	slli	s5,s5,0x1f
+ 244:	000ac463          	bltz	s5,24c <begin_testcode+0x1cc>
+ 248:	00000a93          	li	s5,0
+ 24c:	01fb1b13          	slli	s6,s6,0x1f
+ 250:	000b4463          	bltz	s6,258 <begin_testcode+0x1d8>
+ 254:	00000b13          	li	s6,0
+ 258:	01fb9b93          	slli	s7,s7,0x1f
+ 25c:	000bc463          	bltz	s7,264 <begin_testcode+0x1e4>
+ 260:	00000b93          	li	s7,0
+ 264:	01fc1c13          	slli	s8,s8,0x1f
+ 268:	000c4463          	bltz	s8,270 <begin_testcode+0x1f0>
+ 26c:	00000c13          	li	s8,0
+ 270:	01fc9c93          	slli	s9,s9,0x1f
+ 274:	000cc463          	bltz	s9,27c <begin_testcode+0x1fc>
+ 278:	00000c93          	li	s9,0
+ 27c:	01fd1d13          	slli	s10,s10,0x1f
+ 280:	000d4463          	bltz	s10,288 <begin_testcode+0x208>
+ 284:	00000d13          	li	s10,0
+ 288:	01fd9d93          	slli	s11,s11,0x1f
+ 28c:	000dc463          	bltz	s11,294 <begin_testcode+0x214>
+ 290:	00000d93          	li	s11,0
+ 294:	01fe1e13          	slli	t3,t3,0x1f
+ 298:	000e4463          	bltz	t3,2a0 <begin_testcode+0x220>
+ 29c:	00000e13          	li	t3,0
+ 2a0:	01fe9e93          	slli	t4,t4,0x1f
+ 2a4:	000ec463          	bltz	t4,2ac <begin_testcode+0x22c>
+ 2a8:	00000e93          	li	t4,0
+ 2ac:	01ff1f13          	slli	t5,t5,0x1f
+ 2b0:	000f4463          	bltz	t5,2b8 <begin_testcode+0x238>
+ 2b4:	00000f13          	li	t5,0
+ 2b8:	01ff9f93          	slli	t6,t6,0x1f
+ 2bc:	000fc463          	bltz	t6,2c4 <begin_testcode+0x244>
+ 2c0:	00000f93          	li	t6,0
+ 2c4:	0100a023          	sw	a6,0(ra)
+ 2c8:	0110a223          	sw	a7,4(ra)
+ 2cc:	0120a423          	sw	s2,8(ra)
+ 2d0:	0130a623          	sw	s3,12(ra)
+ 2d4:	0140a823          	sw	s4,16(ra)
+ 2d8:	0150aa23          	sw	s5,20(ra)
+ 2dc:	0160ac23          	sw	s6,24(ra)
+ 2e0:	0170ae23          	sw	s7,28(ra)
+ 2e4:	0380a023          	sw	s8,32(ra)
+ 2e8:	0390a223          	sw	s9,36(ra)
+ 2ec:	03a0a423          	sw	s10,40(ra)
+ 2f0:	03b0a623          	sw	s11,44(ra)
+ 2f4:	03c0a823          	sw	t3,48(ra)
+ 2f8:	03d0aa23          	sw	t4,52(ra)
+ 2fc:	03e0ac23          	sw	t5,56(ra)
+ 300:	03f0ae23          	sw	t6,60(ra)
+ 304:	00002297          	auipc	t0,0x2
+ 308:	cfc28293          	addi	t0,t0,-772 # 2000 <begin_signature>
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00002297          	auipc	t0,0x2
+ 31c:	d6828293          	addi	t0,t0,-664 # 2080 <end_signature>
+ 320:	10000337          	lui	t1,0x10000
+ 324:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 328:	00532023          	sw	t0,0(t1)
+ 32c:	00100293          	li	t0,1
+ 330:	10000337          	lui	t1,0x10000
+ 334:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 338:	00532023          	sw	t0,0(t1)
+ 33c:	00000013          	nop
+ 340:	00100193          	li	gp,1
+ 344:	00000073          	ecall
+
+00000348 <end_testcode>:
+ 348:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <test_A2_res>:
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+
+00002080 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf
new file mode 100644
index 0000000..7b71eee
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.bin
new file mode 100644
index 0000000..8dfa1a7
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.objdump
new file mode 100644
index 0000000..443530c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf.objdump
@@ -0,0 +1,191 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-RF_x0-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002f97          	auipc	t6,0x2
+  84:	f90f8f93          	addi	t6,t6,-112 # 2010 <begin_signature>
+  88:	abcde037          	lui	zero,0xabcde
+  8c:	00100013          	li	zero,1
+  90:	7f006013          	ori	zero,zero,2032
+  94:	53f07013          	andi	zero,zero,1343
+  98:	80304013          	xori	zero,zero,-2045
+  9c:	00501013          	slli	zero,zero,0x5
+  a0:	40205013          	srai	zero,zero,0x2
+  a4:	00405013          	srli	zero,zero,0x4
+  a8:	000fa023          	sw	zero,0(t6)
+  ac:	00002f97          	auipc	t6,0x2
+  b0:	f68f8f93          	addi	t6,t6,-152 # 2014 <test_A2_res>
+  b4:	00100093          	li	ra,1
+  b8:	7f000113          	li	sp,2032
+  bc:	53f00193          	li	gp,1343
+  c0:	80300213          	li	tp,-2045
+  c4:	00500293          	li	t0,5
+  c8:	00200313          	li	t1,2
+  cc:	00400393          	li	t2,4
+  d0:	01800413          	li	s0,24
+  d4:	abcde017          	auipc	zero,0xabcde
+  d8:	00100033          	add	zero,zero,ra
+  dc:	00206033          	or	zero,zero,sp
+  e0:	00307033          	and	zero,zero,gp
+  e4:	00404033          	xor	zero,zero,tp
+  e8:	00501033          	sll	zero,zero,t0
+  ec:	40605033          	sra	zero,zero,t1
+  f0:	00705033          	srl	zero,zero,t2
+  f4:	40800033          	neg	zero,s0
+  f8:	000fa023          	sw	zero,0(t6)
+  fc:	00002f97          	auipc	t6,0x2
+ 100:	f1cf8f93          	addi	t6,t6,-228 # 2018 <test_A3_res>
+ 104:	00100093          	li	ra,1
+ 108:	00200113          	li	sp,2
+ 10c:	0020a033          	slt	zero,ra,sp
+ 110:	000fa023          	sw	zero,0(t6)
+ 114:	0020b033          	sltu	zero,ra,sp
+ 118:	000fa223          	sw	zero,4(t6)
+ 11c:	0020a013          	slti	zero,ra,2
+ 120:	000fa423          	sw	zero,8(t6)
+ 124:	0020b013          	sltiu	zero,ra,2
+ 128:	000fa623          	sw	zero,12(t6)
+ 12c:	00002f97          	auipc	t6,0x2
+ 130:	efcf8f93          	addi	t6,t6,-260 # 2028 <test_A4_res>
+ 134:	0040006f          	j	138 <begin_testcode+0xb8>
+ 138:	000fa023          	sw	zero,0(t6)
+ 13c:	00000097          	auipc	ra,0x0
+ 140:	00c08093          	addi	ra,ra,12 # 148 <begin_testcode+0xc8>
+ 144:	00008067          	ret
+ 148:	000fa223          	sw	zero,4(t6)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	eb408093          	addi	ra,ra,-332 # 2000 <test_A5_data>
+ 154:	00002f97          	auipc	t6,0x2
+ 158:	edcf8f93          	addi	t6,t6,-292 # 2030 <test_A5_res>
+ 15c:	0000a003          	lw	zero,0(ra)
+ 160:	000fa023          	sw	zero,0(t6)
+ 164:	00009003          	lh	zero,0(ra)
+ 168:	000fa223          	sw	zero,4(t6)
+ 16c:	00008003          	lb	zero,0(ra)
+ 170:	000fa423          	sw	zero,8(t6)
+ 174:	0000c003          	lbu	zero,0(ra)
+ 178:	000fa623          	sw	zero,12(t6)
+ 17c:	00002297          	auipc	t0,0x2
+ 180:	e9428293          	addi	t0,t0,-364 # 2010 <begin_signature>
+ 184:	10000337          	lui	t1,0x10000
+ 188:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 18c:	00532023          	sw	t0,0(t1)
+ 190:	00002297          	auipc	t0,0x2
+ 194:	eb028293          	addi	t0,t0,-336 # 2040 <end_signature>
+ 198:	10000337          	lui	t1,0x10000
+ 19c:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 1a0:	00532023          	sw	t0,0(t1)
+ 1a4:	00100293          	li	t0,1
+ 1a8:	10000337          	lui	t1,0x10000
+ 1ac:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 1b0:	00532023          	sw	t0,0(t1)
+ 1b4:	00000013          	nop
+ 1b8:	00100193          	li	gp,1
+ 1bc:	00000073          	ecall
+
+000001c0 <end_testcode>:
+ 1c0:	c0001073          	unimp
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <test_A5_data>:
+    2000:	42524e4f          	fnmadd.d	ft8,ft4,ft5,fs0,rmm
+	...
+
+00002010 <begin_signature>:
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_A2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_A3_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_A4_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+
+00002030 <test_A5_res>:
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf
new file mode 100644
index 0000000..936b695
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.bin
new file mode 100644
index 0000000..5e514b5
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.objdump
new file mode 100644
index 0000000..d9a4170
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf.objdump
@@ -0,0 +1,331 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SB-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8428293          	addi	t0,t0,-124 # 2004 <test_1_res>
+  88:	00028023          	sb	zero,0(t0)
+  8c:	fff00813          	li	a6,-1
+  90:	00028f93          	mv	t6,t0
+  94:	010f8023          	sb	a6,0(t6)
+  98:	fe028f23          	sb	zero,-2(t0)
+  9c:	00100793          	li	a5,1
+  a0:	00028f13          	mv	t5,t0
+  a4:	feff0f23          	sb	a5,-2(t5)
+  a8:	000281a3          	sb	zero,3(t0)
+  ac:	00000713          	li	a4,0
+  b0:	00028e93          	mv	t4,t0
+  b4:	00ee81a3          	sb	a4,3(t4)
+  b8:	fe028e23          	sb	zero,-4(t0)
+  bc:	7ff00693          	li	a3,2047
+  c0:	00028e13          	mv	t3,t0
+  c4:	fede0e23          	sb	a3,-4(t3)
+  c8:	00028123          	sb	zero,2(t0)
+  cc:	00000613          	li	a2,0
+  d0:	00028d93          	mv	s11,t0
+  d4:	00cd8123          	sb	a2,2(s11)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f4008093          	addi	ra,ra,-192 # 2018 <test_2_res>
+  e0:	00008223          	sb	zero,4(ra)
+  e4:	000015b7          	lui	a1,0x1
+  e8:	80058593          	addi	a1,a1,-2048 # 800 <end_testcode+0x4dc>
+  ec:	00008d13          	mv	s10,ra
+  f0:	00bd0223          	sb	a1,4(s10)
+  f4:	fe008fa3          	sb	zero,-1(ra)
+  f8:	07654537          	lui	a0,0x7654
+  fc:	32150513          	addi	a0,a0,801 # 7654321 <_end+0x765211d>
+ 100:	00008c93          	mv	s9,ra
+ 104:	feac8fa3          	sb	a0,-1(s9)
+ 108:	000080a3          	sb	zero,1(ra)
+ 10c:	800004b7          	lui	s1,0x80000
+ 110:	fff48493          	addi	s1,s1,-1 # 7fffffff <_end+0x7fffddfb>
+ 114:	00008c13          	mv	s8,ra
+ 118:	009c00a3          	sb	s1,1(s8)
+ 11c:	00008023          	sb	zero,0(ra)
+ 120:	00100413          	li	s0,1
+ 124:	00008b93          	mv	s7,ra
+ 128:	008b8023          	sb	s0,0(s7)
+ 12c:	fe008f23          	sb	zero,-2(ra)
+ 130:	fff00393          	li	t2,-1
+ 134:	00008b13          	mv	s6,ra
+ 138:	fe7b0f23          	sb	t2,-2(s6)
+ 13c:	00002097          	auipc	ra,0x2
+ 140:	ef008093          	addi	ra,ra,-272 # 202c <test_3_res>
+ 144:	000081a3          	sb	zero,3(ra)
+ 148:	00001337          	lui	t1,0x1
+ 14c:	23430313          	addi	t1,t1,564 # 1234 <fromhost+0x134>
+ 150:	00008a93          	mv	s5,ra
+ 154:	006a81a3          	sb	t1,3(s5)
+ 158:	fe008e23          	sb	zero,-4(ra)
+ 15c:	800002b7          	lui	t0,0x80000
+ 160:	00008a13          	mv	s4,ra
+ 164:	fe5a0e23          	sb	t0,-4(s4)
+ 168:	00008123          	sb	zero,2(ra)
+ 16c:	fffff237          	lui	tp,0xfffff
+ 170:	dcc20213          	addi	tp,tp,-564 # ffffedcc <_end+0xffffcbc8>
+ 174:	00008993          	mv	s3,ra
+ 178:	00498123          	sb	tp,2(s3)
+ 17c:	00008223          	sb	zero,4(ra)
+ 180:	fff00193          	li	gp,-1
+ 184:	00008913          	mv	s2,ra
+ 188:	00390223          	sb	gp,4(s2)
+ 18c:	fe008fa3          	sb	zero,-1(ra)
+ 190:	80100113          	li	sp,-2047
+ 194:	00008893          	mv	a7,ra
+ 198:	fe288fa3          	sb	sp,-1(a7)
+ 19c:	00002117          	auipc	sp,0x2
+ 1a0:	ea410113          	addi	sp,sp,-348 # 2040 <test_4_res>
+ 1a4:	000100a3          	sb	zero,1(sp)
+ 1a8:	00000093          	li	ra,0
+ 1ac:	00010813          	mv	a6,sp
+ 1b0:	001800a3          	sb	ra,1(a6)
+ 1b4:	00010023          	sb	zero,0(sp)
+ 1b8:	fff00013          	li	zero,-1
+ 1bc:	00010793          	mv	a5,sp
+ 1c0:	00078023          	sb	zero,0(a5)
+ 1c4:	fe010f23          	sb	zero,-2(sp)
+ 1c8:	00100f93          	li	t6,1
+ 1cc:	00010713          	mv	a4,sp
+ 1d0:	fff70f23          	sb	t6,-2(a4)
+ 1d4:	000101a3          	sb	zero,3(sp)
+ 1d8:	00000f13          	li	t5,0
+ 1dc:	00010693          	mv	a3,sp
+ 1e0:	01e681a3          	sb	t5,3(a3)
+ 1e4:	fe010e23          	sb	zero,-4(sp)
+ 1e8:	7ff00e93          	li	t4,2047
+ 1ec:	00010613          	mv	a2,sp
+ 1f0:	ffd60e23          	sb	t4,-4(a2)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e6008093          	addi	ra,ra,-416 # 2054 <test_5_res>
+ 1fc:	00008123          	sb	zero,2(ra)
+ 200:	00000e13          	li	t3,0
+ 204:	00008593          	mv	a1,ra
+ 208:	01c58123          	sb	t3,2(a1)
+ 20c:	00008223          	sb	zero,4(ra)
+ 210:	00001db7          	lui	s11,0x1
+ 214:	800d8d93          	addi	s11,s11,-2048 # 800 <end_testcode+0x4dc>
+ 218:	00008513          	mv	a0,ra
+ 21c:	01b50223          	sb	s11,4(a0)
+ 220:	fe008fa3          	sb	zero,-1(ra)
+ 224:	07654d37          	lui	s10,0x7654
+ 228:	321d0d13          	addi	s10,s10,801 # 7654321 <_end+0x765211d>
+ 22c:	00008493          	mv	s1,ra
+ 230:	ffa48fa3          	sb	s10,-1(s1)
+ 234:	000080a3          	sb	zero,1(ra)
+ 238:	80000cb7          	lui	s9,0x80000
+ 23c:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 240:	00008413          	mv	s0,ra
+ 244:	019400a3          	sb	s9,1(s0)
+ 248:	00008023          	sb	zero,0(ra)
+ 24c:	00100c13          	li	s8,1
+ 250:	00008393          	mv	t2,ra
+ 254:	01838023          	sb	s8,0(t2)
+ 258:	00002097          	auipc	ra,0x2
+ 25c:	e1008093          	addi	ra,ra,-496 # 2068 <test_6_res>
+ 260:	fe008f23          	sb	zero,-2(ra)
+ 264:	fff00b93          	li	s7,-1
+ 268:	00008313          	mv	t1,ra
+ 26c:	ff730f23          	sb	s7,-2(t1)
+ 270:	000081a3          	sb	zero,3(ra)
+ 274:	00001b37          	lui	s6,0x1
+ 278:	234b0b13          	addi	s6,s6,564 # 1234 <fromhost+0x134>
+ 27c:	00008293          	mv	t0,ra
+ 280:	016281a3          	sb	s6,3(t0) # 80000003 <_end+0x7fffddff>
+ 284:	fe008e23          	sb	zero,-4(ra)
+ 288:	80000ab7          	lui	s5,0x80000
+ 28c:	00008213          	mv	tp,ra
+ 290:	ff520e23          	sb	s5,-4(tp) # fffffffc <_end+0xffffddf8>
+ 294:	00008123          	sb	zero,2(ra)
+ 298:	fffffa37          	lui	s4,0xfffff
+ 29c:	dcca0a13          	addi	s4,s4,-564 # ffffedcc <_end+0xffffcbc8>
+ 2a0:	00008193          	mv	gp,ra
+ 2a4:	01418123          	sb	s4,2(gp)
+ 2a8:	00008223          	sb	zero,4(ra)
+ 2ac:	fff00993          	li	s3,-1
+ 2b0:	00008113          	mv	sp,ra
+ 2b4:	01310223          	sb	s3,4(sp)
+ 2b8:	00002117          	auipc	sp,0x2
+ 2bc:	dc410113          	addi	sp,sp,-572 # 207c <test_7_res>
+ 2c0:	fe010fa3          	sb	zero,-1(sp)
+ 2c4:	80100913          	li	s2,-2047
+ 2c8:	00010093          	mv	ra,sp
+ 2cc:	ff208fa3          	sb	s2,-1(ra)
+ 2d0:	000100a3          	sb	zero,1(sp)
+ 2d4:	00000893          	li	a7,0
+ 2d8:	00010093          	mv	ra,sp
+ 2dc:	011080a3          	sb	a7,1(ra)
+ 2e0:	00002297          	auipc	t0,0x2
+ 2e4:	d2028293          	addi	t0,t0,-736 # 2000 <begin_signature>
+ 2e8:	10000337          	lui	t1,0x10000
+ 2ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2f0:	00532023          	sw	t0,0(t1)
+ 2f4:	00002297          	auipc	t0,0x2
+ 2f8:	d9c28293          	addi	t0,t0,-612 # 2090 <end_signature>
+ 2fc:	10000337          	lui	t1,0x10000
+ 300:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 304:	00532023          	sw	t0,0(t1)
+ 308:	00100293          	li	t0,1
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00000013          	nop
+ 31c:	00100193          	li	gp,1
+ 320:	00000073          	ecall
+
+00000324 <end_testcode>:
+ 324:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+
+00002004 <test_1_res>:
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_2_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+
+0000202c <test_3_res>:
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <test_4_res>:
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+
+00002054 <test_5_res>:
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+
+00002068 <test_6_res>:
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+
+0000207c <test_7_res>:
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf
new file mode 100644
index 0000000..c9f2dd9
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.bin
new file mode 100644
index 0000000..857881b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.objdump
new file mode 100644
index 0000000..534c070
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf.objdump
@@ -0,0 +1,331 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SH-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8428293          	addi	t0,t0,-124 # 2004 <test_1_res>
+  88:	00029023          	sh	zero,0(t0)
+  8c:	fff00813          	li	a6,-1
+  90:	00028f93          	mv	t6,t0
+  94:	010f9023          	sh	a6,0(t6)
+  98:	fe029f23          	sh	zero,-2(t0)
+  9c:	00100793          	li	a5,1
+  a0:	00028f13          	mv	t5,t0
+  a4:	feff1f23          	sh	a5,-2(t5)
+  a8:	00029123          	sh	zero,2(t0)
+  ac:	00000713          	li	a4,0
+  b0:	00028e93          	mv	t4,t0
+  b4:	00ee9123          	sh	a4,2(t4)
+  b8:	fe029e23          	sh	zero,-4(t0)
+  bc:	7ff00693          	li	a3,2047
+  c0:	00028e13          	mv	t3,t0
+  c4:	fede1e23          	sh	a3,-4(t3)
+  c8:	00029123          	sh	zero,2(t0)
+  cc:	00000613          	li	a2,0
+  d0:	00028d93          	mv	s11,t0
+  d4:	00cd9123          	sh	a2,2(s11)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f4008093          	addi	ra,ra,-192 # 2018 <test_2_res>
+  e0:	00009223          	sh	zero,4(ra)
+  e4:	000015b7          	lui	a1,0x1
+  e8:	80058593          	addi	a1,a1,-2048 # 800 <end_testcode+0x4dc>
+  ec:	00008d13          	mv	s10,ra
+  f0:	00bd1223          	sh	a1,4(s10)
+  f4:	00009023          	sh	zero,0(ra)
+  f8:	07654537          	lui	a0,0x7654
+  fc:	32150513          	addi	a0,a0,801 # 7654321 <_end+0x765211d>
+ 100:	00008c93          	mv	s9,ra
+ 104:	00ac9023          	sh	a0,0(s9)
+ 108:	00009023          	sh	zero,0(ra)
+ 10c:	800004b7          	lui	s1,0x80000
+ 110:	fff48493          	addi	s1,s1,-1 # 7fffffff <_end+0x7fffddfb>
+ 114:	00008c13          	mv	s8,ra
+ 118:	009c1023          	sh	s1,0(s8)
+ 11c:	00009023          	sh	zero,0(ra)
+ 120:	00100413          	li	s0,1
+ 124:	00008b93          	mv	s7,ra
+ 128:	008b9023          	sh	s0,0(s7)
+ 12c:	fe009f23          	sh	zero,-2(ra)
+ 130:	fff00393          	li	t2,-1
+ 134:	00008b13          	mv	s6,ra
+ 138:	fe7b1f23          	sh	t2,-2(s6)
+ 13c:	00002097          	auipc	ra,0x2
+ 140:	ef008093          	addi	ra,ra,-272 # 202c <test_3_res>
+ 144:	00009123          	sh	zero,2(ra)
+ 148:	00001337          	lui	t1,0x1
+ 14c:	23430313          	addi	t1,t1,564 # 1234 <fromhost+0x134>
+ 150:	00008a93          	mv	s5,ra
+ 154:	006a9123          	sh	t1,2(s5)
+ 158:	fe009e23          	sh	zero,-4(ra)
+ 15c:	800002b7          	lui	t0,0x80000
+ 160:	00008a13          	mv	s4,ra
+ 164:	fe5a1e23          	sh	t0,-4(s4)
+ 168:	00009123          	sh	zero,2(ra)
+ 16c:	fffff237          	lui	tp,0xfffff
+ 170:	dcc20213          	addi	tp,tp,-564 # ffffedcc <_end+0xffffcbc8>
+ 174:	00008993          	mv	s3,ra
+ 178:	00499123          	sh	tp,2(s3)
+ 17c:	00009223          	sh	zero,4(ra)
+ 180:	fff00193          	li	gp,-1
+ 184:	00008913          	mv	s2,ra
+ 188:	00391223          	sh	gp,4(s2)
+ 18c:	00009023          	sh	zero,0(ra)
+ 190:	80100113          	li	sp,-2047
+ 194:	00008893          	mv	a7,ra
+ 198:	00289023          	sh	sp,0(a7)
+ 19c:	00002117          	auipc	sp,0x2
+ 1a0:	ea410113          	addi	sp,sp,-348 # 2040 <test_4_res>
+ 1a4:	00011023          	sh	zero,0(sp)
+ 1a8:	00000093          	li	ra,0
+ 1ac:	00010813          	mv	a6,sp
+ 1b0:	00181023          	sh	ra,0(a6)
+ 1b4:	00011023          	sh	zero,0(sp)
+ 1b8:	fff00013          	li	zero,-1
+ 1bc:	00010793          	mv	a5,sp
+ 1c0:	00079023          	sh	zero,0(a5)
+ 1c4:	fe011f23          	sh	zero,-2(sp)
+ 1c8:	00100f93          	li	t6,1
+ 1cc:	00010713          	mv	a4,sp
+ 1d0:	fff71f23          	sh	t6,-2(a4)
+ 1d4:	00011123          	sh	zero,2(sp)
+ 1d8:	00000f13          	li	t5,0
+ 1dc:	00010693          	mv	a3,sp
+ 1e0:	01e69123          	sh	t5,2(a3)
+ 1e4:	fe011e23          	sh	zero,-4(sp)
+ 1e8:	7ff00e93          	li	t4,2047
+ 1ec:	00010613          	mv	a2,sp
+ 1f0:	ffd61e23          	sh	t4,-4(a2)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e6008093          	addi	ra,ra,-416 # 2054 <test_5_res>
+ 1fc:	00009123          	sh	zero,2(ra)
+ 200:	00000e13          	li	t3,0
+ 204:	00008593          	mv	a1,ra
+ 208:	01c59123          	sh	t3,2(a1)
+ 20c:	00009223          	sh	zero,4(ra)
+ 210:	00001db7          	lui	s11,0x1
+ 214:	800d8d93          	addi	s11,s11,-2048 # 800 <end_testcode+0x4dc>
+ 218:	00008513          	mv	a0,ra
+ 21c:	01b51223          	sh	s11,4(a0)
+ 220:	00009023          	sh	zero,0(ra)
+ 224:	07654d37          	lui	s10,0x7654
+ 228:	321d0d13          	addi	s10,s10,801 # 7654321 <_end+0x765211d>
+ 22c:	00008493          	mv	s1,ra
+ 230:	01a49023          	sh	s10,0(s1)
+ 234:	00009023          	sh	zero,0(ra)
+ 238:	80000cb7          	lui	s9,0x80000
+ 23c:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 240:	00008413          	mv	s0,ra
+ 244:	01941023          	sh	s9,0(s0)
+ 248:	00009023          	sh	zero,0(ra)
+ 24c:	00100c13          	li	s8,1
+ 250:	00008393          	mv	t2,ra
+ 254:	01839023          	sh	s8,0(t2)
+ 258:	00002097          	auipc	ra,0x2
+ 25c:	e1008093          	addi	ra,ra,-496 # 2068 <test_6_res>
+ 260:	fe009f23          	sh	zero,-2(ra)
+ 264:	fff00b93          	li	s7,-1
+ 268:	00008313          	mv	t1,ra
+ 26c:	ff731f23          	sh	s7,-2(t1)
+ 270:	00009123          	sh	zero,2(ra)
+ 274:	00001b37          	lui	s6,0x1
+ 278:	234b0b13          	addi	s6,s6,564 # 1234 <fromhost+0x134>
+ 27c:	00008293          	mv	t0,ra
+ 280:	01629123          	sh	s6,2(t0) # 80000002 <_end+0x7fffddfe>
+ 284:	fe009e23          	sh	zero,-4(ra)
+ 288:	80000ab7          	lui	s5,0x80000
+ 28c:	00008213          	mv	tp,ra
+ 290:	ff521e23          	sh	s5,-4(tp) # fffffffc <_end+0xffffddf8>
+ 294:	00009123          	sh	zero,2(ra)
+ 298:	fffffa37          	lui	s4,0xfffff
+ 29c:	dcca0a13          	addi	s4,s4,-564 # ffffedcc <_end+0xffffcbc8>
+ 2a0:	00008193          	mv	gp,ra
+ 2a4:	01419123          	sh	s4,2(gp)
+ 2a8:	00009223          	sh	zero,4(ra)
+ 2ac:	fff00993          	li	s3,-1
+ 2b0:	00008113          	mv	sp,ra
+ 2b4:	01311223          	sh	s3,4(sp)
+ 2b8:	00002117          	auipc	sp,0x2
+ 2bc:	dc410113          	addi	sp,sp,-572 # 207c <test_7_res>
+ 2c0:	00011023          	sh	zero,0(sp)
+ 2c4:	80100913          	li	s2,-2047
+ 2c8:	00010093          	mv	ra,sp
+ 2cc:	01209023          	sh	s2,0(ra)
+ 2d0:	00011023          	sh	zero,0(sp)
+ 2d4:	00000893          	li	a7,0
+ 2d8:	00010093          	mv	ra,sp
+ 2dc:	01109023          	sh	a7,0(ra)
+ 2e0:	00002297          	auipc	t0,0x2
+ 2e4:	d2028293          	addi	t0,t0,-736 # 2000 <begin_signature>
+ 2e8:	10000337          	lui	t1,0x10000
+ 2ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2f0:	00532023          	sw	t0,0(t1)
+ 2f4:	00002297          	auipc	t0,0x2
+ 2f8:	d9c28293          	addi	t0,t0,-612 # 2090 <end_signature>
+ 2fc:	10000337          	lui	t1,0x10000
+ 300:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 304:	00532023          	sw	t0,0(t1)
+ 308:	00100293          	li	t0,1
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00000013          	nop
+ 31c:	00100193          	li	gp,1
+ 320:	00000073          	ecall
+
+00000324 <end_testcode>:
+ 324:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+
+00002004 <test_1_res>:
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+
+00002018 <test_2_res>:
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+
+0000202c <test_3_res>:
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+
+00002040 <test_4_res>:
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+
+00002054 <test_5_res>:
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+
+00002068 <test_6_res>:
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+
+0000207c <test_7_res>:
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf
new file mode 100644
index 0000000..1fe7f47
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.bin
new file mode 100644
index 0000000..1ae0afb
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.objdump
new file mode 100644
index 0000000..b07cf6d
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf.objdump
@@ -0,0 +1,329 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLL-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010f9033          	sll	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	00000793          	li	a5,0
+  a0:	00ff10b3          	sll	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	00100713          	li	a4,1
+  b0:	00ee9133          	sll	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	00400693          	li	a3,4
+  c0:	00de11b3          	sll	gp,t3,a3
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00000d93          	li	s11,0
+  cc:	00800613          	li	a2,8
+  d0:	00cd9233          	sll	tp,s11,a2
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f3c08093          	addi	ra,ra,-196 # 2014 <test_2_res>
+  e0:	00001d37          	lui	s10,0x1
+  e4:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4dc>
+  e8:	01f00593          	li	a1,31
+  ec:	00bd12b3          	sll	t0,s10,a1
+  f0:	0050a023          	sw	t0,0(ra)
+  f4:	07654cb7          	lui	s9,0x7654
+  f8:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  fc:	01000513          	li	a0,16
+ 100:	00ac9333          	sll	t1,s9,a0
+ 104:	0060a223          	sw	t1,4(ra)
+ 108:	80000c37          	lui	s8,0x80000
+ 10c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 110:	00100493          	li	s1,1
+ 114:	009c13b3          	sll	t2,s8,s1
+ 118:	0070a423          	sw	t2,8(ra)
+ 11c:	00100b93          	li	s7,1
+ 120:	00000413          	li	s0,0
+ 124:	008b9433          	sll	s0,s7,s0
+ 128:	0080a623          	sw	s0,12(ra)
+ 12c:	fff00b13          	li	s6,-1
+ 130:	00000393          	li	t2,0
+ 134:	007b14b3          	sll	s1,s6,t2
+ 138:	0090a823          	sw	s1,16(ra)
+ 13c:	00002097          	auipc	ra,0x2
+ 140:	eec08093          	addi	ra,ra,-276 # 2028 <test_3_res>
+ 144:	00001ab7          	lui	s5,0x1
+ 148:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 14c:	00100313          	li	t1,1
+ 150:	006a9533          	sll	a0,s5,t1
+ 154:	00a0a023          	sw	a0,0(ra)
+ 158:	80000a37          	lui	s4,0x80000
+ 15c:	00400293          	li	t0,4
+ 160:	005a15b3          	sll	a1,s4,t0
+ 164:	00b0a223          	sw	a1,4(ra)
+ 168:	fffff9b7          	lui	s3,0xfffff
+ 16c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 170:	00800213          	li	tp,8
+ 174:	00499633          	sll	a2,s3,tp
+ 178:	00c0a423          	sw	a2,8(ra)
+ 17c:	fff00913          	li	s2,-1
+ 180:	01f00193          	li	gp,31
+ 184:	003916b3          	sll	a3,s2,gp
+ 188:	00d0a623          	sw	a3,12(ra)
+ 18c:	80100893          	li	a7,-2047
+ 190:	01000113          	li	sp,16
+ 194:	00289733          	sll	a4,a7,sp
+ 198:	00e0a823          	sw	a4,16(ra)
+ 19c:	00002117          	auipc	sp,0x2
+ 1a0:	ea010113          	addi	sp,sp,-352 # 203c <test_4_res>
+ 1a4:	00000813          	li	a6,0
+ 1a8:	00100093          	li	ra,1
+ 1ac:	001817b3          	sll	a5,a6,ra
+ 1b0:	00f12023          	sw	a5,0(sp)
+ 1b4:	fff00793          	li	a5,-1
+ 1b8:	00000013          	nop
+ 1bc:	00079833          	sll	a6,a5,zero
+ 1c0:	01012223          	sw	a6,4(sp)
+ 1c4:	00100713          	li	a4,1
+ 1c8:	00000f93          	li	t6,0
+ 1cc:	01f718b3          	sll	a7,a4,t6
+ 1d0:	01112423          	sw	a7,8(sp)
+ 1d4:	00000693          	li	a3,0
+ 1d8:	00100f13          	li	t5,1
+ 1dc:	01e69933          	sll	s2,a3,t5
+ 1e0:	01212623          	sw	s2,12(sp)
+ 1e4:	7ff00613          	li	a2,2047
+ 1e8:	00400e93          	li	t4,4
+ 1ec:	01d619b3          	sll	s3,a2,t4
+ 1f0:	01312823          	sw	s3,16(sp)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e5c08093          	addi	ra,ra,-420 # 2050 <test_5_res>
+ 1fc:	00000593          	li	a1,0
+ 200:	00800e13          	li	t3,8
+ 204:	01c59a33          	sll	s4,a1,t3
+ 208:	0140a023          	sw	s4,0(ra)
+ 20c:	00001537          	lui	a0,0x1
+ 210:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4dc>
+ 214:	01f00d93          	li	s11,31
+ 218:	01b51ab3          	sll	s5,a0,s11
+ 21c:	0150a223          	sw	s5,4(ra)
+ 220:	076544b7          	lui	s1,0x7654
+ 224:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 228:	01000d13          	li	s10,16
+ 22c:	01a49b33          	sll	s6,s1,s10
+ 230:	0160a423          	sw	s6,8(ra)
+ 234:	80000437          	lui	s0,0x80000
+ 238:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 23c:	00100c93          	li	s9,1
+ 240:	01941bb3          	sll	s7,s0,s9
+ 244:	0170a623          	sw	s7,12(ra)
+ 248:	00100393          	li	t2,1
+ 24c:	00000c13          	li	s8,0
+ 250:	01839c33          	sll	s8,t2,s8
+ 254:	0180a823          	sw	s8,16(ra)
+ 258:	00002097          	auipc	ra,0x2
+ 25c:	e0c08093          	addi	ra,ra,-500 # 2064 <test_6_res>
+ 260:	fff00313          	li	t1,-1
+ 264:	00000b93          	li	s7,0
+ 268:	01731cb3          	sll	s9,t1,s7
+ 26c:	0190a023          	sw	s9,0(ra)
+ 270:	000012b7          	lui	t0,0x1
+ 274:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 278:	00100b13          	li	s6,1
+ 27c:	01629d33          	sll	s10,t0,s6
+ 280:	01a0a223          	sw	s10,4(ra)
+ 284:	80000237          	lui	tp,0x80000
+ 288:	00400a93          	li	s5,4
+ 28c:	01521db3          	sll	s11,tp,s5
+ 290:	01b0a423          	sw	s11,8(ra)
+ 294:	fffff1b7          	lui	gp,0xfffff
+ 298:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 29c:	00800a13          	li	s4,8
+ 2a0:	01419e33          	sll	t3,gp,s4
+ 2a4:	01c0a623          	sw	t3,12(ra)
+ 2a8:	fff00113          	li	sp,-1
+ 2ac:	01f00993          	li	s3,31
+ 2b0:	01311eb3          	sll	t4,sp,s3
+ 2b4:	01d0a823          	sw	t4,16(ra)
+ 2b8:	00002117          	auipc	sp,0x2
+ 2bc:	dc010113          	addi	sp,sp,-576 # 2078 <test_7_res>
+ 2c0:	80100093          	li	ra,-2047
+ 2c4:	01000913          	li	s2,16
+ 2c8:	01209f33          	sll	t5,ra,s2
+ 2cc:	01e12023          	sw	t5,0(sp)
+ 2d0:	00000013          	nop
+ 2d4:	00100893          	li	a7,1
+ 2d8:	01101fb3          	sll	t6,zero,a7
+ 2dc:	01f12223          	sw	t6,4(sp)
+ 2e0:	00002297          	auipc	t0,0x2
+ 2e4:	d2028293          	addi	t0,t0,-736 # 2000 <begin_signature>
+ 2e8:	10000337          	lui	t1,0x10000
+ 2ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2f0:	00532023          	sw	t0,0(t1)
+ 2f4:	00002297          	auipc	t0,0x2
+ 2f8:	d9c28293          	addi	t0,t0,-612 # 2090 <end_signature>
+ 2fc:	10000337          	lui	t1,0x10000
+ 300:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 304:	00532023          	sw	t0,0(t1)
+ 308:	00100293          	li	t0,1
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00000013          	nop
+ 31c:	00100193          	li	gp,1
+ 320:	00000073          	ecall
+
+00000324 <end_testcode>:
+ 324:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf
new file mode 100644
index 0000000..8adf8f0
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.bin
new file mode 100644
index 0000000..aef87e9
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.objdump
new file mode 100644
index 0000000..b4aa6bb
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLLI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000f9013          	slli	zero,t6,0x0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	000f1093          	slli	ra,t5,0x0
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	001e9113          	slli	sp,t4,0x1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	004e1193          	slli	gp,t3,0x4
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	008d9213          	slli	tp,s11,0x8
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	01fd1293          	slli	t0,s10,0x1f
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	010c9313          	slli	t1,s9,0x10
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c1393          	slli	t2,s8,0x1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	000b9413          	slli	s0,s7,0x0
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	000b1493          	slli	s1,s6,0x0
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	001a9513          	slli	a0,s5,0x1
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	004a1593          	slli	a1,s4,0x4
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	00899613          	slli	a2,s3,0x8
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	01f91693          	slli	a3,s2,0x1f
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	01089713          	slli	a4,a7,0x10
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00181793          	slli	a5,a6,0x1
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	00079813          	slli	a6,a5,0x0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	00071893          	slli	a7,a4,0x0
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	00169913          	slli	s2,a3,0x1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	00461993          	slli	s3,a2,0x4
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	00859a13          	slli	s4,a1,0x8
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	01f51a93          	slli	s5,a0,0x1f
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	01049b13          	slli	s6,s1,0x10
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00141b93          	slli	s7,s0,0x1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	00039c13          	slli	s8,t2,0x0
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	00031c93          	slli	s9,t1,0x0
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	00129d13          	slli	s10,t0,0x1
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00421d93          	slli	s11,tp,0x4
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	00819e13          	slli	t3,gp,0x8
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	01f11e93          	slli	t4,sp,0x1f
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	01009f13          	slli	t5,ra,0x10
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00101f93          	slli	t6,zero,0x1
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf
new file mode 100644
index 0000000..1b29762
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.bin
new file mode 100644
index 0000000..a425d2e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.objdump
new file mode 100644
index 0000000..138087c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLT-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010fa033          	slt	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff20b3          	slt	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00eea133          	slt	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de21b3          	slt	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cda233          	slt	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd22b3          	slt	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00aca333          	slt	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c23b3          	slt	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008ba433          	slt	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b24b3          	slt	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006aa533          	slt	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a25b3          	slt	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	0049a633          	slt	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003926b3          	slt	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	0028a733          	slt	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001827b3          	slt	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	0007a833          	sltz	a6,a5
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f728b3          	slt	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e6a933          	slt	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d629b3          	slt	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c5aa33          	slt	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b52ab3          	slt	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a4ab33          	slt	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01942bb3          	slt	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	0183ac33          	slt	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01732cb3          	slt	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	0162ad33          	slt	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01522db3          	slt	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	0141ae33          	slt	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01312eb3          	slt	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	0120af33          	slt	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01102fb3          	sgtz	t6,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf
new file mode 100644
index 0000000..d8f3230
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.bin
new file mode 100644
index 0000000..5ffee9f
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.objdump
new file mode 100644
index 0000000..1dbb56c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLTI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000fa013          	slti	zero,t6,0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f2093          	slti	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffea113          	slti	sp,t4,-1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e2193          	slti	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800da213          	slti	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d2293          	slti	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800ca313          	slti	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c2393          	slti	t2,s8,1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800ba413          	slti	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b2493          	slti	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800aa513          	slti	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a2593          	slti	a1,s4,0
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff9a613          	slti	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff92693          	slti	a3,s2,-1
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0018a713          	slti	a4,a7,1
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00082793          	slti	a5,a6,0
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007a813          	slti	a6,a5,0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80172893          	slti	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff6a913          	slti	s2,a3,-1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80062993          	slti	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	8005aa13          	slti	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80052a93          	slti	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	8004ab13          	slti	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00142b93          	slti	s7,s0,1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	8003ac13          	slti	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80032c93          	slti	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	8002ad13          	slti	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00022d93          	slti	s11,tp,0
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff1ae13          	slti	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff12e93          	slti	t4,sp,-1
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0010af13          	slti	t5,ra,1
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00002f93          	slti	t6,zero,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf
new file mode 100644
index 0000000..e351260
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.bin
new file mode 100644
index 0000000..8c5fa09
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.objdump
new file mode 100644
index 0000000..737c723
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLTIU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000fb013          	sltiu	zero,t6,0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f3093          	sltiu	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffeb113          	sltiu	sp,t4,-1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e3193          	sltiu	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800db213          	sltiu	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d3293          	sltiu	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800cb313          	sltiu	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c3393          	seqz	t2,s8
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800bb413          	sltiu	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b3493          	sltiu	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800ab513          	sltiu	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a3593          	sltiu	a1,s4,0
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff9b613          	sltiu	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff93693          	sltiu	a3,s2,-1
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0018b713          	seqz	a4,a7
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00083793          	sltiu	a5,a6,0
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007b813          	sltiu	a6,a5,0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80173893          	sltiu	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff6b913          	sltiu	s2,a3,-1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80063993          	sltiu	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	8005ba13          	sltiu	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80053a93          	sltiu	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	8004bb13          	sltiu	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00143b93          	seqz	s7,s0
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	8003bc13          	sltiu	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80033c93          	sltiu	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	8002bd13          	sltiu	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00023d93          	sltiu	s11,tp,0
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff1be13          	sltiu	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff13e93          	sltiu	t4,sp,-1
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0010bf13          	seqz	t5,ra
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00003f93          	sltiu	t6,zero,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf
new file mode 100644
index 0000000..9c0a672
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.bin
new file mode 100644
index 0000000..ff2d3f7
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.objdump
new file mode 100644
index 0000000..e56927b
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SLTU-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010fb033          	sltu	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff30b3          	sltu	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00eeb133          	sltu	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de31b3          	sltu	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cdb233          	sltu	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd32b3          	sltu	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00acb333          	sltu	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c33b3          	sltu	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008bb433          	sltu	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b34b3          	sltu	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006ab533          	sltu	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a35b3          	sltu	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	0049b633          	sltu	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003936b3          	sltu	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	0028b733          	sltu	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001837b3          	sltu	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	0007b833          	sltu	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f738b3          	sltu	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e6b933          	sltu	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d639b3          	sltu	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c5ba33          	sltu	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b53ab3          	sltu	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a4bb33          	sltu	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01943bb3          	sltu	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	0183bc33          	sltu	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01733cb3          	sltu	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	0162bd33          	sltu	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01523db3          	sltu	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	0141be33          	sltu	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01313eb3          	sltu	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	0120bf33          	sltu	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01103fb3          	snez	t6,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf
new file mode 100644
index 0000000..61a1323
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.bin
new file mode 100644
index 0000000..43079ae
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.objdump
new file mode 100644
index 0000000..6fb83a8
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf.objdump
@@ -0,0 +1,329 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SRA-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	410fd033          	sra	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	00000793          	li	a5,0
+  a0:	40ff50b3          	sra	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	00100713          	li	a4,1
+  b0:	40eed133          	sra	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	00400693          	li	a3,4
+  c0:	40de51b3          	sra	gp,t3,a3
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00000d93          	li	s11,0
+  cc:	00800613          	li	a2,8
+  d0:	40cdd233          	sra	tp,s11,a2
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f3c08093          	addi	ra,ra,-196 # 2014 <test_2_res>
+  e0:	00001d37          	lui	s10,0x1
+  e4:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4dc>
+  e8:	01f00593          	li	a1,31
+  ec:	40bd52b3          	sra	t0,s10,a1
+  f0:	0050a023          	sw	t0,0(ra)
+  f4:	07654cb7          	lui	s9,0x7654
+  f8:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  fc:	01000513          	li	a0,16
+ 100:	40acd333          	sra	t1,s9,a0
+ 104:	0060a223          	sw	t1,4(ra)
+ 108:	80000c37          	lui	s8,0x80000
+ 10c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 110:	00100493          	li	s1,1
+ 114:	409c53b3          	sra	t2,s8,s1
+ 118:	0070a423          	sw	t2,8(ra)
+ 11c:	00100b93          	li	s7,1
+ 120:	00000413          	li	s0,0
+ 124:	408bd433          	sra	s0,s7,s0
+ 128:	0080a623          	sw	s0,12(ra)
+ 12c:	fff00b13          	li	s6,-1
+ 130:	00000393          	li	t2,0
+ 134:	407b54b3          	sra	s1,s6,t2
+ 138:	0090a823          	sw	s1,16(ra)
+ 13c:	00002097          	auipc	ra,0x2
+ 140:	eec08093          	addi	ra,ra,-276 # 2028 <test_3_res>
+ 144:	00001ab7          	lui	s5,0x1
+ 148:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 14c:	00100313          	li	t1,1
+ 150:	406ad533          	sra	a0,s5,t1
+ 154:	00a0a023          	sw	a0,0(ra)
+ 158:	80000a37          	lui	s4,0x80000
+ 15c:	00400293          	li	t0,4
+ 160:	405a55b3          	sra	a1,s4,t0
+ 164:	00b0a223          	sw	a1,4(ra)
+ 168:	fffff9b7          	lui	s3,0xfffff
+ 16c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 170:	00800213          	li	tp,8
+ 174:	4049d633          	sra	a2,s3,tp
+ 178:	00c0a423          	sw	a2,8(ra)
+ 17c:	fff00913          	li	s2,-1
+ 180:	01f00193          	li	gp,31
+ 184:	403956b3          	sra	a3,s2,gp
+ 188:	00d0a623          	sw	a3,12(ra)
+ 18c:	80100893          	li	a7,-2047
+ 190:	01000113          	li	sp,16
+ 194:	4028d733          	sra	a4,a7,sp
+ 198:	00e0a823          	sw	a4,16(ra)
+ 19c:	00002117          	auipc	sp,0x2
+ 1a0:	ea010113          	addi	sp,sp,-352 # 203c <test_4_res>
+ 1a4:	00000813          	li	a6,0
+ 1a8:	00100093          	li	ra,1
+ 1ac:	401857b3          	sra	a5,a6,ra
+ 1b0:	00f12023          	sw	a5,0(sp)
+ 1b4:	fff00793          	li	a5,-1
+ 1b8:	00000013          	nop
+ 1bc:	4007d833          	sra	a6,a5,zero
+ 1c0:	01012223          	sw	a6,4(sp)
+ 1c4:	00100713          	li	a4,1
+ 1c8:	00000f93          	li	t6,0
+ 1cc:	41f758b3          	sra	a7,a4,t6
+ 1d0:	01112423          	sw	a7,8(sp)
+ 1d4:	00000693          	li	a3,0
+ 1d8:	00100f13          	li	t5,1
+ 1dc:	41e6d933          	sra	s2,a3,t5
+ 1e0:	01212623          	sw	s2,12(sp)
+ 1e4:	7ff00613          	li	a2,2047
+ 1e8:	00400e93          	li	t4,4
+ 1ec:	41d659b3          	sra	s3,a2,t4
+ 1f0:	01312823          	sw	s3,16(sp)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e5c08093          	addi	ra,ra,-420 # 2050 <test_5_res>
+ 1fc:	00000593          	li	a1,0
+ 200:	00800e13          	li	t3,8
+ 204:	41c5da33          	sra	s4,a1,t3
+ 208:	0140a023          	sw	s4,0(ra)
+ 20c:	00001537          	lui	a0,0x1
+ 210:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4dc>
+ 214:	01f00d93          	li	s11,31
+ 218:	41b55ab3          	sra	s5,a0,s11
+ 21c:	0150a223          	sw	s5,4(ra)
+ 220:	076544b7          	lui	s1,0x7654
+ 224:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 228:	01000d13          	li	s10,16
+ 22c:	41a4db33          	sra	s6,s1,s10
+ 230:	0160a423          	sw	s6,8(ra)
+ 234:	80000437          	lui	s0,0x80000
+ 238:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 23c:	00100c93          	li	s9,1
+ 240:	41945bb3          	sra	s7,s0,s9
+ 244:	0170a623          	sw	s7,12(ra)
+ 248:	00100393          	li	t2,1
+ 24c:	00000c13          	li	s8,0
+ 250:	4183dc33          	sra	s8,t2,s8
+ 254:	0180a823          	sw	s8,16(ra)
+ 258:	00002097          	auipc	ra,0x2
+ 25c:	e0c08093          	addi	ra,ra,-500 # 2064 <test_6_res>
+ 260:	fff00313          	li	t1,-1
+ 264:	00000b93          	li	s7,0
+ 268:	41735cb3          	sra	s9,t1,s7
+ 26c:	0190a023          	sw	s9,0(ra)
+ 270:	000012b7          	lui	t0,0x1
+ 274:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 278:	00100b13          	li	s6,1
+ 27c:	4162dd33          	sra	s10,t0,s6
+ 280:	01a0a223          	sw	s10,4(ra)
+ 284:	80000237          	lui	tp,0x80000
+ 288:	00400a93          	li	s5,4
+ 28c:	41525db3          	sra	s11,tp,s5
+ 290:	01b0a423          	sw	s11,8(ra)
+ 294:	fffff1b7          	lui	gp,0xfffff
+ 298:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 29c:	00800a13          	li	s4,8
+ 2a0:	4141de33          	sra	t3,gp,s4
+ 2a4:	01c0a623          	sw	t3,12(ra)
+ 2a8:	fff00113          	li	sp,-1
+ 2ac:	01f00993          	li	s3,31
+ 2b0:	41315eb3          	sra	t4,sp,s3
+ 2b4:	01d0a823          	sw	t4,16(ra)
+ 2b8:	00002117          	auipc	sp,0x2
+ 2bc:	dc010113          	addi	sp,sp,-576 # 2078 <test_7_res>
+ 2c0:	80100093          	li	ra,-2047
+ 2c4:	01000913          	li	s2,16
+ 2c8:	4120df33          	sra	t5,ra,s2
+ 2cc:	01e12023          	sw	t5,0(sp)
+ 2d0:	00000013          	nop
+ 2d4:	00100893          	li	a7,1
+ 2d8:	41105fb3          	sra	t6,zero,a7
+ 2dc:	01f12223          	sw	t6,4(sp)
+ 2e0:	00002297          	auipc	t0,0x2
+ 2e4:	d2028293          	addi	t0,t0,-736 # 2000 <begin_signature>
+ 2e8:	10000337          	lui	t1,0x10000
+ 2ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2f0:	00532023          	sw	t0,0(t1)
+ 2f4:	00002297          	auipc	t0,0x2
+ 2f8:	d9c28293          	addi	t0,t0,-612 # 2090 <end_signature>
+ 2fc:	10000337          	lui	t1,0x10000
+ 300:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 304:	00532023          	sw	t0,0(t1)
+ 308:	00100293          	li	t0,1
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00000013          	nop
+ 31c:	00100193          	li	gp,1
+ 320:	00000073          	ecall
+
+00000324 <end_testcode>:
+ 324:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf
new file mode 100644
index 0000000..23b0fed
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.bin
new file mode 100644
index 0000000..55da1ff
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.objdump
new file mode 100644
index 0000000..827fa15
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SRAI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	400fd013          	srai	zero,t6,0x0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	400f5093          	srai	ra,t5,0x0
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	401ed113          	srai	sp,t4,0x1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	404e5193          	srai	gp,t3,0x4
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	408dd213          	srai	tp,s11,0x8
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	41fd5293          	srai	t0,s10,0x1f
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	410cd313          	srai	t1,s9,0x10
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	401c5393          	srai	t2,s8,0x1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	400bd413          	srai	s0,s7,0x0
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	400b5493          	srai	s1,s6,0x0
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	401ad513          	srai	a0,s5,0x1
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	404a5593          	srai	a1,s4,0x4
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	4089d613          	srai	a2,s3,0x8
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	41f95693          	srai	a3,s2,0x1f
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	4108d713          	srai	a4,a7,0x10
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	40185793          	srai	a5,a6,0x1
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	4007d813          	srai	a6,a5,0x0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	40075893          	srai	a7,a4,0x0
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	4016d913          	srai	s2,a3,0x1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	40465993          	srai	s3,a2,0x4
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	4085da13          	srai	s4,a1,0x8
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	41f55a93          	srai	s5,a0,0x1f
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	4104db13          	srai	s6,s1,0x10
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	40145b93          	srai	s7,s0,0x1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	4003dc13          	srai	s8,t2,0x0
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	40035c93          	srai	s9,t1,0x0
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	4012dd13          	srai	s10,t0,0x1
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	40425d93          	srai	s11,tp,0x4
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	4081de13          	srai	t3,gp,0x8
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	41f15e93          	srai	t4,sp,0x1f
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	4100df13          	srai	t5,ra,0x10
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	40105f93          	srai	t6,zero,0x1
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf
new file mode 100644
index 0000000..88fc19c
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.bin
new file mode 100644
index 0000000..6cdcea2
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.objdump
new file mode 100644
index 0000000..11337fd
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf.objdump
@@ -0,0 +1,329 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SRL-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010fd033          	srl	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	00000793          	li	a5,0
+  a0:	00ff50b3          	srl	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	00100713          	li	a4,1
+  b0:	00eed133          	srl	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	00400693          	li	a3,4
+  c0:	00de51b3          	srl	gp,t3,a3
+  c4:	0032a623          	sw	gp,12(t0)
+  c8:	00000d93          	li	s11,0
+  cc:	00800613          	li	a2,8
+  d0:	00cdd233          	srl	tp,s11,a2
+  d4:	0042a823          	sw	tp,16(t0)
+  d8:	00002097          	auipc	ra,0x2
+  dc:	f3c08093          	addi	ra,ra,-196 # 2014 <test_2_res>
+  e0:	00001d37          	lui	s10,0x1
+  e4:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4dc>
+  e8:	01f00593          	li	a1,31
+  ec:	00bd52b3          	srl	t0,s10,a1
+  f0:	0050a023          	sw	t0,0(ra)
+  f4:	07654cb7          	lui	s9,0x7654
+  f8:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  fc:	01000513          	li	a0,16
+ 100:	00acd333          	srl	t1,s9,a0
+ 104:	0060a223          	sw	t1,4(ra)
+ 108:	80000c37          	lui	s8,0x80000
+ 10c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 110:	00100493          	li	s1,1
+ 114:	009c53b3          	srl	t2,s8,s1
+ 118:	0070a423          	sw	t2,8(ra)
+ 11c:	00100b93          	li	s7,1
+ 120:	00000413          	li	s0,0
+ 124:	008bd433          	srl	s0,s7,s0
+ 128:	0080a623          	sw	s0,12(ra)
+ 12c:	fff00b13          	li	s6,-1
+ 130:	00000393          	li	t2,0
+ 134:	007b54b3          	srl	s1,s6,t2
+ 138:	0090a823          	sw	s1,16(ra)
+ 13c:	00002097          	auipc	ra,0x2
+ 140:	eec08093          	addi	ra,ra,-276 # 2028 <test_3_res>
+ 144:	00001ab7          	lui	s5,0x1
+ 148:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 14c:	00100313          	li	t1,1
+ 150:	006ad533          	srl	a0,s5,t1
+ 154:	00a0a023          	sw	a0,0(ra)
+ 158:	80000a37          	lui	s4,0x80000
+ 15c:	00400293          	li	t0,4
+ 160:	005a55b3          	srl	a1,s4,t0
+ 164:	00b0a223          	sw	a1,4(ra)
+ 168:	fffff9b7          	lui	s3,0xfffff
+ 16c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 170:	00800213          	li	tp,8
+ 174:	0049d633          	srl	a2,s3,tp
+ 178:	00c0a423          	sw	a2,8(ra)
+ 17c:	fff00913          	li	s2,-1
+ 180:	01f00193          	li	gp,31
+ 184:	003956b3          	srl	a3,s2,gp
+ 188:	00d0a623          	sw	a3,12(ra)
+ 18c:	80100893          	li	a7,-2047
+ 190:	01000113          	li	sp,16
+ 194:	0028d733          	srl	a4,a7,sp
+ 198:	00e0a823          	sw	a4,16(ra)
+ 19c:	00002117          	auipc	sp,0x2
+ 1a0:	ea010113          	addi	sp,sp,-352 # 203c <test_4_res>
+ 1a4:	00000813          	li	a6,0
+ 1a8:	00100093          	li	ra,1
+ 1ac:	001857b3          	srl	a5,a6,ra
+ 1b0:	00f12023          	sw	a5,0(sp)
+ 1b4:	fff00793          	li	a5,-1
+ 1b8:	00000013          	nop
+ 1bc:	0007d833          	srl	a6,a5,zero
+ 1c0:	01012223          	sw	a6,4(sp)
+ 1c4:	00100713          	li	a4,1
+ 1c8:	00000f93          	li	t6,0
+ 1cc:	01f758b3          	srl	a7,a4,t6
+ 1d0:	01112423          	sw	a7,8(sp)
+ 1d4:	00000693          	li	a3,0
+ 1d8:	00100f13          	li	t5,1
+ 1dc:	01e6d933          	srl	s2,a3,t5
+ 1e0:	01212623          	sw	s2,12(sp)
+ 1e4:	7ff00613          	li	a2,2047
+ 1e8:	00400e93          	li	t4,4
+ 1ec:	01d659b3          	srl	s3,a2,t4
+ 1f0:	01312823          	sw	s3,16(sp)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e5c08093          	addi	ra,ra,-420 # 2050 <test_5_res>
+ 1fc:	00000593          	li	a1,0
+ 200:	00800e13          	li	t3,8
+ 204:	01c5da33          	srl	s4,a1,t3
+ 208:	0140a023          	sw	s4,0(ra)
+ 20c:	00001537          	lui	a0,0x1
+ 210:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4dc>
+ 214:	01f00d93          	li	s11,31
+ 218:	01b55ab3          	srl	s5,a0,s11
+ 21c:	0150a223          	sw	s5,4(ra)
+ 220:	076544b7          	lui	s1,0x7654
+ 224:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 228:	01000d13          	li	s10,16
+ 22c:	01a4db33          	srl	s6,s1,s10
+ 230:	0160a423          	sw	s6,8(ra)
+ 234:	80000437          	lui	s0,0x80000
+ 238:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 23c:	00100c93          	li	s9,1
+ 240:	01945bb3          	srl	s7,s0,s9
+ 244:	0170a623          	sw	s7,12(ra)
+ 248:	00100393          	li	t2,1
+ 24c:	00000c13          	li	s8,0
+ 250:	0183dc33          	srl	s8,t2,s8
+ 254:	0180a823          	sw	s8,16(ra)
+ 258:	00002097          	auipc	ra,0x2
+ 25c:	e0c08093          	addi	ra,ra,-500 # 2064 <test_6_res>
+ 260:	fff00313          	li	t1,-1
+ 264:	00000b93          	li	s7,0
+ 268:	01735cb3          	srl	s9,t1,s7
+ 26c:	0190a023          	sw	s9,0(ra)
+ 270:	000012b7          	lui	t0,0x1
+ 274:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 278:	00100b13          	li	s6,1
+ 27c:	0162dd33          	srl	s10,t0,s6
+ 280:	01a0a223          	sw	s10,4(ra)
+ 284:	80000237          	lui	tp,0x80000
+ 288:	00400a93          	li	s5,4
+ 28c:	01525db3          	srl	s11,tp,s5
+ 290:	01b0a423          	sw	s11,8(ra)
+ 294:	fffff1b7          	lui	gp,0xfffff
+ 298:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 29c:	00800a13          	li	s4,8
+ 2a0:	0141de33          	srl	t3,gp,s4
+ 2a4:	01c0a623          	sw	t3,12(ra)
+ 2a8:	fff00113          	li	sp,-1
+ 2ac:	01f00993          	li	s3,31
+ 2b0:	01315eb3          	srl	t4,sp,s3
+ 2b4:	01d0a823          	sw	t4,16(ra)
+ 2b8:	00002117          	auipc	sp,0x2
+ 2bc:	dc010113          	addi	sp,sp,-576 # 2078 <test_7_res>
+ 2c0:	80100093          	li	ra,-2047
+ 2c4:	01000913          	li	s2,16
+ 2c8:	0120df33          	srl	t5,ra,s2
+ 2cc:	01e12023          	sw	t5,0(sp)
+ 2d0:	00000013          	nop
+ 2d4:	00100893          	li	a7,1
+ 2d8:	01105fb3          	srl	t6,zero,a7
+ 2dc:	01f12223          	sw	t6,4(sp)
+ 2e0:	00002297          	auipc	t0,0x2
+ 2e4:	d2028293          	addi	t0,t0,-736 # 2000 <begin_signature>
+ 2e8:	10000337          	lui	t1,0x10000
+ 2ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 2f0:	00532023          	sw	t0,0(t1)
+ 2f4:	00002297          	auipc	t0,0x2
+ 2f8:	d9c28293          	addi	t0,t0,-612 # 2090 <end_signature>
+ 2fc:	10000337          	lui	t1,0x10000
+ 300:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 304:	00532023          	sw	t0,0(t1)
+ 308:	00100293          	li	t0,1
+ 30c:	10000337          	lui	t1,0x10000
+ 310:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 314:	00532023          	sw	t0,0(t1)
+ 318:	00000013          	nop
+ 31c:	00100193          	li	gp,1
+ 320:	00000073          	ecall
+
+00000324 <end_testcode>:
+ 324:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf
new file mode 100644
index 0000000..53e9db1
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.bin
new file mode 100644
index 0000000..25e32f5
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.objdump
new file mode 100644
index 0000000..e8a49c7
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SRLI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000fd013          	srli	zero,t6,0x0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	000f5093          	srli	ra,t5,0x0
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	001ed113          	srli	sp,t4,0x1
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	004e5193          	srli	gp,t3,0x4
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	008dd213          	srli	tp,s11,0x8
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	01fd5293          	srli	t0,s10,0x1f
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	010cd313          	srli	t1,s9,0x10
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c5393          	srli	t2,s8,0x1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	000bd413          	srli	s0,s7,0x0
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	000b5493          	srli	s1,s6,0x0
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	001ad513          	srli	a0,s5,0x1
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	004a5593          	srli	a1,s4,0x4
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	0089d613          	srli	a2,s3,0x8
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	01f95693          	srli	a3,s2,0x1f
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0108d713          	srli	a4,a7,0x10
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00185793          	srli	a5,a6,0x1
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007d813          	srli	a6,a5,0x0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	00075893          	srli	a7,a4,0x0
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	0016d913          	srli	s2,a3,0x1
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	00465993          	srli	s3,a2,0x4
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	0085da13          	srli	s4,a1,0x8
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	01f55a93          	srli	s5,a0,0x1f
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	0104db13          	srli	s6,s1,0x10
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00145b93          	srli	s7,s0,0x1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	0003dc13          	srli	s8,t2,0x0
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	00035c93          	srli	s9,t1,0x0
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	0012dd13          	srli	s10,t0,0x1
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00425d93          	srli	s11,tp,0x4
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	0081de13          	srli	t3,gp,0x8
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	01f15e93          	srli	t4,sp,0x1f
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0100df13          	srli	t5,ra,0x10
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00105f93          	srli	t6,zero,0x1
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf
new file mode 100644
index 0000000..4042f83
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.bin
new file mode 100644
index 0000000..6958799
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.objdump
new file mode 100644
index 0000000..6406c5b
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SUB-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	410f8033          	sub	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	40ff00b3          	sub	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	40ee8133          	sub	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	40de01b3          	sub	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	40cd8233          	sub	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	40bd02b3          	sub	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	40ac8333          	sub	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	409c03b3          	sub	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	408b8433          	sub	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	407b04b3          	sub	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	406a8533          	sub	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	405a05b3          	sub	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	40498633          	sub	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	403906b3          	sub	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	40288733          	sub	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	401807b3          	sub	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	40078833          	sub	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	41f708b3          	sub	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	41e68933          	sub	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	41d609b3          	sub	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	41c58a33          	sub	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	41b50ab3          	sub	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	41a48b33          	sub	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	41940bb3          	sub	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	41838c33          	sub	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	41730cb3          	sub	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	41628d33          	sub	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	41520db3          	sub	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	41418e33          	sub	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	41310eb3          	sub	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	41208f33          	sub	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	41100fb3          	neg	t6,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf
new file mode 100644
index 0000000..e557028
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.bin
new file mode 100644
index 0000000..8c52408
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.objdump
new file mode 100644
index 0000000..77d765a
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf.objdump
@@ -0,0 +1,393 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-SW-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	0002a023          	sw	zero,0(t0)
+  8c:	fff00813          	li	a6,-1
+  90:	00028f93          	mv	t6,t0
+  94:	7d0f8f93          	addi	t6,t6,2000
+  98:	830fa823          	sw	a6,-2000(t6)
+  9c:	0002a383          	lw	t2,0(t0)
+  a0:	0002a223          	sw	zero,4(t0)
+  a4:	00100793          	li	a5,1
+  a8:	00428f13          	addi	t5,t0,4
+  ac:	000f0f13          	mv	t5,t5
+  b0:	00ff2023          	sw	a5,0(t5)
+  b4:	0042a383          	lw	t2,4(t0)
+  b8:	0002a423          	sw	zero,8(t0)
+  bc:	00000713          	li	a4,0
+  c0:	00828e93          	addi	t4,t0,8
+  c4:	001e8e93          	addi	t4,t4,1
+  c8:	feeeafa3          	sw	a4,-1(t4)
+  cc:	0082a383          	lw	t2,8(t0)
+  d0:	0002a623          	sw	zero,12(t0)
+  d4:	7ff00693          	li	a3,2047
+  d8:	00c28e13          	addi	t3,t0,12
+  dc:	7d0e0e13          	addi	t3,t3,2000
+  e0:	82de2823          	sw	a3,-2000(t3)
+  e4:	00c2a383          	lw	t2,12(t0)
+  e8:	0002a823          	sw	zero,16(t0)
+  ec:	00000613          	li	a2,0
+  f0:	01028d93          	addi	s11,t0,16
+  f4:	830d8d93          	addi	s11,s11,-2000
+  f8:	7ccda823          	sw	a2,2000(s11)
+  fc:	0102a383          	lw	t2,16(t0)
+ 100:	00002097          	auipc	ra,0x2
+ 104:	f1408093          	addi	ra,ra,-236 # 2014 <test_2_res>
+ 108:	0000a023          	sw	zero,0(ra)
+ 10c:	000015b7          	lui	a1,0x1
+ 110:	80058593          	addi	a1,a1,-2048 # 800 <end_testcode+0x3dc>
+ 114:	00008d13          	mv	s10,ra
+ 118:	830d0d13          	addi	s10,s10,-2000
+ 11c:	7cbd2823          	sw	a1,2000(s10)
+ 120:	0000a183          	lw	gp,0(ra)
+ 124:	0000a223          	sw	zero,4(ra)
+ 128:	07654537          	lui	a0,0x7654
+ 12c:	32150513          	addi	a0,a0,801 # 7654321 <_end+0x765211d>
+ 130:	00408c93          	addi	s9,ra,4
+ 134:	830c8c93          	addi	s9,s9,-2000
+ 138:	7caca823          	sw	a0,2000(s9)
+ 13c:	0040a183          	lw	gp,4(ra)
+ 140:	0000a423          	sw	zero,8(ra)
+ 144:	800004b7          	lui	s1,0x80000
+ 148:	fff48493          	addi	s1,s1,-1 # 7fffffff <_end+0x7fffddfb>
+ 14c:	00808c13          	addi	s8,ra,8
+ 150:	fffc0c13          	addi	s8,s8,-1
+ 154:	009c20a3          	sw	s1,1(s8)
+ 158:	0080a183          	lw	gp,8(ra)
+ 15c:	0000a623          	sw	zero,12(ra)
+ 160:	00100413          	li	s0,1
+ 164:	00c08b93          	addi	s7,ra,12
+ 168:	830b8b93          	addi	s7,s7,-2000
+ 16c:	7c8ba823          	sw	s0,2000(s7)
+ 170:	00c0a183          	lw	gp,12(ra)
+ 174:	0000a823          	sw	zero,16(ra)
+ 178:	fff00393          	li	t2,-1
+ 17c:	01008b13          	addi	s6,ra,16
+ 180:	830b0b13          	addi	s6,s6,-2000
+ 184:	7c7b2823          	sw	t2,2000(s6)
+ 188:	0100a183          	lw	gp,16(ra)
+ 18c:	00002097          	auipc	ra,0x2
+ 190:	e9c08093          	addi	ra,ra,-356 # 2028 <test_3_res>
+ 194:	0000a023          	sw	zero,0(ra)
+ 198:	00001337          	lui	t1,0x1
+ 19c:	23430313          	addi	t1,t1,564 # 1234 <fromhost+0x134>
+ 1a0:	00008a93          	mv	s5,ra
+ 1a4:	830a8a93          	addi	s5,s5,-2000
+ 1a8:	7c6aa823          	sw	t1,2000(s5)
+ 1ac:	0000a403          	lw	s0,0(ra)
+ 1b0:	0000a223          	sw	zero,4(ra)
+ 1b4:	800002b7          	lui	t0,0x80000
+ 1b8:	00408a13          	addi	s4,ra,4
+ 1bc:	000a0a13          	mv	s4,s4
+ 1c0:	005a2023          	sw	t0,0(s4)
+ 1c4:	0040a403          	lw	s0,4(ra)
+ 1c8:	0000a423          	sw	zero,8(ra)
+ 1cc:	fffff237          	lui	tp,0xfffff
+ 1d0:	dcc20213          	addi	tp,tp,-564 # ffffedcc <_end+0xffffcbc8>
+ 1d4:	00808993          	addi	s3,ra,8
+ 1d8:	83098993          	addi	s3,s3,-2000
+ 1dc:	7c49a823          	sw	tp,2000(s3)
+ 1e0:	0080a403          	lw	s0,8(ra)
+ 1e4:	0000a623          	sw	zero,12(ra)
+ 1e8:	fff00193          	li	gp,-1
+ 1ec:	00c08913          	addi	s2,ra,12
+ 1f0:	00190913          	addi	s2,s2,1
+ 1f4:	fe392fa3          	sw	gp,-1(s2)
+ 1f8:	00c0a403          	lw	s0,12(ra)
+ 1fc:	0000a823          	sw	zero,16(ra)
+ 200:	80100113          	li	sp,-2047
+ 204:	01008893          	addi	a7,ra,16
+ 208:	00088893          	mv	a7,a7
+ 20c:	0028a023          	sw	sp,0(a7)
+ 210:	0100a403          	lw	s0,16(ra)
+ 214:	00002117          	auipc	sp,0x2
+ 218:	e2810113          	addi	sp,sp,-472 # 203c <test_4_res>
+ 21c:	00012023          	sw	zero,0(sp)
+ 220:	ffe00093          	li	ra,-2
+ 224:	00010813          	mv	a6,sp
+ 228:	fff80813          	addi	a6,a6,-1
+ 22c:	001820a3          	sw	ra,1(a6)
+ 230:	00012203          	lw	tp,0(sp)
+ 234:	00012223          	sw	zero,4(sp)
+ 238:	fff00013          	li	zero,-1
+ 23c:	00410793          	addi	a5,sp,4
+ 240:	7d078793          	addi	a5,a5,2000
+ 244:	8207a823          	sw	zero,-2000(a5)
+ 248:	00412203          	lw	tp,4(sp)
+ 24c:	00012423          	sw	zero,8(sp)
+ 250:	00100f93          	li	t6,1
+ 254:	00810713          	addi	a4,sp,8
+ 258:	00070713          	mv	a4,a4
+ 25c:	01f72023          	sw	t6,0(a4)
+ 260:	00812203          	lw	tp,8(sp)
+ 264:	00012623          	sw	zero,12(sp)
+ 268:	00000f13          	li	t5,0
+ 26c:	00c10693          	addi	a3,sp,12
+ 270:	00168693          	addi	a3,a3,1
+ 274:	ffe6afa3          	sw	t5,-1(a3)
+ 278:	00c12203          	lw	tp,12(sp)
+ 27c:	00012823          	sw	zero,16(sp)
+ 280:	7ff00e93          	li	t4,2047
+ 284:	01010613          	addi	a2,sp,16
+ 288:	7d060613          	addi	a2,a2,2000
+ 28c:	83d62823          	sw	t4,-2000(a2)
+ 290:	01012203          	lw	tp,16(sp)
+ 294:	00002097          	auipc	ra,0x2
+ 298:	dbc08093          	addi	ra,ra,-580 # 2050 <test_5_res>
+ 29c:	0000a023          	sw	zero,0(ra)
+ 2a0:	00000e13          	li	t3,0
+ 2a4:	00008593          	mv	a1,ra
+ 2a8:	83058593          	addi	a1,a1,-2000
+ 2ac:	7dc5a823          	sw	t3,2000(a1)
+ 2b0:	0000a183          	lw	gp,0(ra)
+ 2b4:	0000a223          	sw	zero,4(ra)
+ 2b8:	00001db7          	lui	s11,0x1
+ 2bc:	800d8d93          	addi	s11,s11,-2048 # 800 <end_testcode+0x3dc>
+ 2c0:	00408513          	addi	a0,ra,4
+ 2c4:	83050513          	addi	a0,a0,-2000
+ 2c8:	7db52823          	sw	s11,2000(a0)
+ 2cc:	0040a183          	lw	gp,4(ra)
+ 2d0:	0000a423          	sw	zero,8(ra)
+ 2d4:	07654d37          	lui	s10,0x7654
+ 2d8:	321d0d13          	addi	s10,s10,801 # 7654321 <_end+0x765211d>
+ 2dc:	00808493          	addi	s1,ra,8
+ 2e0:	83048493          	addi	s1,s1,-2000
+ 2e4:	7da4a823          	sw	s10,2000(s1)
+ 2e8:	0080a183          	lw	gp,8(ra)
+ 2ec:	0000a623          	sw	zero,12(ra)
+ 2f0:	80000cb7          	lui	s9,0x80000
+ 2f4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 2f8:	00c08413          	addi	s0,ra,12
+ 2fc:	fff40413          	addi	s0,s0,-1
+ 300:	019420a3          	sw	s9,1(s0)
+ 304:	00c0a183          	lw	gp,12(ra)
+ 308:	0000a823          	sw	zero,16(ra)
+ 30c:	00100c13          	li	s8,1
+ 310:	01008393          	addi	t2,ra,16
+ 314:	83038393          	addi	t2,t2,-2000
+ 318:	7d83a823          	sw	s8,2000(t2)
+ 31c:	0100a183          	lw	gp,16(ra)
+ 320:	00002097          	auipc	ra,0x2
+ 324:	d4408093          	addi	ra,ra,-700 # 2064 <test_6_res>
+ 328:	0000a023          	sw	zero,0(ra)
+ 32c:	fff00b93          	li	s7,-1
+ 330:	00008313          	mv	t1,ra
+ 334:	83030313          	addi	t1,t1,-2000
+ 338:	7d732823          	sw	s7,2000(t1)
+ 33c:	0000a403          	lw	s0,0(ra)
+ 340:	0000a223          	sw	zero,4(ra)
+ 344:	00001b37          	lui	s6,0x1
+ 348:	234b0b13          	addi	s6,s6,564 # 1234 <fromhost+0x134>
+ 34c:	00408293          	addi	t0,ra,4
+ 350:	83028293          	addi	t0,t0,-2000 # 7ffff830 <_end+0x7fffd62c>
+ 354:	7d62a823          	sw	s6,2000(t0)
+ 358:	0040a403          	lw	s0,4(ra)
+ 35c:	0000a423          	sw	zero,8(ra)
+ 360:	80000ab7          	lui	s5,0x80000
+ 364:	00808213          	addi	tp,ra,8
+ 368:	00020213          	mv	tp,tp
+ 36c:	01522023          	sw	s5,0(tp) # 0 <_start>
+ 370:	0080a403          	lw	s0,8(ra)
+ 374:	0000a623          	sw	zero,12(ra)
+ 378:	fffffa37          	lui	s4,0xfffff
+ 37c:	dcca0a13          	addi	s4,s4,-564 # ffffedcc <_end+0xffffcbc8>
+ 380:	00c08193          	addi	gp,ra,12
+ 384:	83018193          	addi	gp,gp,-2000
+ 388:	7d41a823          	sw	s4,2000(gp)
+ 38c:	00c0a403          	lw	s0,12(ra)
+ 390:	0000a823          	sw	zero,16(ra)
+ 394:	fff00993          	li	s3,-1
+ 398:	01008113          	addi	sp,ra,16
+ 39c:	00110113          	addi	sp,sp,1
+ 3a0:	ff312fa3          	sw	s3,-1(sp)
+ 3a4:	0100a403          	lw	s0,16(ra)
+ 3a8:	00002117          	auipc	sp,0x2
+ 3ac:	cd010113          	addi	sp,sp,-816 # 2078 <test_7_res>
+ 3b0:	00012023          	sw	zero,0(sp)
+ 3b4:	80100913          	li	s2,-2047
+ 3b8:	00010093          	mv	ra,sp
+ 3bc:	00008093          	mv	ra,ra
+ 3c0:	0120a023          	sw	s2,0(ra)
+ 3c4:	00012203          	lw	tp,0(sp)
+ 3c8:	00012223          	sw	zero,4(sp)
+ 3cc:	ffe00893          	li	a7,-2
+ 3d0:	00410093          	addi	ra,sp,4
+ 3d4:	fff08093          	addi	ra,ra,-1
+ 3d8:	0110a0a3          	sw	a7,1(ra)
+ 3dc:	00412203          	lw	tp,4(sp)
+ 3e0:	00002297          	auipc	t0,0x2
+ 3e4:	c2028293          	addi	t0,t0,-992 # 2000 <begin_signature>
+ 3e8:	10000337          	lui	t1,0x10000
+ 3ec:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 3f0:	00532023          	sw	t0,0(t1)
+ 3f4:	00002297          	auipc	t0,0x2
+ 3f8:	c9c28293          	addi	t0,t0,-868 # 2090 <end_signature>
+ 3fc:	10000337          	lui	t1,0x10000
+ 400:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 404:	00532023          	sw	t0,0(t1)
+ 408:	00100293          	li	t0,1
+ 40c:	10000337          	lui	t1,0x10000
+ 410:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 414:	00532023          	sw	t0,0(t1)
+ 418:	00000013          	nop
+ 41c:	00100193          	li	gp,1
+ 420:	00000073          	ecall
+
+00000424 <end_testcode>:
+ 424:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf
new file mode 100644
index 0000000..5fe7e1b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.bin
new file mode 100644
index 0000000..b3dce17
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.objdump
new file mode 100644
index 0000000..4aa8432
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf.objdump
@@ -0,0 +1,339 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-XOR-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	00000813          	li	a6,0
+  90:	010fc033          	xor	zero,t6,a6
+  94:	0002a023          	sw	zero,0(t0)
+  98:	00100f13          	li	t5,1
+  9c:	80100793          	li	a5,-2047
+  a0:	00ff40b3          	xor	ra,t5,a5
+  a4:	0012a223          	sw	ra,4(t0)
+  a8:	00000e93          	li	t4,0
+  ac:	fff00713          	li	a4,-1
+  b0:	00eec133          	xor	sp,t4,a4
+  b4:	0022a423          	sw	sp,8(t0)
+  b8:	7ff00e13          	li	t3,2047
+  bc:	fffff6b7          	lui	a3,0xfffff
+  c0:	dcc68693          	addi	a3,a3,-564 # ffffedcc <_end+0xffffcbc8>
+  c4:	00de41b3          	xor	gp,t3,a3
+  c8:	0032a623          	sw	gp,12(t0)
+  cc:	00000d93          	li	s11,0
+  d0:	80000637          	lui	a2,0x80000
+  d4:	00cdc233          	xor	tp,s11,a2
+  d8:	0042a823          	sw	tp,16(t0)
+  dc:	00002097          	auipc	ra,0x2
+  e0:	f3808093          	addi	ra,ra,-200 # 2014 <test_2_res>
+  e4:	00001d37          	lui	s10,0x1
+  e8:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x4b4>
+  ec:	000015b7          	lui	a1,0x1
+  f0:	23458593          	addi	a1,a1,564 # 1234 <fromhost+0x134>
+  f4:	00bd42b3          	xor	t0,s10,a1
+  f8:	0050a023          	sw	t0,0(ra)
+  fc:	07654cb7          	lui	s9,0x7654
+ 100:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+ 104:	fff00513          	li	a0,-1
+ 108:	00acc333          	xor	t1,s9,a0
+ 10c:	0060a223          	sw	t1,4(ra)
+ 110:	80000c37          	lui	s8,0x80000
+ 114:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 118:	00100493          	li	s1,1
+ 11c:	009c43b3          	xor	t2,s8,s1
+ 120:	0070a423          	sw	t2,8(ra)
+ 124:	00100b93          	li	s7,1
+ 128:	80000437          	lui	s0,0x80000
+ 12c:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 130:	008bc433          	xor	s0,s7,s0
+ 134:	0080a623          	sw	s0,12(ra)
+ 138:	fff00b13          	li	s6,-1
+ 13c:	076543b7          	lui	t2,0x7654
+ 140:	32138393          	addi	t2,t2,801 # 7654321 <_end+0x765211d>
+ 144:	007b44b3          	xor	s1,s6,t2
+ 148:	0090a823          	sw	s1,16(ra)
+ 14c:	00002097          	auipc	ra,0x2
+ 150:	edc08093          	addi	ra,ra,-292 # 2028 <test_3_res>
+ 154:	00001ab7          	lui	s5,0x1
+ 158:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 15c:	00001337          	lui	t1,0x1
+ 160:	80030313          	addi	t1,t1,-2048 # 800 <end_testcode+0x4b4>
+ 164:	006ac533          	xor	a0,s5,t1
+ 168:	00a0a023          	sw	a0,0(ra)
+ 16c:	80000a37          	lui	s4,0x80000
+ 170:	00000293          	li	t0,0
+ 174:	005a45b3          	xor	a1,s4,t0
+ 178:	00b0a223          	sw	a1,4(ra)
+ 17c:	fffff9b7          	lui	s3,0xfffff
+ 180:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 184:	7ff00213          	li	tp,2047
+ 188:	0049c633          	xor	a2,s3,tp
+ 18c:	00c0a423          	sw	a2,8(ra)
+ 190:	fff00913          	li	s2,-1
+ 194:	fff00193          	li	gp,-1
+ 198:	003946b3          	xor	a3,s2,gp
+ 19c:	00d0a623          	sw	a3,12(ra)
+ 1a0:	80100893          	li	a7,-2047
+ 1a4:	00100113          	li	sp,1
+ 1a8:	0028c733          	xor	a4,a7,sp
+ 1ac:	00e0a823          	sw	a4,16(ra)
+ 1b0:	00002117          	auipc	sp,0x2
+ 1b4:	e8c10113          	addi	sp,sp,-372 # 203c <test_4_res>
+ 1b8:	00000813          	li	a6,0
+ 1bc:	00000093          	li	ra,0
+ 1c0:	001847b3          	xor	a5,a6,ra
+ 1c4:	00f12023          	sw	a5,0(sp)
+ 1c8:	fff00793          	li	a5,-1
+ 1cc:	00000013          	nop
+ 1d0:	0007c833          	xor	a6,a5,zero
+ 1d4:	01012223          	sw	a6,4(sp)
+ 1d8:	00100713          	li	a4,1
+ 1dc:	80100f93          	li	t6,-2047
+ 1e0:	01f748b3          	xor	a7,a4,t6
+ 1e4:	01112423          	sw	a7,8(sp)
+ 1e8:	00000693          	li	a3,0
+ 1ec:	fff00f13          	li	t5,-1
+ 1f0:	01e6c933          	xor	s2,a3,t5
+ 1f4:	01212623          	sw	s2,12(sp)
+ 1f8:	7ff00613          	li	a2,2047
+ 1fc:	fffffeb7          	lui	t4,0xfffff
+ 200:	dcce8e93          	addi	t4,t4,-564 # ffffedcc <_end+0xffffcbc8>
+ 204:	01d649b3          	xor	s3,a2,t4
+ 208:	01312823          	sw	s3,16(sp)
+ 20c:	00002097          	auipc	ra,0x2
+ 210:	e4408093          	addi	ra,ra,-444 # 2050 <test_5_res>
+ 214:	00000593          	li	a1,0
+ 218:	80000e37          	lui	t3,0x80000
+ 21c:	01c5ca33          	xor	s4,a1,t3
+ 220:	0140a023          	sw	s4,0(ra)
+ 224:	00001537          	lui	a0,0x1
+ 228:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x4b4>
+ 22c:	00001db7          	lui	s11,0x1
+ 230:	234d8d93          	addi	s11,s11,564 # 1234 <fromhost+0x134>
+ 234:	01b54ab3          	xor	s5,a0,s11
+ 238:	0150a223          	sw	s5,4(ra)
+ 23c:	076544b7          	lui	s1,0x7654
+ 240:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 244:	fff00d13          	li	s10,-1
+ 248:	01a4cb33          	xor	s6,s1,s10
+ 24c:	0160a423          	sw	s6,8(ra)
+ 250:	80000437          	lui	s0,0x80000
+ 254:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 258:	00100c93          	li	s9,1
+ 25c:	01944bb3          	xor	s7,s0,s9
+ 260:	0170a623          	sw	s7,12(ra)
+ 264:	00100393          	li	t2,1
+ 268:	80000c37          	lui	s8,0x80000
+ 26c:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+ 270:	0183cc33          	xor	s8,t2,s8
+ 274:	0180a823          	sw	s8,16(ra)
+ 278:	00002097          	auipc	ra,0x2
+ 27c:	dec08093          	addi	ra,ra,-532 # 2064 <test_6_res>
+ 280:	fff00313          	li	t1,-1
+ 284:	07654bb7          	lui	s7,0x7654
+ 288:	321b8b93          	addi	s7,s7,801 # 7654321 <_end+0x765211d>
+ 28c:	01734cb3          	xor	s9,t1,s7
+ 290:	0190a023          	sw	s9,0(ra)
+ 294:	000012b7          	lui	t0,0x1
+ 298:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 29c:	00001b37          	lui	s6,0x1
+ 2a0:	800b0b13          	addi	s6,s6,-2048 # 800 <end_testcode+0x4b4>
+ 2a4:	0162cd33          	xor	s10,t0,s6
+ 2a8:	01a0a223          	sw	s10,4(ra)
+ 2ac:	80000237          	lui	tp,0x80000
+ 2b0:	00000a93          	li	s5,0
+ 2b4:	01524db3          	xor	s11,tp,s5
+ 2b8:	01b0a423          	sw	s11,8(ra)
+ 2bc:	fffff1b7          	lui	gp,0xfffff
+ 2c0:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 2c4:	7ff00a13          	li	s4,2047
+ 2c8:	0141ce33          	xor	t3,gp,s4
+ 2cc:	01c0a623          	sw	t3,12(ra)
+ 2d0:	fff00113          	li	sp,-1
+ 2d4:	fff00993          	li	s3,-1
+ 2d8:	01314eb3          	xor	t4,sp,s3
+ 2dc:	01d0a823          	sw	t4,16(ra)
+ 2e0:	00002117          	auipc	sp,0x2
+ 2e4:	d9810113          	addi	sp,sp,-616 # 2078 <test_7_res>
+ 2e8:	80100093          	li	ra,-2047
+ 2ec:	00100913          	li	s2,1
+ 2f0:	0120cf33          	xor	t5,ra,s2
+ 2f4:	01e12023          	sw	t5,0(sp)
+ 2f8:	00000013          	nop
+ 2fc:	00000893          	li	a7,0
+ 300:	01104fb3          	xor	t6,zero,a7
+ 304:	01f12223          	sw	t6,4(sp)
+ 308:	00002297          	auipc	t0,0x2
+ 30c:	cf828293          	addi	t0,t0,-776 # 2000 <begin_signature>
+ 310:	10000337          	lui	t1,0x10000
+ 314:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 318:	00532023          	sw	t0,0(t1)
+ 31c:	00002297          	auipc	t0,0x2
+ 320:	d7428293          	addi	t0,t0,-652 # 2090 <end_signature>
+ 324:	10000337          	lui	t1,0x10000
+ 328:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 32c:	00532023          	sw	t0,0(t1)
+ 330:	00100293          	li	t0,1
+ 334:	10000337          	lui	t1,0x10000
+ 338:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 33c:	00532023          	sw	t0,0(t1)
+ 340:	00000013          	nop
+ 344:	00100193          	li	gp,1
+ 348:	00000073          	ecall
+
+0000034c <end_testcode>:
+ 34c:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf
new file mode 100644
index 0000000..87cdc14
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.bin b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.bin
new file mode 100644
index 0000000..4eddc45
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.objdump b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.objdump
new file mode 100644
index 0000000..299cdad
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf.objdump
@@ -0,0 +1,297 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32i/I-XORI-01.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002297          	auipc	t0,0x2
+  84:	f8028293          	addi	t0,t0,-128 # 2000 <begin_signature>
+  88:	fff00f93          	li	t6,-1
+  8c:	000fc013          	xori	zero,t6,0
+  90:	0002a023          	sw	zero,0(t0)
+  94:	00100f13          	li	t5,1
+  98:	801f4093          	xori	ra,t5,-2047
+  9c:	0012a223          	sw	ra,4(t0)
+  a0:	00000e93          	li	t4,0
+  a4:	fffec113          	not	sp,t4
+  a8:	0022a423          	sw	sp,8(t0)
+  ac:	7ff00e13          	li	t3,2047
+  b0:	800e4193          	xori	gp,t3,-2048
+  b4:	0032a623          	sw	gp,12(t0)
+  b8:	00000d93          	li	s11,0
+  bc:	800dc213          	xori	tp,s11,-2048
+  c0:	0042a823          	sw	tp,16(t0)
+  c4:	00002097          	auipc	ra,0x2
+  c8:	f5008093          	addi	ra,ra,-176 # 2014 <test_2_res>
+  cc:	00001d37          	lui	s10,0x1
+  d0:	800d0d13          	addi	s10,s10,-2048 # 800 <end_testcode+0x55c>
+  d4:	800d4293          	xori	t0,s10,-2048
+  d8:	0050a023          	sw	t0,0(ra)
+  dc:	07654cb7          	lui	s9,0x7654
+  e0:	321c8c93          	addi	s9,s9,801 # 7654321 <_end+0x765211d>
+  e4:	800cc313          	xori	t1,s9,-2048
+  e8:	0060a223          	sw	t1,4(ra)
+  ec:	80000c37          	lui	s8,0x80000
+  f0:	fffc0c13          	addi	s8,s8,-1 # 7fffffff <_end+0x7fffddfb>
+  f4:	001c4393          	xori	t2,s8,1
+  f8:	0070a423          	sw	t2,8(ra)
+  fc:	00100b93          	li	s7,1
+ 100:	800bc413          	xori	s0,s7,-2048
+ 104:	0080a623          	sw	s0,12(ra)
+ 108:	fff00b13          	li	s6,-1
+ 10c:	800b4493          	xori	s1,s6,-2048
+ 110:	0090a823          	sw	s1,16(ra)
+ 114:	00002097          	auipc	ra,0x2
+ 118:	f1408093          	addi	ra,ra,-236 # 2028 <test_3_res>
+ 11c:	00001ab7          	lui	s5,0x1
+ 120:	234a8a93          	addi	s5,s5,564 # 1234 <fromhost+0x134>
+ 124:	800ac513          	xori	a0,s5,-2048
+ 128:	00a0a023          	sw	a0,0(ra)
+ 12c:	80000a37          	lui	s4,0x80000
+ 130:	000a4593          	xori	a1,s4,0
+ 134:	00b0a223          	sw	a1,4(ra)
+ 138:	fffff9b7          	lui	s3,0xfffff
+ 13c:	dcc98993          	addi	s3,s3,-564 # ffffedcc <_end+0xffffcbc8>
+ 140:	7ff9c613          	xori	a2,s3,2047
+ 144:	00c0a423          	sw	a2,8(ra)
+ 148:	fff00913          	li	s2,-1
+ 14c:	fff94693          	not	a3,s2
+ 150:	00d0a623          	sw	a3,12(ra)
+ 154:	80100893          	li	a7,-2047
+ 158:	0018c713          	xori	a4,a7,1
+ 15c:	00e0a823          	sw	a4,16(ra)
+ 160:	00002117          	auipc	sp,0x2
+ 164:	edc10113          	addi	sp,sp,-292 # 203c <test_4_res>
+ 168:	00000813          	li	a6,0
+ 16c:	00084793          	xori	a5,a6,0
+ 170:	00f12023          	sw	a5,0(sp)
+ 174:	fff00793          	li	a5,-1
+ 178:	0007c813          	xori	a6,a5,0
+ 17c:	01012223          	sw	a6,4(sp)
+ 180:	00100713          	li	a4,1
+ 184:	80174893          	xori	a7,a4,-2047
+ 188:	01112423          	sw	a7,8(sp)
+ 18c:	00000693          	li	a3,0
+ 190:	fff6c913          	not	s2,a3
+ 194:	01212623          	sw	s2,12(sp)
+ 198:	7ff00613          	li	a2,2047
+ 19c:	80064993          	xori	s3,a2,-2048
+ 1a0:	01312823          	sw	s3,16(sp)
+ 1a4:	00002097          	auipc	ra,0x2
+ 1a8:	eac08093          	addi	ra,ra,-340 # 2050 <test_5_res>
+ 1ac:	00000593          	li	a1,0
+ 1b0:	8005ca13          	xori	s4,a1,-2048
+ 1b4:	0140a023          	sw	s4,0(ra)
+ 1b8:	00001537          	lui	a0,0x1
+ 1bc:	80050513          	addi	a0,a0,-2048 # 800 <end_testcode+0x55c>
+ 1c0:	80054a93          	xori	s5,a0,-2048
+ 1c4:	0150a223          	sw	s5,4(ra)
+ 1c8:	076544b7          	lui	s1,0x7654
+ 1cc:	32148493          	addi	s1,s1,801 # 7654321 <_end+0x765211d>
+ 1d0:	8004cb13          	xori	s6,s1,-2048
+ 1d4:	0160a423          	sw	s6,8(ra)
+ 1d8:	80000437          	lui	s0,0x80000
+ 1dc:	fff40413          	addi	s0,s0,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	00144b93          	xori	s7,s0,1
+ 1e4:	0170a623          	sw	s7,12(ra)
+ 1e8:	00100393          	li	t2,1
+ 1ec:	8003cc13          	xori	s8,t2,-2048
+ 1f0:	0180a823          	sw	s8,16(ra)
+ 1f4:	00002097          	auipc	ra,0x2
+ 1f8:	e7008093          	addi	ra,ra,-400 # 2064 <test_6_res>
+ 1fc:	fff00313          	li	t1,-1
+ 200:	80034c93          	xori	s9,t1,-2048
+ 204:	0190a023          	sw	s9,0(ra)
+ 208:	000012b7          	lui	t0,0x1
+ 20c:	23428293          	addi	t0,t0,564 # 1234 <fromhost+0x134>
+ 210:	8002cd13          	xori	s10,t0,-2048
+ 214:	01a0a223          	sw	s10,4(ra)
+ 218:	80000237          	lui	tp,0x80000
+ 21c:	00024d93          	xori	s11,tp,0
+ 220:	01b0a423          	sw	s11,8(ra)
+ 224:	fffff1b7          	lui	gp,0xfffff
+ 228:	dcc18193          	addi	gp,gp,-564 # ffffedcc <_end+0xffffcbc8>
+ 22c:	7ff1ce13          	xori	t3,gp,2047
+ 230:	01c0a623          	sw	t3,12(ra)
+ 234:	fff00113          	li	sp,-1
+ 238:	fff14e93          	not	t4,sp
+ 23c:	01d0a823          	sw	t4,16(ra)
+ 240:	00002117          	auipc	sp,0x2
+ 244:	e3810113          	addi	sp,sp,-456 # 2078 <test_7_res>
+ 248:	80100093          	li	ra,-2047
+ 24c:	0010cf13          	xori	t5,ra,1
+ 250:	01e12023          	sw	t5,0(sp)
+ 254:	00000013          	nop
+ 258:	00004f93          	xori	t6,zero,0
+ 25c:	01f12223          	sw	t6,4(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e1c28293          	addi	t0,t0,-484 # 2090 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+    208c:	0000                	unimp
+	...
+
+00002090 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIV.elf b/tests/riscv-compliance/build_generated/rv32im/DIV.elf
new file mode 100644
index 0000000..5a7ac37
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/DIV.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIV.elf.bin b/tests/riscv-compliance/build_generated/rv32im/DIV.elf.bin
new file mode 100644
index 0000000..8de3f3a
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/DIV.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIV.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/DIV.elf.objdump
new file mode 100644
index 0000000..9f7f66c
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/DIV.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/DIV.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031948b3          	div	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a49b3          	div	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b4ab3          	div	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c4bb3          	div	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d4cb3          	div	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be4db3          	div	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df4eb3          	div	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351cab3          	div	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02444233          	div	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295c4b3          	div	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6c633          	div	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7c733          	div	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308c833          	div	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329c933          	div	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034aca33          	div	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036bcb33          	div	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038ccc33          	div	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03adcd33          	div	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03cece33          	div	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eacf33          	div	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023241b3          	div	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284c433          	div	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b645b3          	div	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d746b3          	div	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f847b3          	div	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIVU.elf b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf
new file mode 100644
index 0000000..f39faf4
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.bin b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.bin
new file mode 100644
index 0000000..f8dd501
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.objdump
new file mode 100644
index 0000000..c64d83d
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/DIVU.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/DIVU.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031958b3          	divu	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a59b3          	divu	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b5ab3          	divu	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c5bb3          	divu	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d5cb3          	divu	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be5db3          	divu	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df5eb3          	divu	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351dab3          	divu	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02445233          	divu	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295d4b3          	divu	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6d633          	divu	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7d733          	divu	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308d833          	divu	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329d933          	divu	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034ada33          	divu	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036bdb33          	divu	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038cdc33          	divu	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03addd33          	divu	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03cede33          	divu	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eadf33          	divu	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023251b3          	divu	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284d433          	divu	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b655b3          	divu	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d756b3          	divu	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f857b3          	divu	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/MUL.elf b/tests/riscv-compliance/build_generated/rv32im/MUL.elf
new file mode 100644
index 0000000..9c48a02
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MUL.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MUL.elf.bin b/tests/riscv-compliance/build_generated/rv32im/MUL.elf.bin
new file mode 100644
index 0000000..ef30e3d
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MUL.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MUL.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/MUL.elf.objdump
new file mode 100644
index 0000000..3a364b6
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/MUL.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/MUL.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031908b3          	mul	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a09b3          	mul	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b0ab3          	mul	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c0bb3          	mul	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d0cb3          	mul	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be0db3          	mul	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df0eb3          	mul	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	03518ab3          	mul	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02440233          	mul	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	029584b3          	mul	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c68633          	mul	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e78733          	mul	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	03088833          	mul	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	03298933          	mul	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034a8a33          	mul	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036b8b33          	mul	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038c8c33          	mul	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03ad8d33          	mul	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03ce8e33          	mul	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03ea8f33          	mul	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023201b3          	mul	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	02848433          	mul	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b605b3          	mul	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d706b3          	mul	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f807b3          	mul	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULH.elf b/tests/riscv-compliance/build_generated/rv32im/MULH.elf
new file mode 100644
index 0000000..c1a6e4d
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULH.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULH.elf.bin b/tests/riscv-compliance/build_generated/rv32im/MULH.elf.bin
new file mode 100644
index 0000000..06c735b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULH.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULH.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/MULH.elf.objdump
new file mode 100644
index 0000000..272f6e0
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/MULH.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/MULH.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031918b3          	mulh	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a19b3          	mulh	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b1ab3          	mulh	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c1bb3          	mulh	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d1cb3          	mulh	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be1db3          	mulh	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df1eb3          	mulh	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	03519ab3          	mulh	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02441233          	mulh	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	029594b3          	mulh	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c69633          	mulh	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e79733          	mulh	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	03089833          	mulh	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	03299933          	mulh	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034a9a33          	mulh	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036b9b33          	mulh	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038c9c33          	mulh	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03ad9d33          	mulh	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03ce9e33          	mulh	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03ea9f33          	mulh	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023211b3          	mulh	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	02849433          	mulh	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b615b3          	mulh	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d716b3          	mulh	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f817b3          	mulh	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf
new file mode 100644
index 0000000..44b11f1
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.bin b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.bin
new file mode 100644
index 0000000..3daa04c
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.objdump
new file mode 100644
index 0000000..9df9e26
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/MULHSU.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031928b3          	mulhsu	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a29b3          	mulhsu	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b2ab3          	mulhsu	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c2bb3          	mulhsu	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d2cb3          	mulhsu	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be2db3          	mulhsu	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df2eb3          	mulhsu	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351aab3          	mulhsu	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02442233          	mulhsu	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295a4b3          	mulhsu	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6a633          	mulhsu	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7a733          	mulhsu	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308a833          	mulhsu	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329a933          	mulhsu	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034aaa33          	mulhsu	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036bab33          	mulhsu	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038cac33          	mulhsu	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03adad33          	mulhsu	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03ceae33          	mulhsu	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eaaf33          	mulhsu	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023221b3          	mulhsu	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284a433          	mulhsu	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b625b3          	mulhsu	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d726b3          	mulhsu	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f827b3          	mulhsu	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHU.elf b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf
new file mode 100644
index 0000000..3d32874
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.bin b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.bin
new file mode 100644
index 0000000..1dfa40c
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.objdump
new file mode 100644
index 0000000..fb964d3
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/MULHU.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/MULHU.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031938b3          	mulhu	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a39b3          	mulhu	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b3ab3          	mulhu	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c3bb3          	mulhu	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d3cb3          	mulhu	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be3db3          	mulhu	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df3eb3          	mulhu	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351bab3          	mulhu	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02443233          	mulhu	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295b4b3          	mulhu	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6b633          	mulhu	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7b733          	mulhu	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308b833          	mulhu	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329b933          	mulhu	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034aba33          	mulhu	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036bbb33          	mulhu	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038cbc33          	mulhu	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03adbd33          	mulhu	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03cebe33          	mulhu	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eabf33          	mulhu	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023231b3          	mulhu	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284b433          	mulhu	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b635b3          	mulhu	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d736b3          	mulhu	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f837b3          	mulhu	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/REM.elf b/tests/riscv-compliance/build_generated/rv32im/REM.elf
new file mode 100644
index 0000000..058781e
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/REM.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/REM.elf.bin b/tests/riscv-compliance/build_generated/rv32im/REM.elf.bin
new file mode 100644
index 0000000..014a2d8
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/REM.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/REM.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/REM.elf.objdump
new file mode 100644
index 0000000..7f010b6
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/REM.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/REM.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031968b3          	rem	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a69b3          	rem	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b6ab3          	rem	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c6bb3          	rem	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d6cb3          	rem	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be6db3          	rem	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df6eb3          	rem	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351eab3          	rem	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02446233          	rem	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295e4b3          	rem	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6e633          	rem	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7e733          	rem	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308e833          	rem	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329e933          	rem	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034aea33          	rem	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036beb33          	rem	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038cec33          	rem	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03aded33          	rem	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03ceee33          	rem	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eaef33          	rem	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023261b3          	rem	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284e433          	rem	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b665b3          	rem	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d766b3          	rem	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f867b3          	rem	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/build_generated/rv32im/REMU.elf b/tests/riscv-compliance/build_generated/rv32im/REMU.elf
new file mode 100644
index 0000000..d55880b
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/REMU.elf differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/REMU.elf.bin b/tests/riscv-compliance/build_generated/rv32im/REMU.elf.bin
new file mode 100644
index 0000000..0db6c20
Binary files /dev/null and b/tests/riscv-compliance/build_generated/rv32im/REMU.elf.bin differ
diff --git a/tests/riscv-compliance/build_generated/rv32im/REMU.elf.objdump b/tests/riscv-compliance/build_generated/rv32im/REMU.elf.objdump
new file mode 100644
index 0000000..86b7c12
--- /dev/null
+++ b/tests/riscv-compliance/build_generated/rv32im/REMU.elf.objdump
@@ -0,0 +1,332 @@
+
+D:/gitee/open/tinyriscv/tests/riscv-compliance/build_generated/rv32im/REMU.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	04c0006f          	j	4c <reset_vector>
+
+00000004 <trap_vector>:
+   4:	34202f73          	csrr	t5,mcause
+   8:	00800f93          	li	t6,8
+   c:	03ff0a63          	beq	t5,t6,40 <write_tohost>
+  10:	00900f93          	li	t6,9
+  14:	03ff0663          	beq	t5,t6,40 <write_tohost>
+  18:	00b00f93          	li	t6,11
+  1c:	03ff0263          	beq	t5,t6,40 <write_tohost>
+  20:	00000f17          	auipc	t5,0x0
+  24:	fe0f0f13          	addi	t5,t5,-32 # 0 <_start>
+  28:	000f0463          	beqz	t5,30 <trap_vector+0x2c>
+  2c:	000f0067          	jr	t5
+  30:	34202f73          	csrr	t5,mcause
+  34:	000f5463          	bgez	t5,3c <handle_exception>
+  38:	0040006f          	j	3c <handle_exception>
+
+0000003c <handle_exception>:
+  3c:	5391e193          	ori	gp,gp,1337
+
+00000040 <write_tohost>:
+  40:	00001f17          	auipc	t5,0x1
+  44:	fc3f2023          	sw	gp,-64(t5) # 1000 <tohost>
+  48:	ff9ff06f          	j	40 <write_tohost>
+
+0000004c <reset_vector>:
+  4c:	00000193          	li	gp,0
+  50:	00000297          	auipc	t0,0x0
+  54:	fb428293          	addi	t0,t0,-76 # 4 <trap_vector>
+  58:	30529073          	csrw	mtvec,t0
+  5c:	30005073          	csrwi	mstatus,0
+  60:	00000297          	auipc	t0,0x0
+  64:	02028293          	addi	t0,t0,32 # 80 <begin_testcode>
+  68:	34129073          	csrw	mepc,t0
+  6c:	00000293          	li	t0,0
+  70:	10000337          	lui	t1,0x10000
+  74:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+  78:	00532023          	sw	t0,0(t1)
+  7c:	30200073          	mret
+
+00000080 <begin_testcode>:
+  80:	00002117          	auipc	sp,0x2
+  84:	f8010113          	addi	sp,sp,-128 # 2000 <begin_signature>
+  88:	00000913          	li	s2,0
+  8c:	00000893          	li	a7,0
+  90:	031978b3          	remu	a7,s2,a7
+  94:	01112023          	sw	a7,0(sp)
+  98:	00000a13          	li	s4,0
+  9c:	00100993          	li	s3,1
+  a0:	033a79b3          	remu	s3,s4,s3
+  a4:	01312223          	sw	s3,4(sp)
+  a8:	00000b13          	li	s6,0
+  ac:	fff00a93          	li	s5,-1
+  b0:	035b7ab3          	remu	s5,s6,s5
+  b4:	01512423          	sw	s5,8(sp)
+  b8:	00000c13          	li	s8,0
+  bc:	80000bb7          	lui	s7,0x80000
+  c0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+  c4:	037c7bb3          	remu	s7,s8,s7
+  c8:	01712623          	sw	s7,12(sp)
+  cc:	00000d13          	li	s10,0
+  d0:	80000cb7          	lui	s9,0x80000
+  d4:	039d7cb3          	remu	s9,s10,s9
+  d8:	01912823          	sw	s9,16(sp)
+  dc:	00002117          	auipc	sp,0x2
+  e0:	f3810113          	addi	sp,sp,-200 # 2014 <test_2_res>
+  e4:	00100e13          	li	t3,1
+  e8:	00000d93          	li	s11,0
+  ec:	03be7db3          	remu	s11,t3,s11
+  f0:	01b12023          	sw	s11,0(sp)
+  f4:	00100f13          	li	t5,1
+  f8:	00100e93          	li	t4,1
+  fc:	03df7eb3          	remu	t4,t5,t4
+ 100:	01d12223          	sw	t4,4(sp)
+ 104:	00100193          	li	gp,1
+ 108:	fff00a93          	li	s5,-1
+ 10c:	0351fab3          	remu	s5,gp,s5
+ 110:	01512423          	sw	s5,8(sp)
+ 114:	00100413          	li	s0,1
+ 118:	80000237          	lui	tp,0x80000
+ 11c:	fff20213          	addi	tp,tp,-1 # 7fffffff <_end+0x7fffddfb>
+ 120:	02447233          	remu	tp,s0,tp
+ 124:	00412623          	sw	tp,12(sp)
+ 128:	00100593          	li	a1,1
+ 12c:	800004b7          	lui	s1,0x80000
+ 130:	0295f4b3          	remu	s1,a1,s1
+ 134:	00912823          	sw	s1,16(sp)
+ 138:	00002117          	auipc	sp,0x2
+ 13c:	ef010113          	addi	sp,sp,-272 # 2028 <test_3_res>
+ 140:	fff00693          	li	a3,-1
+ 144:	00000613          	li	a2,0
+ 148:	02c6f633          	remu	a2,a3,a2
+ 14c:	00c12023          	sw	a2,0(sp)
+ 150:	fff00793          	li	a5,-1
+ 154:	00100713          	li	a4,1
+ 158:	02e7f733          	remu	a4,a5,a4
+ 15c:	00e12223          	sw	a4,4(sp)
+ 160:	fff00893          	li	a7,-1
+ 164:	fff00813          	li	a6,-1
+ 168:	0308f833          	remu	a6,a7,a6
+ 16c:	01012423          	sw	a6,8(sp)
+ 170:	fff00993          	li	s3,-1
+ 174:	80000937          	lui	s2,0x80000
+ 178:	fff90913          	addi	s2,s2,-1 # 7fffffff <_end+0x7fffddfb>
+ 17c:	0329f933          	remu	s2,s3,s2
+ 180:	01212623          	sw	s2,12(sp)
+ 184:	fff00a93          	li	s5,-1
+ 188:	80000a37          	lui	s4,0x80000
+ 18c:	034afa33          	remu	s4,s5,s4
+ 190:	01412823          	sw	s4,16(sp)
+ 194:	00002117          	auipc	sp,0x2
+ 198:	ea810113          	addi	sp,sp,-344 # 203c <test_4_res>
+ 19c:	80000bb7          	lui	s7,0x80000
+ 1a0:	fffb8b93          	addi	s7,s7,-1 # 7fffffff <_end+0x7fffddfb>
+ 1a4:	00000b13          	li	s6,0
+ 1a8:	036bfb33          	remu	s6,s7,s6
+ 1ac:	01612023          	sw	s6,0(sp)
+ 1b0:	80000cb7          	lui	s9,0x80000
+ 1b4:	fffc8c93          	addi	s9,s9,-1 # 7fffffff <_end+0x7fffddfb>
+ 1b8:	00100c13          	li	s8,1
+ 1bc:	038cfc33          	remu	s8,s9,s8
+ 1c0:	01812223          	sw	s8,4(sp)
+ 1c4:	80000db7          	lui	s11,0x80000
+ 1c8:	fffd8d93          	addi	s11,s11,-1 # 7fffffff <_end+0x7fffddfb>
+ 1cc:	fff00d13          	li	s10,-1
+ 1d0:	03adfd33          	remu	s10,s11,s10
+ 1d4:	01a12423          	sw	s10,8(sp)
+ 1d8:	80000eb7          	lui	t4,0x80000
+ 1dc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e0:	80000e37          	lui	t3,0x80000
+ 1e4:	fffe0e13          	addi	t3,t3,-1 # 7fffffff <_end+0x7fffddfb>
+ 1e8:	03cefe33          	remu	t3,t4,t3
+ 1ec:	01c12623          	sw	t3,12(sp)
+ 1f0:	80000ab7          	lui	s5,0x80000
+ 1f4:	fffa8a93          	addi	s5,s5,-1 # 7fffffff <_end+0x7fffddfb>
+ 1f8:	80000f37          	lui	t5,0x80000
+ 1fc:	03eaff33          	remu	t5,s5,t5
+ 200:	01e12823          	sw	t5,16(sp)
+ 204:	00002117          	auipc	sp,0x2
+ 208:	e4c10113          	addi	sp,sp,-436 # 2050 <test_5_res>
+ 20c:	80000237          	lui	tp,0x80000
+ 210:	00000193          	li	gp,0
+ 214:	023271b3          	remu	gp,tp,gp
+ 218:	00312023          	sw	gp,0(sp)
+ 21c:	800004b7          	lui	s1,0x80000
+ 220:	00100413          	li	s0,1
+ 224:	0284f433          	remu	s0,s1,s0
+ 228:	00812223          	sw	s0,4(sp)
+ 22c:	80000637          	lui	a2,0x80000
+ 230:	fff00593          	li	a1,-1
+ 234:	02b675b3          	remu	a1,a2,a1
+ 238:	00b12423          	sw	a1,8(sp)
+ 23c:	80000737          	lui	a4,0x80000
+ 240:	800006b7          	lui	a3,0x80000
+ 244:	fff68693          	addi	a3,a3,-1 # 7fffffff <_end+0x7fffddfb>
+ 248:	02d776b3          	remu	a3,a4,a3
+ 24c:	00d12623          	sw	a3,12(sp)
+ 250:	80000837          	lui	a6,0x80000
+ 254:	800007b7          	lui	a5,0x80000
+ 258:	02f877b3          	remu	a5,a6,a5
+ 25c:	00f12823          	sw	a5,16(sp)
+ 260:	00002297          	auipc	t0,0x2
+ 264:	da028293          	addi	t0,t0,-608 # 2000 <begin_signature>
+ 268:	10000337          	lui	t1,0x10000
+ 26c:	00830313          	addi	t1,t1,8 # 10000008 <_end+0xfffde04>
+ 270:	00532023          	sw	t0,0(t1)
+ 274:	00002297          	auipc	t0,0x2
+ 278:	e5c28293          	addi	t0,t0,-420 # 20d0 <end_signature>
+ 27c:	10000337          	lui	t1,0x10000
+ 280:	00c30313          	addi	t1,t1,12 # 1000000c <_end+0xfffde08>
+ 284:	00532023          	sw	t0,0(t1)
+ 288:	00100293          	li	t0,1
+ 28c:	10000337          	lui	t1,0x10000
+ 290:	01030313          	addi	t1,t1,16 # 10000010 <_end+0xfffde0c>
+ 294:	00532023          	sw	t0,0(t1)
+ 298:	00000013          	nop
+ 29c:	00100193          	li	gp,1
+ 2a0:	00000073          	ecall
+
+000002a4 <end_testcode>:
+ 2a4:	c0001073          	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001000 <tohost>:
+	...
+
+00001100 <fromhost>:
+	...
+
+Disassembly of section .data:
+
+00002000 <begin_signature>:
+    2000:	ffff                	0xffff
+    2002:	ffff                	0xffff
+    2004:	ffff                	0xffff
+    2006:	ffff                	0xffff
+    2008:	ffff                	0xffff
+    200a:	ffff                	0xffff
+    200c:	ffff                	0xffff
+    200e:	ffff                	0xffff
+    2010:	ffff                	0xffff
+    2012:	ffff                	0xffff
+
+00002014 <test_2_res>:
+    2014:	ffff                	0xffff
+    2016:	ffff                	0xffff
+    2018:	ffff                	0xffff
+    201a:	ffff                	0xffff
+    201c:	ffff                	0xffff
+    201e:	ffff                	0xffff
+    2020:	ffff                	0xffff
+    2022:	ffff                	0xffff
+    2024:	ffff                	0xffff
+    2026:	ffff                	0xffff
+
+00002028 <test_3_res>:
+    2028:	ffff                	0xffff
+    202a:	ffff                	0xffff
+    202c:	ffff                	0xffff
+    202e:	ffff                	0xffff
+    2030:	ffff                	0xffff
+    2032:	ffff                	0xffff
+    2034:	ffff                	0xffff
+    2036:	ffff                	0xffff
+    2038:	ffff                	0xffff
+    203a:	ffff                	0xffff
+
+0000203c <test_4_res>:
+    203c:	ffff                	0xffff
+    203e:	ffff                	0xffff
+    2040:	ffff                	0xffff
+    2042:	ffff                	0xffff
+    2044:	ffff                	0xffff
+    2046:	ffff                	0xffff
+    2048:	ffff                	0xffff
+    204a:	ffff                	0xffff
+    204c:	ffff                	0xffff
+    204e:	ffff                	0xffff
+
+00002050 <test_5_res>:
+    2050:	ffff                	0xffff
+    2052:	ffff                	0xffff
+    2054:	ffff                	0xffff
+    2056:	ffff                	0xffff
+    2058:	ffff                	0xffff
+    205a:	ffff                	0xffff
+    205c:	ffff                	0xffff
+    205e:	ffff                	0xffff
+    2060:	ffff                	0xffff
+    2062:	ffff                	0xffff
+
+00002064 <test_6_res>:
+    2064:	ffff                	0xffff
+    2066:	ffff                	0xffff
+    2068:	ffff                	0xffff
+    206a:	ffff                	0xffff
+    206c:	ffff                	0xffff
+    206e:	ffff                	0xffff
+    2070:	ffff                	0xffff
+    2072:	ffff                	0xffff
+    2074:	ffff                	0xffff
+    2076:	ffff                	0xffff
+
+00002078 <test_7_res>:
+    2078:	ffff                	0xffff
+    207a:	ffff                	0xffff
+    207c:	ffff                	0xffff
+    207e:	ffff                	0xffff
+    2080:	ffff                	0xffff
+    2082:	ffff                	0xffff
+    2084:	ffff                	0xffff
+    2086:	ffff                	0xffff
+    2088:	ffff                	0xffff
+    208a:	ffff                	0xffff
+
+0000208c <test_8_res>:
+    208c:	ffff                	0xffff
+    208e:	ffff                	0xffff
+    2090:	ffff                	0xffff
+    2092:	ffff                	0xffff
+    2094:	ffff                	0xffff
+    2096:	ffff                	0xffff
+    2098:	ffff                	0xffff
+    209a:	ffff                	0xffff
+    209c:	ffff                	0xffff
+    209e:	ffff                	0xffff
+
+000020a0 <test_9_res>:
+    20a0:	ffff                	0xffff
+    20a2:	ffff                	0xffff
+    20a4:	ffff                	0xffff
+    20a6:	ffff                	0xffff
+    20a8:	ffff                	0xffff
+    20aa:	ffff                	0xffff
+    20ac:	ffff                	0xffff
+    20ae:	ffff                	0xffff
+    20b0:	ffff                	0xffff
+    20b2:	ffff                	0xffff
+
+000020b4 <test_10_res>:
+    20b4:	ffff                	0xffff
+    20b6:	ffff                	0xffff
+    20b8:	ffff                	0xffff
+    20ba:	ffff                	0xffff
+    20bc:	ffff                	0xffff
+    20be:	ffff                	0xffff
+    20c0:	ffff                	0xffff
+    20c2:	ffff                	0xffff
+    20c4:	ffff                	0xffff
+    20c6:	ffff                	0xffff
+	...
+
+000020d0 <end_signature>:
+	...
+
+00002100 <begin_regstate>:
+    2100:	0080                	addi	s0,sp,64
+	...
+
+00002200 <end_regstate>:
+    2200:	0004                	0x4
+	...
diff --git a/tests/riscv-compliance/doc/.gitignore b/tests/riscv-compliance/doc/.gitignore
new file mode 100644
index 0000000..70954a1
--- /dev/null
+++ b/tests/riscv-compliance/doc/.gitignore
@@ -0,0 +1,6 @@
+# Ignore editor backups
+*~
+# Generated files
+custom.dict
+README.pdf
+README.html
\ No newline at end of file
diff --git a/tests/riscv-compliance/doc/ChangeLog b/tests/riscv-compliance/doc/ChangeLog
new file mode 100644
index 0000000..6b40841
--- /dev/null
+++ b/tests/riscv-compliance/doc/ChangeLog
@@ -0,0 +1,147 @@
+2019-02-21  Deborah Soung  <debs@sifive.com>
+	* README.adoc: Documentation for rocket chip as target.
+
+2019-02-05  Deborah Soung  <debs@sifive.com>
+	* README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S).
+	* README.adoc: Update documentation for rocket chip as target (fixed breakpoint.S).
+
+2019-01-29  Deborah Soung  <debs@sifive.com>
+	* README.adoc: Documentation for rocket chip as target.
+
+2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
+
+	* README.adoc (Repository structure) Added documentation for the $TARGETDIR environmental variable
+
+2018-11-21  Neel Gala  <neelgala@incoresemi.com>
+	* README.adoc: Added new signature format spec.
+
+2018-06-18  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.adoc (Future work): Reflect changes made to support
+	Codasip simulator.
+	(Repository structure): Diagrammatic representation of the file
+	structure deleted.
+
+2018-06-12  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* .gitignore: Add custom.dict.
+
+2018-06-12  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	Document issue 1.8 Draft.
+
+	* README.adoc (Introduction): Add Future work section and bump
+	version.
+	* custom.wordlist: Add words needed for Future work section.
+
+2018-06-12  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.adoc: Remove special apostrophe from "licensor's".
+	* custom.wordlist: Updated with more words to be ignored.
+
+2018-06-12  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README-old.md: Deleted.
+	* README.adoc: Include details of how to contribute and installing
+	the tools from the old README and reference the licence as an
+	appendix.
+
+2018-06-11  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	This makes the document appear directly as the README of the doc
+	directory, so there is now no longer a need to publish to GitHub
+	pages.
+
+	* .gitignore: Change name of files ignored.
+	* Makefile: Remove publish target.
+	* README.adoc: Symbolic link removed and replaced by design.adoc,
+	to which the CC license text has been added.
+	* design.adoc: Renamed as README.adoc.
+	* publish.sh: Deleted.
+
+2018-06-11  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Previous version moved to README-old.md for the time
+	being.
+	* README.adoc: Created as symbolic link to design.adoc.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Note about make publish.
+	* design.adoc (Overall structure): Make list or instruction sets
+	and extensions compact representation.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* publish.sh: Only publish from clean and committed master branch
+	to avoid difficult use of git stash.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* publish.sh: Don't rely on doc directory being available on
+	gh-pages branch.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* publish.sh: Make executable and correctly set top level
+	repository directory.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	Add a mechanism to make the latest documentation available via
+	GitHub pages.  This means that design.html is no longer part of
+	the master branch, but is published by copying to index.html on
+	the gh-pages branch.
+
+	* .gitignore: Ignore design.html.
+	* Makefile: Add publish target and delete design.html when cleaning.
+	* README.md: Link to GitHub pages for latest documentation.
+	* design.adoc: Deal with AsciiDoc apparent bug with consecutive
+	comment blogs.
+	* design.html: Deleted.
+	* publish.sh: Created.
+
+2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* README.md: Fix link to generated documentation.
+	* design.html: Regenerated.
+
+2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* Makefile: Add sanity check for version number and spell target.
+	* design.adoc: Fix trivial typo.
+	* design.html: Regenerated.
+
+2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* .gitignore: Don't ignore .html or .xml
+	* README.md: Note location of old documentation, give link to HTML
+	and explain how to contribute.
+	* custom.wordlist: Created.
+	* design.adoc: Cleaned up from top to bottom and spell checked.
+	* design.html: Generated.
+
+2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* Makefile: Clean up and add license header.
+	* README.md: Created.
+	* design.adoc: Add licensing and SPDX license identifier.
+	* legacy.adoc: Deleted.
+
+2018-06-04  Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	This is the first version of the document taken from Simon
+	Davidmann's MS Word document. The main document is design.adoc,
+	legacy material, currently just appendices C and D has been moved
+	to legacy.adoc.
+
+	design.adoc is correct AsciiDoc.  legacy.adoc is just a raw dump,
+	which needs cleaning up.
+
+	The next step will be restructuring design.adoc as agreed.
+
+	* .gitignore: Created.
+	* ChangeLog: Created.
+	* Makefile: Created.
+	* design.adoc: Created.
+	* legacy.adoc: Created.
diff --git a/tests/riscv-compliance/doc/Makefile b/tests/riscv-compliance/doc/Makefile
new file mode 100644
index 0000000..f6ac46c
--- /dev/null
+++ b/tests/riscv-compliance/doc/Makefile
@@ -0,0 +1,82 @@
+# Makefile for RISC-V Compliance Task Group documentation
+
+# This file is part of the RISC-V Foundation Compliance Task Group compliance
+# tool set and documentation.
+
+# Copyright (C) 2017 CodaSip Limited <www.codasip.com>
+# Copyright (C) 2018 Embecosm Limited <www.embecosm.com>.
+# Copyright (C) 2018 Imperas Limited <www.imperas.com>
+
+# All rights reserved.
+
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+# 3. Neither the name of mosquitto nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+# SPDX-License-Identifier: BSD-3-Clause
+
+ROOT = README
+SRC = $(ROOT).adoc
+SRC_STRIPPED = $(ROOT)-stripped.adoc
+
+.PHONY: all
+all: pdf html
+
+.PHONY: pdf
+pdf: $(ROOT).pdf
+
+$(ROOT).pdf: sanity-check $(SRC)
+	asciidoctor-pdf -d article $(SRC)
+
+.PHONY: html
+html: $(ROOT).html
+
+$(ROOT).html: sanity-check $(SRC)
+	asciidoctor -d article -b html $(SRC)
+
+# It is all too easy for the document history and title page to have diverging
+# version numbers.  This target checks first.
+
+.PHONY: sanity-check
+sanity-check:
+	@s=$$(sed -n < $(SRC) -e '3s/Issue //p') ; \
+	t=$$(sed -n < $(SRC) -e "/== Document history/,/^$$/p" | \
+	           grep -c "$${s}") ; \
+	if [ $${t} -ne 1 ] ; \
+	then \
+	    echo "Version number of title and document history do not match" ; \
+	    exit 1 ; \
+	fi
+
+custom.dict: custom.wordlist
+	aspell --lang=en create master ./$@ < $<
+
+.PHONY: spell
+spell: custom.dict $(SRC)
+	sed < $(SRC) > $(SRC_STRIPPED) -e 's/`[^`]\+`//gp' -e '/^----$$/,/^----$$/d'
+	aspell --master=en_US --mode=none --add-extra-dicts=./custom.dict \
+	    -c $(SRC_STRIPPED)
+	$(RM) $(SRC_STRIPPED)
+
+clean:
+	rm -f $(ROOT)-stripped.adoc $(ROOT).pdf $(ROOT).html custom.dict
diff --git a/tests/riscv-compliance/doc/README.adoc b/tests/riscv-compliance/doc/README.adoc
new file mode 100644
index 0000000..47150bb
--- /dev/null
+++ b/tests/riscv-compliance/doc/README.adoc
@@ -0,0 +1,646 @@
+= RISC-V Compliance Tests =
+RISC-V Foundation Compliance Task Group
+Issue 1.15 Draft
+:toc:
+:icons: font
+:numbered:
+:source-highlighter: rouge
+
+////
+SPDX-License-Identifier: CC-BY-4.0
+
+Document conventions:
+- one line per paragraph (don't fill lines - this makes changes clearer)
+- Wikipedia heading conventions (First word only capitalized)
+- US spelling throughout.
+- Run "make spell" before committing changes.
+- Build the HTML and commit it with any changed source.
+- Do not commit the PDF!
+////
+
+== Introduction
+=== About
+
+This document describes the RISC-V Compliance Testing framework which is used to test a RISC-V device's compliance  to the different RISC-V specifications.
+
+* It explains the required structure of a test, the framework around the tests, the running of individual tests, and the suites of tests.
+
+* It includes, as reference, details of the first suite of tests for the RV32I and their reference signatures.
+
+* It explains how to set up different targets to run the tests.
+
+* It is an expansion of the work carried out by Codasip in the second half of 2017.
+
+This document is made freely available under a <<app_cc_by_4.0>>.
+
+=== Purpose of compliance tests
+
+The goal of compliance tests is to check whether the processor under development meets the open RISC-V standards or not. It is considered as non-functional testing meaning that it doesn’t substitute for design verification. This can be interpreted as testing to check all important aspects of the specification but without focusing on details, for example, on all possible values of instruction operands or all combinations of possible registers.
+
+The result that compliance tests provide to the user is an assurance that the specification has been interpreted correctly and the design under test (DUT) can be declared as RISC-V compliant.
+
+=== Intended audience
+
+This document is intended for design and verification engineers who wish to develop new compliance tests and also those who wish check if their implementation (simulation models, HDL models, etc.) of a RISC-V processor is compliant to the RISC-V specifications.
+
+=== Future work
+
+This is a work in progress. A number of areas need resolving before the work is complete, and are recorded here so they do not get forgotten.
+
+Consider whether `compliance_test.h` is needed :: It's not clear if this belongs in target directories, or if it is needed at all.
+
+Generalize Makefile configuration :: At present each platform requires editing of the makefile, and many areas are not even fully parameterized.  Again we wish to explore a wider range of platforms before deciding what needs parameterization.  For now `COMPILE_TARGET` allows a choice between GCC and LLVM.  More generally, we know that with tools like _autotools_ and _cmake_ this is a well understood problem to solve.
+
+Free up all registers for compliance testing :: At present some platforms have macros which use some registers in set up and verification, thus excluding them from compliance testing. We believe careful structuring of the macros will mean this problem can be avoided in the future, thus avoiding any registers being excluded from compliance testing.
+
+=== Feedback and how to contribute
+
+Comments on this document should be made through the RISC-V Compliance Task Group mailing list. Proposed changes may be submitted as git pull requests.
+
+You are encouraged to contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory.
+
+NOTE: Don't forget to add your own name to the list of contributors in the document.
+
+==== AsciiDoc
+
+This is a structured text format used by this document.  Simple usage should be fairly self evident.
+
+* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website].
+
+* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website].
+
+* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful.
+
+==== Installing tools
+
+To generate the documentation as HTML you need _asciidoctor_ and to generate as
+PDF you need _asciidoctor-pdf_.
+
+* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor].
+
+* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf].
+
+To spell check you need _aspell_ installed.
+
+==== Building the documentation
+
+To build HTML:
+[source,make]
+----
+make html
+----
+
+To build PDF:
+[source,make]
+----
+make pdf
+----
+
+To build both:
+[source,make]
+----
+make
+----
+
+To check the spelling (excludes any listing or code phrases):
+[source,make]
+----
+make spell
+----
+
+Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`].
+
+=== Contributors
+
+This document has been created by the following people (in alphabetical order of surname).
+
+[quote]
+Jeremy Bennett, Mary Bennett, Simon Davidmann, Neel Gala, Radek Hajek, Lee Moore, Milan Nostersky, Marcela Zachariasova.
+
+=== Document history
+[cols="<1,<2,<3,<4",options="header,pagewidth",]
+|================================================================================
+| _Revision_ | _Date_            | _Author_ | _Modification_
+| 1.15 Draft | 14 March 2019     |
+Prashanth Mundkur |
+
+Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
+| 1.14 Draft  | 21 February 2019      |
+Deborah Soung |
+
+Documented how to use SiFive's RISC-V ISA Formal Specification model as a target.
+| 1.13 Draft  | 29 January 2019      |
+Deborah Soung |
+
+Added documentation on how to use Rocket Chip generated cores as targets.
+| 1.12 Draft  | 22 November 2018      |
+Simon Davidmann |
+
+Updated notes on Test Suites.
+| 1.11 Draft  | 21 November 2018      |
+Neel Gala |
+
+Added new signature format specs .
+| 1.10 Draft  | 20 June 2018      |
+
+Simon Davidmann, Lee Moore |
+
+Cleaned up description of updated framework and inclusion of riscvOVPsim.
+
+| 1.9 Draft  | 12 June 2018      |
+
+Jeremy Bennett |
+
+Update Future work section to take account of Codasip changes. Remove diagrammatic directory structure.
+
+| 1.8 Draft  | 12 June 2018      |
+
+Jeremy Bennett |
+
+Add Future work section.
+
+| 1.7 Draft  | 12 June 2018      |
+
+Jeremy Bennett |
+
+Add CC license as an appendix.
+
+| 1.6 Draft  | 10 June 2018      |
+
+Jeremy Bennett |
+
+Tidy up areas that are flawed in HTML version.
+
+| 1.5 Draft  |  8 June 2018      |
+
+Jeremy Bennett |
+
+General tidy up.
+
+| 1.4 Draft  |  8 June 2018      |
+
+Jeremy Bennett |
+
+Added license preamble.
+
+| 1.3 Draft  |  5 June 2018      |
+
+Simon Davidmann |
+
+Updated to reflect directory structure and trace macros.
+
+| 1.2 Draft  |  3 June 2018      |
+
+Jeremy Bennett |
+
+Converted to AsciiDoc, cleaned up and restructured.
+
+| 1.1 Draft  |  1 June 2018      |
+
+Simon Davidmann
+Lee Moore |
+
+Revised format and expand to describe framework, usage of many tests groups,
+and different Targets
+
+|1.0         | 24 December 2017  |
+
+Radek Hajek
+Milan Nostersky
+Marcela Zachariasova |
+
+First version of the document.
+
+|================================================================================
+
+== Overall structure
+=== The compliance test
+
+At the heart of the testing infrastructure is the detailed compliance test.  This is the RISC-V assembler code that is executed on the processor and that provides results in a defined memory area (the _signature_).  The test should only use the minimum of instructions and only those absolutely necessary.  It should only use instructions and registers from the ISA instruction set on which it is targeted.
+
+=== The Test Virtual Machine
+
+The test runs in the context of a _Test Virtual Machine_ (TVM) as defined and available at https://github.com/riscv/riscv-tests. There will be a different TVM for each instruction subset and each profile.
+
+=== The target environment
+
+A specific target will need to be chosen and setup to run the Test. This can be an Instruction Set Simulator (ISS), full system simulator (emulator), HDL simulator, FPGA prototype, or a board/chip, etc.  The test runs in the context of a TVM and is set up to run on the specific target.  The _target environment_ controls the loading of the test plus TVM onto the target, configures the device if needed, controls the execution, and then extracts the signature.
+
+=== The processor configuration (device configuration)
+
+The RISC-V specification allows many optional instructions, registers, and other features.  Many targets have a fixed selection of these optional items which cannot be changed. For example, a chip is fixed in the mask.  A simulator on the other hand may implement all known options and will need to be constrained to have only the required options available.  There will need to be processor configuration for those target devices which need to be constrained to only reflect the features of the device being compliance tested. This is essential when writing compliance tests to ensure that only available options are used in the tests.
+
+=== The test signature
+
+The _test signature_ is defined as reference data written into memory during the execution of the test.  It should record values and results of the operation of the Test. It is expected that an implementation, at the end of a test, dumps the signature in to a file such that only 4-bytes are written per line, starting with the most-significant byte on the left.
+
+=== The test reference signature
+
+The _test reference signature_ is the _test signature_ saved from an execution run of the RISC‑V _golden model_.  This is currently from a RISC-V ISS, but the intention is that the RISC-V Formal Model from the RISCV.org Formal Working Group will be used when it is complete, functional, and available. 
+
+=== The test suites
+
+Tests are grouped into different functional test suites targeting the different subsets of the full RISC-V specifications.  There will be ISA and privilege suites.
+
+For information on the status of the different test suites, look here: link:../riscv-test-suite/README.md[../riscv-test-suite/README.md]
+
+
+=== The test framework
+
+This works at several levels.  At the lowest level it runs a test with a TVM on a specific configured target device and compares the test’s output test signature against the test reference signature and reports if there is any difference. A difference indicates that the target has failed that specific compliance test.
+
+The test framework allows different test suites to be run depending on the capabilities of the target
+
+The test framework collates the results of all the Tests that comprise a Test Suite and reports the overall results.
+
+== Developing new tests
+=== Structure
+
+* Clone directory structure of an existing test suite alongside the RV32I tree.
+
+* This must include test and reference signature directories (`src` and `references`).
+
+* Check the target environment setup files.
+
+* Check the processor configuration files.
+
+=== Process
+
+This description assumes the use of a configurable simulator with good trace and debug capabilities.
+
+* Work on one test at a time.
+
+* Ensure that the processor configuration is set appropriately.
+
+* Use the `RVTEST` macros (defined in `compliance_io.h`) to make it easy to see the details of a Test’s execution. There are macros for assertions (`RVTEST_IO_ASSERT_GPR_EQ`) and tracing (`RVTEST_IO_WRITE_STR`) which are empty on targets that can not implement them.
+
+* Assuming you are developing the test on a simulator, use the simulator’s tracing capabilities, especially a register change mode to single step your test examining all changing registers etc. to ensure your test is stimulating what is intending.
+
+* Make sure that the signature you generate at the end of the run shows adequate internal test state such that any checks do report as fails if wrong.
+
+* When you are satisfied that the test does what is intended and that the test signature is correct, copy this into a test reference signature (in the references directory).
+
+For a test suite to be complete it needs to have tests that exercise the full functionality of what it is intended to test. There are tools available to measure instruction and other resource coverage. These should be used to ensure that 100% of the intended instructions have been tested.
+
+== Test framework
+
+For running compliance tests, the Test Virtual Machine (TVM) “p” available at https://github.com/riscv/riscv-tests is utilized.
+
+In addition to using the basic functionality of the TVM, the script for running compliance tests runs the test on the target and then performs comparison of the target’s generated test signature to the manually reviewed test reference signature.
+
+See the chapter below for selecting and setting up the target (simulator, or hardware, etc.).
+
+If using a target that requires the processor to be configured, see the chapter below on processor configuration.
+
+You will also need to have a suitable compiler tool chain (GCC or LLVM) installed in your environment and available on your path.
+
+Tests are run by commands in the top level `Makefile` which has targets for simulate and verify
+
+[source,make]
+----
+RISCV_TARGET ?= riscvOVPsim
+RISCV_DEVICE ?= rv32i
+RISCV_PREFIX ?= riscv64-unknown-elf-
+
+simulate:
+        make RISCV_TARGET=$(RISCV_TARGET) \
+             RISCV_DEVICE=$(RISCV_DEVICE) \
+             RISCV_PREFIX=$(RISCV_PREFIX) \
+             run -C $(SUITEDIR)
+
+verify:
+    riscv-test-env/verify.sh
+----
+
+== Setting the target environment
+
+The target environment needs setting up to allow the compliance tests to be run on the target.  This can be used while developing compliance test suites or it can be used with new targets to see if they correctly execute the compliance test suites and are compliant!
+
+This chapter provides information on the currently available targets and includes a short tutorial on how to add a new target.
+
+== Support for parallel make
+
+In order to speed compilation and execution runs, make can be run in parallel using options to control parallelism.
+
+Two variables are of importance here PARALLEL=<0|1> and JOBS=<-jX --max-load=Y> whereby X and Y are integer values
+
+Additionally the target selected, must be coded in such a way to support parallel execution, unfortunately some targets use common intermediate files, rather than unique files, this makes them unsuitable for parallel execution, these targets will need to be re-coded.
+
+At the moment the riscvOVPsim target will support parallel execution by default, and will select the options -j8 --max-load=4 - these can be overridden either by disable (PARALLEL=0), or redefinition JOBS="-j2 --max-load=2"
+
+=== Imperas riscvOVPsim compliance simulator
+
+For tracing the test the following  macros are defined in `riscv-target/riscvOVPsim/compliance_io.h`:
+
+[source,make]
+----
+RVTEST_IO_INIT
+RVTEST_IO_WRITE_STR(_SP, _STR)
+RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+----
+
+An example of a test that uses the tracing macros is `riscv-test-suite/rv32i/ISA/src/I-IO.S`.
+
+To configure the simulator for different target devices there needs to be a Makefile fragment in the `device` directory.
+
+The Makefile fragment for RV32I is in `riscv-target/riscvOVPsim/device/rv32i`
+
+In the top level Makefile there needs to be a selection for the target and device:
+[source,make]
+----
+RISCV_TARGET?=riscvOVPsim
+RISCV_DEVICE?=rv32i
+----
+
+The path to the RUN_TARGET is defined within the riscv-target Makefile.include.
+
+
+=== Codasip ISA simulator
+
+tbd
+
+=== GNU CGEN ISS
+==== Within GDB
+
+tbd
+
+==== Via GDB Remote Serial Protocol
+
+tbd
+
+=== Berkeley Spike ISA simulator
+For spike the file `riscv-target/spike/compliance_io.h` has the trace macros defined as empty.  The Makefile fragment in `riscv-target/spike/device/rv32i` has the spike run command for the RV32I device.
+
+=== Berkeley Rocket Chip emulators
+Additional environment variables:
+
+* `ROCKET_DIR`: Specifies link:https://github.com/freechipsproject/rocket-chip[Rocket Chip] directory. Required.
+* `ROCKET_CONFIG`: Specifies Rocket Chip link:https://github.com/freechipsproject/rocket-chip/blob/master/src/main/scala/system/Configs.scala[configuration]. **Usually** defaults to `DefaultConfig` or `DefaultRV32Config`, unless the aforementioned configurations do not support a test suite's ISA extensions (for example, in the case of `rv32ud`).
+
+Before running the compliance test, make sure that the correct emulator is built, following the link:https://github.com/freechipsproject/rocket-chip#emulator[instructions in the Rocket Chip repository].
+
+**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following test — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S].
+
+=== SiFive RISC-V ISA Formal Specification
+Additional environment variables:
+
+* `FORMALSPEC_DIR`: Specifies link:https://github.com/sifive/RiscvSpecFormal[formal specification] directory. Required.
+
+Build the link:https://github.com/sifive/RiscvSpecFormal[formal model] before running compliance tests. The model currently supports `RV32i` with `a`, `c`, and `f` extensions.
+
+**Note**: Some tests in the `rv32i` suite will fail because privileged CSRs are not yet implemented in the formal specification.
+
+=== GRIFT (Galois RISC-V Formal Tools) Simulator
+
+To run the compliance test suite on the GRIFT simulator, first build/install GRIFT (https://github.com/GaloisInc/grift). The GRIFT simulation tool `grift-sim` needs to be on your PATH.
+
+Then, we can run the compliance suite via:
+
+[source,make]
+----
+make RISCV_TARGET=grift
+----
+
+We have ported the rv32i, rv32im, rv32imc, rv64i, and rv64im tests. You can also run these individually, e.g.:
+
+[source,make]
+----
+make RISCV_TARGET=grift RISCV_ISA=rv64i RISCV_DEVICE=rv64i
+----
+
+=== SiFive Freedom Unleashed 540 board (tbd)
+
+tbd
+
+=== Verilator Verilog RI5CY RTL processor
+==== With GDB Server
+
+tbd
+
+==== With testbench monitor
+
+tbd
+
+=== Adding a new Target
+
+In this section, a short tutorial how to add a user target in the TVM is provided.
+
+If you do not want to use the TVM at all, it is recommended to just take the tests and references and incorporate them into your testing environment.  The only requirement needed in this case is that there must be an option to dump the results from the target in the test environment so as the comparison to test reference signature is possible.
+
+The following steps demonstrate an example in which a target was replaced by Codasip ISA simulator. In a similar way, any RISC-V ISA simulator or any RTL simulation model of the RISC-V processor can be connected.
+
+* Redefine macros in `ISA/src/compliance_test.h` and `binary_coding/src/compliance_test.h`.
++
+For example, to support Codasip ISA simulator as Target, it was necessary to redefine `RV_COMPLIANCE_HALT macro`, `RV_COMPLIANCE_DATA_BEGIN` macro and `RV_COMPLIANCE_DATA_END` macro in `ISA/compliance_test.h` in the following way:
++
+[source,c]
+----
+#define RV_COMPLIANCE_HALT
+        add     x31, x0, 1
+        sw      x31, codasip_syscall, t0
+----
+
+* This means that on the address defined by `codasip_syscall`, the 1 value is stored and this is interpreted as `HALT` for the Codasip ISA simulator.
++
+[source,c]
+----
+#define RV_COMPLIANCE_DATA_BEGIN
+        .align  4;
+        .global codasip_signature_start;
+codasip_signature_start:
+----
++
+[source,c]
+----
+#define RV_COMPLIANCE_DATA_END
+        .align  4;
+        .global codasip_signature_end;
+codasip_signature_end:
+----
+
+* The Codasip ISA simulator dumps data from the addresses bounded by labels `codasip_signature_start` and `codasip_signature_end` to `stdout`.  The dumped data represent the results of the tests.
+
+* Modify Makefiles in `ISA/Makefile` and `binary_coding/Makefile`.  It is important to change tools that are evaluated and parameters that are passed to the tools.
++
+For example, to support the Codasip ISA simulator as the device under test
+(DUT), it was necessary to change `RISCV_SIM` from `spike` to
+`codix_berkelium-ia-isimulator –r` and parameters for running the simulator
+from `+signature=$(work_dir)/$<.signature.output` to `–info 5` plus handle
+redirection to a file by `1>$(work_dir)/$<.signature.output`.
+
+== Configuring the target device
+
+This section is for how to specify which optional parts are being used
+
+NOTE: This is primarily for simulators.
+
+In the directory `riscv-target/*/device` there are directories that have Makefile fragments that configure the simulator to simulate only those parts of the RISC-V specification that is required for the specific target device being tested.
+
+For example for the riscvOVPsim to be configured to be a RV32I
+[source,make]
+----
+RUN_TARGET= \
+        riscvOVPsim.exe --variant RV32I --program $(work_dir_isa)/$< \
+            --signaturedump \
+            --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+            --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
+            --override riscvOVPsim/cpu/simulateexceptions=T \
+            --logfile $(work_dir_isa)/$@
+----
+[appendix]
+== One ISA Test
+
+For a detailed description of one ISA test please have a look at the example: link:../riscv-test-suite/rv32i/src/I-IO.S[`I-IO.S`].
+
+This includes use of all the logging and assertion macros and shows how a test is split into sections.
+
+[appendix]
+== Repository structure
+
+The top level directory contains a `README.md` file giving an overview of the project, top level `Makefile`, `ChangeLog`, the `verify.sh` script and complete license files for the Creative Commons and BSD licenses used by the task group.  There are then four top level directories.
+
+`doc`:: All the documentation for the project, written using _AsciiDoc_.
+
+`riscv-target`:: Contains a further subdirectory for each target, within which are placed the `compliance_io.h` header for that target and a `device` directory for all the devices of that target. If the `$TARGETDIR` environment variable is set to another directory, the scripts will search this directory for targets instead.
+
+`riscv-test-env`:: This contains headers common to all environments, and then a directory for each TVM variant, with `link.ld` linker script and `riscv_test.h` header.
+
+`riscv-test-suite`:: This contains a subdirectory for each instruction set or instruction set extension.  Within each subdirectory the source code and reference output for each test are in the `ISA` directory.
+
+`riscv-ovpsim`:: This contains a copy of the Imperas OVP riscvOVPsim simulator for use in compliance testing. It includes a subdirectory of examples with pre-compiled .elf files and has binaries of the simulator for Linux64 and Windows64. This is referenced by the makefiles for developing and running the compliance suites. riscvOVPsim can run all the tracing and assertion macros used in the tests.
+
+[appendix]
+== Creative Commons Attribution 4.0 International License
+
+Creative Commons Corporation (“Creative Commons”) is not a law firm and does not provide legal services or legal advice. Distribution of Creative Commons public licenses does not create a lawyer-client or other relationship. Creative Commons makes its licenses and related information available on an “as-is” basis. Creative Commons gives no warranties regarding its licenses, any material licensed under their terms and conditions, or any related information. Creative Commons disclaims all liability for damages resulting from their use to the fullest extent possible.
+
+=== Using Creative Commons Public Licenses
+
+Creative Commons public licenses provide a standard set of terms and conditions that creators and other rights holders may use to share original works of authorship and other material subject to copyright and certain other rights specified in the public license below. The following considerations are for informational purposes only, are not exhaustive, and do not form part of our licenses.
+
+[horizontal]
+*Considerations for licensors*:: Our public licenses are intended for use by those authorized to give the public permission to use material in ways otherwise restricted by copyright and certain other rights. Our licenses are irrevocable. Licensors should read and understand the terms and conditions of the license they choose before applying it. Licensors should also secure all rights necessary before applying our licenses so that the public can reuse the material as expected. Licensors should clearly mark any material not subject to the license. This includes other CC-licensed material, or material used under an exception or limitation to copyright.  https://wiki.creativecommons.org/wiki/Considerations_for_licensors_and_licensees#Considerations_for_licensors[More considerations for licensors].
+
+*Considerations for the public*:: By using one of our public licenses, a licensor grants the public permission to use the licensed material under specified terms and conditions. If the licensor's permission is not necessary for any reason–for example, because of any applicable exception or limitation to copyright–then that use is not regulated by the license. Our licenses grant only permissions under copyright and certain other rights that a licensor has authority to grant. Use of the licensed material may still be restricted for other reasons, including because others have copyright or other rights in the material. A licensor may make special requests, such as asking that all changes be marked or described. Although not required by our licenses, you are encouraged to respect those requests where reasonable.  https://wiki.creativecommons.org/Considerations_for_licensors_and_licensees#Considerations_for_licensees[More considerations for the public].
+
+[[app_cc_by_4.0]]
+=== Creative Commons Attribution 4.0 International Public License
+
+By exercising the Licensed Rights (defined below), You accept and agree to be bound by the terms and conditions of this Creative Commons Attribution 4.0 International Public License ("Public License"). To the extent this Public License may be interpreted as a contract, You are granted the Licensed Rights in consideration of Your acceptance of these terms and conditions, and the Licensor grants You such rights in consideration of benefits the Licensor receives from making the Licensed Material available under these terms and conditions.
+
+:numbered!:
+==== Section 1--Definitions.
+
+a. *Adapted Material* means material subject to Copyright and Similar Rights that is derived from or based upon the Licensed Material and in which the Licensed Material is translated, altered, arranged, transformed, or otherwise modified in a manner requiring permission under the Copyright and Similar Rights held by the Licensor. For purposes of this Public License, where the Licensed Material is a musical work, performance, or sound recording, Adapted Material is always produced where the Licensed Material is synched in timed relation with a moving image.
+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+k. *You* means the individual or entity exercising the Licensed Rights under this Public License. Your has a corresponding meaning.
+
+==== Section 2 – Scope
+
+a. *License grant*.
+   1. Subject to the terms and conditions of this Public License, the Licensor hereby grants You a worldwide, royalty-free, non-sublicensable, non-exclusive, irrevocable license to exercise the Licensed Rights in the Licensed Material to:
+      A. reproduce and Share the Licensed Material, in whole or in part; and
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+   5. _Downstream recipients_.
+      A. _Offer from the Licensor – Licensed Material_. Every recipient of the Licensed Material automatically receives an offer from the Licensor to exercise the Licensed Rights under the terms and conditions of this Public License.
+      B. _No downstream restrictions_. You may not offer or impose any additional or different terms or conditions on, or apply any Effective Technological Measures to, the Licensed Material if doing so restricts exercise of the Licensed Rights by any recipient of the Licensed Material.
+   6. _No endorsement_. Nothing in this Public License constitutes or may be construed as permission to assert or imply that You are, or that Your use of the Licensed Material is, connected with, or sponsored, endorsed, or granted official status by, the Licensor or others designated to receive attribution as provided in Section 3(a)(1)(A)(i).
+
+b. *Other rights*.
+   1. Moral rights, such as the right of integrity, are not licensed under this Public License, nor are publicity, privacy, and/or other similar personality rights; however, to the extent possible, the Licensor waives and/or agrees not to assert any such rights held by the Licensor to the limited extent necessary to allow You to exercise the Licensed Rights, but not otherwise.
+   2. Patent and trademark rights are not licensed under this Public License.
+   3. To the extent possible, the Licensor waives any right to collect royalties from You for the exercise of the Licensed Rights, whether directly or through a collecting society under any voluntary or waivable statutory or compulsory licensing scheme. In all other cases the Licensor expressly reserves any right to collect such royalties.
+
+==== Section 3 -- License Conditions.
+
+Your exercise of the Licensed Rights is expressly made subject to the
+following conditions.
+ 
+a. Attribution.
+   1. If You Share the Licensed Material (including in modified form), You must:
+      A. retain the following if it is supplied by the Licensor with the Licensed Material:
+      	 i) identification of the creator(s) of the Licensed Material and any others designated to receive attribution, in any reasonable manner requested by the Licensor (including by pseudonym if designated);
+	 ii) a copyright notice;
+	 iii) notice that refers to this Public License;
+	 iv) a notice that refers to the disclaimer of warranties;
+	 v) a URI or hyperlink to the Licensed Material to the extent reasonably practicable;
+      B. indicate if You modified the Licensed Material and retain an indication of any previous modifications; and
+      C. indicate the Licensed Material is licensed under this Public License, and include the text of, or the URI or hyperlink to, this Public License.
+   2. You may satisfy the conditions in Section 3(a)(1) in any reasonable manner based on the medium, means, and context in which You Share the Licensed Material. For example, it may be reasonable to satisfy the conditions by providing a URI or hyperlink to a resource that includes the required information.
+   3. If requested by the Licensor, You must remove any of the information required by Section 3(a)(1)(A) to the extent reasonably practicable.
+   4. If You Share Adapted Material You produce, the Adapter's License You apply must not prevent recipients of the Adapted Material from complying with this Public License.
+
+==== Section 4 -- Sui Generis Database Rights.
+
+Where the Licensed Rights include Sui Generis Database Rights that apply to Your use of the Licensed Material:
+
+a. for the avoidance of doubt, Section 2(a)(1) grants You the right to extract, reuse, reproduce, and Share all or a substantial portion of the contents of the database;
+
+b. if You include all or a substantial portion of the database contents in a database in which You have Sui Generis Database Rights, then the database in which You have Sui Generis Database Rights (but not its individual contents) is Adapted Material; and
+
+c. You must comply with the conditions in Section 3(a) if You Share all or a substantial portion of the contents of the database.
+For the avoidance of doubt, this Section 4 supplements and does not replace Your obligations under this Public License where the Licensed Rights include other Copyright and Similar Rights.
+
+==== Section 5 -- Disclaimer of Warranties and Limitation of Liability.
+
+a. *Unless otherwise separately undertaken by the Licensor, to the extent possible, the Licensor offers the Licensed Material as-is and as-available, and makes no representations or warranties of any kind concerning the Licensed Material, whether express, implied, statutory, or other. This includes, without limitation, warranties of title, merchantability, fitness for a particular purpose, non-infringement, absence of latent or other defects, accuracy, or the presence or absence of errors, whether or not known or discoverable. Where disclaimers of warranties are not allowed in full or in part, this disclaimer may not apply to You.*
+
+b. *To the extent possible, in no event will the Licensor be liable to You on any legal theory (including, without limitation, negligence) or otherwise for any direct, special, indirect, incidental, consequential, punitive, exemplary, or other losses, costs, expenses, or damages arising out of this Public License or use of the Licensed Material, even if the Licensor has been advised of the possibility of such losses, costs, expenses, or damages. Where a limitation of liability is not allowed in full or in part, this limitation may not apply to You.*
+
+c. The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+==== Section 6 -- Term and Termination.
+
+a. This Public License applies for the term of the Copyright and Similar Rights licensed here. However, if You fail to comply with this Public License, then Your rights under this Public License terminate automatically.
+
+b. Where Your right to use the Licensed Material has terminated under Section 6(a), it reinstates:
+   1. automatically as of the date the violation is cured, provided it is cured within 30 days of Your discovery of the violation; or
+   2. upon express reinstatement by the Licensor.
+
+c. For the avoidance of doubt, this Section 6(b) does not affect any right the Licensor may have to seek remedies for Your violations of this Public License.
+
+d. For the avoidance of doubt, the Licensor may also offer the Licensed Material under separate terms or conditions or stop distributing the Licensed Material at any time; however, doing so will not terminate this Public License.
+Sections 1, 5, 6, 7, and 8 survive termination of this Public License.
+
+==== Section 7 -- Other Terms and Conditions.
+
+a. The Licensor shall not be bound by any additional or different terms or conditions communicated by You unless expressly agreed.
+
+b. Any arrangements, understandings, or agreements regarding the Licensed Material not stated herein are separate from and independent of the terms and conditions of this Public License.
+
+==== Section 8 -- Interpretation.
+
+a. For the avoidance of doubt, this Public License does not, and shall not be interpreted to, reduce, limit, restrict, or impose conditions on any use of the Licensed Material that could lawfully be made without permission under this Public License.
+
+b. To the extent possible, if any provision of this Public License is deemed unenforceable, it shall be automatically reformed to the minimum extent necessary to make it enforceable. If the provision cannot be reformed, it shall be severed from this Public License without affecting the enforceability of the remaining terms and conditions.
+
+c. No term or condition of this Public License will be waived and no failure to comply consented to unless expressly agreed to by the Licensor.
+
+d. Nothing in this Public License constitutes or may be interpreted as a limitation upon, or waiver of, any privileges and immunities that apply to the Licensor or You, including from the legal processes of any jurisdiction or authority.
+
+=== Supplementary
+
+Creative Commons is not a party to its public licenses. Notwithstanding, Creative Commons may elect to apply one of its public licenses to material it publishes and in those instances will be considered the “Licensor.” The text of the Creative Commons public licenses is dedicated to the public domain under the https://creativecommons.org/publicdomain/zero/1.0/legalcode[CC0 Public Domain Dedication]. Except for the limited purpose of indicating that material is shared under a Creative Commons public license or as otherwise permitted by the Creative Commons policies published at https://creativecommons.org/policies[creativecommons.org/policies], Creative Commons does not authorize the use of the trademark “Creative Commons” or any other trademark or logo of Creative Commons without its prior written consent including, without limitation, in connection with any unauthorized modifications to any of its public licenses or any other arrangements, understandings, or agreements concerning use of licensed material. For the avoidance of doubt, this paragraph does not form part of the public licenses.
+
+Creative Commons may be contacted at https://creativecommons.org/[creativecommons.org].
diff --git a/tests/riscv-compliance/doc/custom.wordlist b/tests/riscv-compliance/doc/custom.wordlist
new file mode 100644
index 0000000..2efdc59
--- /dev/null
+++ b/tests/riscv-compliance/doc/custom.wordlist
@@ -0,0 +1,73 @@
+AsciiDoc
+asciidoc
+AsciiDoctor
+asciidoctor
+aspell
+autotools
+CGEN
+cmake
+Codasip
+creativecommons
+CY
+Davidmann
+discoverable
+DUT
+EF
+enforceability
+FPGA
+GDB
+Generis
+github
+Hajek
+HDL
+http
+https
+IC
+ies
+immunities
+Imperas
+io
+IM
+ISA
+legalcode
+licensor
+licensors
+licensor's
+LLVM
+makefile
+makefiles
+Marcela
+md
+merchantability
+Nostersky
+nz
+pagewidth
+parameterization
+pdf
+publicdomain
+Radek
+README
+riscv
+riscvOVPsim
+RTL
+rv
+RVTEST
+SiFive
+spdx
+src
+subdirectory
+sublicensable
+synched
+tbd
+testbench
+toc
+toolchain
+TVM
+URI
+Verilator
+Verilog
+waivable
+WIPO
+wordlist
+www
+Zachariasova
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/README.md b/tests/riscv-compliance/riscv-target/tinyriscv/README.md
new file mode 100644
index 0000000..0a226c7
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/README.md
@@ -0,0 +1,21 @@
+# Running the compliance tests with RI5CY
+Build RI5CY's core testbench by navigating to `riscv/tb/core` and calling `make
+vsim-all` or if you prefer verilator `make verilate`.
+
+Set `TARGET_SIM` by providing the `vsim` executable and the work directory of
+the compiled model of RI5CY e.g.
+`export TARGET_SIM=vsim -work RI5CY_REPO/tb/core/work`
+or point `TARGET_SIM` to the compiled verilator testbench e.g.
+`export TARGET_SIM=RI5CY_REPO/tb/core/testbench_verilator`
+
+Now set the following variables:
+```
+export RISCV_PREFIX=riscv32-unknown-elf-
+export RISCV_TARGET=ri5cy
+export RISCV_DEVICE=rv32imc
+```
+
+You are now ready to run the tests. The following are supported:
+* `make RISCV_ISA=rv32i`
+* `make RISCV_ISA=rv32im`
+* `make RISCV_ISA=rv32imc`
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/compliance_io.h b/tests/riscv-compliance/riscv-target/tinyriscv/compliance_io.h
new file mode 100644
index 0000000..b56fafc
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/compliance_io.h
@@ -0,0 +1,36 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_WRITE_STR(_SP, _STR)
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#endif // _COMPLIANCE_IO_H
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/compliance_test.h b/tests/riscv-compliance/riscv-target/tinyriscv/compliance_test.h
new file mode 100644
index 0000000..f0c7540
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/compliance_test.h
@@ -0,0 +1,51 @@
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+#include "riscv_test.h"
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+
+#define TESTUTIL_BASE 0x10000000
+#define TESTUTIL_ADDR_HALT (TESTUTIL_BASE + 0x10)
+#define TESTUTIL_ADDR_BEGIN_SIGNATURE (TESTUTIL_BASE + 0x8)
+#define TESTUTIL_ADDR_END_SIGNATURE (TESTUTIL_BASE + 0xc)
+
+#define RV_COMPLIANCE_HALT                                                    \
+        /* tell simulation about location of begin_signature */               \
+        la t0, begin_signature;                                               \
+        li t1, TESTUTIL_ADDR_BEGIN_SIGNATURE;                                 \
+        sw t0, 0(t1);                                                         \
+        /* tell simulation about location of end_signature */                 \
+        la t0, end_signature;                                                 \
+        li t1, TESTUTIL_ADDR_END_SIGNATURE;                                   \
+        sw t0, 0(t1);                                                         \
+        /* dump signature and terminate simulation */                         \
+        li t0, 1;                                                             \
+        li t1, TESTUTIL_ADDR_HALT;                                            \
+        sw t0, 0(t1);                                                         \
+        RVTEST_PASS                                                           \
+
+#define RV_COMPLIANCE_RV32M                                                   \
+        RVTEST_RV32M                                                          \
+
+#define RV_COMPLIANCE_CODE_BEGIN                                              \
+        RVTEST_CODE_BEGIN                                                     \
+
+#define RV_COMPLIANCE_CODE_END                                                \
+        RVTEST_CODE_END                                                       \
+
+#define RV_COMPLIANCE_DATA_BEGIN                                              \
+        RVTEST_DATA_BEGIN                                                     \
+
+#define RV_COMPLIANCE_DATA_END                                                \
+        RVTEST_DATA_END                                                       \
+
+#endif
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zicsr/Makefile.include b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zicsr/Makefile.include
new file mode 100644
index 0000000..f848d3e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zicsr/Makefile.include
@@ -0,0 +1,18 @@
+
+
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump; \
+    $$(RISCV_OBJCOPY) -O binary $$(@)  $$(@).bin
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zifencei/Makefile.include b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zifencei/Makefile.include
new file mode 100644
index 0000000..f848d3e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32Zifencei/Makefile.include
@@ -0,0 +1,18 @@
+
+
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump; \
+    $$(RISCV_OBJCOPY) -O binary $$(@)  $$(@).bin
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32i/Makefile.include b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32i/Makefile.include
new file mode 100644
index 0000000..f848d3e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32i/Makefile.include
@@ -0,0 +1,18 @@
+
+
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump; \
+    $$(RISCV_OBJCOPY) -O binary $$(@)  $$(@).bin
diff --git a/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32im/Makefile.include b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32im/Makefile.include
new file mode 100644
index 0000000..f848d3e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-target/tinyriscv/device/rv32im/Makefile.include
@@ -0,0 +1,18 @@
+
+
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY  ?= $(RISCV_PREFIX)objcopy
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+COMPILE_TARGET=\
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump; \
+    $$(RISCV_OBJCOPY) -O binary $$(@)  $$(@).bin
diff --git a/tests/riscv-compliance/riscv-test-env/LICENSE b/tests/riscv-compliance/riscv-test-env/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/tests/riscv-compliance/riscv-test-env/encoding.h b/tests/riscv-compliance/riscv-test-env/encoding.h
new file mode 100644
index 0000000..c109ce1
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/encoding.h
@@ -0,0 +1,1471 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_SUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_TVM         0x00100000
+#define MSTATUS_TW          0x00200000
+#define MSTATUS_TSR         0x00400000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS_UXL         0x0000000300000000
+#define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS_UXL         0x0000000300000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN  0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN  0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF  0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define CLINT_BASE         0x02000000
+#define CLINT_SIZE         0x000c0000
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SATP_MODE SATP64_MODE
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SATP_MODE SATP32_MODE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes.  */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q  0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q  0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q  0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q  0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q  0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q  0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q  0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q  0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q  0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q  0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S  0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q  0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D  0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q  0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q  0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q  0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q  0xfff0007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q  0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q  0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q  0xfff0707f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W  0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU  0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L  0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU  0xfff0007f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q  0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q  0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q  0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q  0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_SATP 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(stval, CSR_STVAL)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mtval, CSR_MTVAL)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
+#endif
diff --git a/tests/riscv-compliance/riscv-test-env/p/link.ld b/tests/riscv-compliance/riscv-test-env/p/link.ld
new file mode 100644
index 0000000..f1566b9
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/p/link.ld
@@ -0,0 +1,19 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x00000000;
+  .text.init : { *(.text.init) }
+
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string)}
+  .bss : { *(.bss) }
+  _end = .;
+}
+
diff --git a/tests/riscv-compliance/riscv-test-env/p/riscv_test.h b/tests/riscv-compliance/riscv-test-env/p/riscv_test.h
new file mode 100644
index 0000000..a8ddf67
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/p/riscv_test.h
@@ -0,0 +1,232 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
+#define _ENV_PHYSICAL_SINGLE_CORE_H
+
+#include "../encoding.h"
+#include "compliance_test.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV64UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV32U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV32UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV64M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV64S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#define RVTEST_RV32M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV32S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#if __riscv_xlen == 64
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
+#else
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+#endif
+
+#define INIT_PMP                                                        \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  li t0, -1;        /* Set up a PMP to permit all accesses */           \
+  csrw pmpaddr0, t0;                                                    \
+  li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
+  csrw pmpcfg0, t0;                                                     \
+  .align 2;                                                             \
+1:
+
+#define INIT_SPTBR                                                      \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi sptbr, 0;                                                       \
+  .align 2;                                                             \
+1:
+
+#define DELEGATE_NO_TRAPS                                               \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi medeleg, 0;                                                     \
+  csrwi mideleg, 0;                                                     \
+  csrwi mie, 0;                                                         \
+  .align 2;                                                             \
+1:
+
+#define RVTEST_ENABLE_SUPERVISOR                                        \
+  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
+  csrs mstatus, a0;                                                     \
+  li a0, SIP_SSIP | SIP_STIP;                                           \
+  csrs mideleg, a0;                                                     \
+
+#define RVTEST_ENABLE_MACHINE                                           \
+  li a0, MSTATUS_MPP;                                                   \
+  csrs mstatus, a0;                                                     \
+
+#define RVTEST_FP_ENABLE                                                \
+  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0
+
+#define RISCV_MULTICORE_DISABLE                                         \
+  csrr a0, mhartid;                                                     \
+  1: bnez a0, 1b
+
+#define EXTRA_TVEC_USER
+#define EXTRA_TVEC_MACHINE
+#define EXTRA_INIT
+#define EXTRA_INIT_TIMER
+
+//
+// undefine some unusable CSR Accesses if no PRIV Mode present
+//
+#if defined(PRIV_MISA_S)
+#  if (PRIV_MISA_S==0)
+#    undef  INIT_SPTBR
+#    define INIT_SPTBR
+#    undef  INIT_PMP
+#    define INIT_PMP
+#    undef  DELEGATE_NO_TRAPS
+#    define DELEGATE_NO_TRAPS
+#    undef  RVTEST_ENABLE_SUPERVISOR
+#    define RVTEST_ENABLE_SUPERVISOR
+#  endif
+#endif
+#if defined(PRIV_MISA_U)
+#  if (PRIV_MISA_U==0)
+#  endif
+#endif
+#if defined(TRAPHANDLER)
+#include TRAPHANDLER
+#endif
+
+#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
+
+#define RVTEST_CODE_BEGIN                                               \
+        .section .text.init;                                            \
+        .align  6;                                                      \
+        .weak stvec_handler;                                            \
+        .weak mtvec_handler;                                            \
+        .globl _start;                                                  \
+_start:                                                                 \
+        /* reset vector */                                              \
+        j reset_vector;                                                 \
+        .align 2;                                                       \
+trap_vector:                                                            \
+        /* test whether the test came from pass/fail */                 \
+        csrr t5, mcause;                                                \
+        li t6, CAUSE_USER_ECALL;                                        \
+        beq t5, t6, write_tohost;                                       \
+        li t6, CAUSE_SUPERVISOR_ECALL;                                  \
+        beq t5, t6, write_tohost;                                       \
+        li t6, CAUSE_MACHINE_ECALL;                                     \
+        beq t5, t6, write_tohost;                                       \
+        /* if an mtvec_handler is defined, jump to it */                \
+        la t5, mtvec_handler;                                           \
+        beqz t5, 1f;                                                    \
+        jr t5;                                                          \
+        /* was it an interrupt or an exception? */                      \
+  1:    csrr t5, mcause;                                                \
+        bgez t5, handle_exception;                                      \
+        INTERRUPT_HANDLER;                                              \
+handle_exception:                                                       \
+        /* we don't know how to handle whatever the exception was */    \
+  other_exception:                                                      \
+        /* some unhandlable exception occurred */                       \
+  1:    ori TESTNUM, TESTNUM, 1337;                                     \
+  write_tohost:                                                         \
+        sw TESTNUM, tohost, t5;                                         \
+        j write_tohost;                                                 \
+reset_vector:                                                           \
+        li TESTNUM, 0;                                                  \
+        la t0, trap_vector;                                             \
+        csrw mtvec, t0;                                                 \
+        csrwi mstatus, 0;                                               \
+        la t0, 1f;                                                      \
+        csrw mepc, t0;                                                  \
+        li t0, 0;                                                       \
+        li t1, TESTUTIL_ADDR_HALT;                                      \
+        sw t0, 0(t1);                                                   \
+        mret;                                                           \
+1:                                                                      \
+begin_testcode:
+
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+end_testcode:                                                           \
+        unimp
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+//#define RVTEST_SYNC fence
+#define RVTEST_SYNC nop
+
+#define RVTEST_PASS                                                     \
+        RVTEST_SYNC;                                                    \
+        li TESTNUM, 1;                                                  \
+        SWSIG (0, TESTNUM);                                             \
+        ecall
+
+#define TESTNUM gp
+#define RVTEST_FAIL                                                     \
+        RVTEST_SYNC;                                                    \
+1:      beqz TESTNUM, 1b;                                               \
+        sll TESTNUM, TESTNUM, 1;                                        \
+        or TESTNUM, TESTNUM, 1;                                         \
+        SWSIG (0, TESTNUM);                                             \
+        ecall
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN                                               \
+        EXTRA_DATA                                                      \
+        .pushsection .tohost,"aw",@progbits;                            \
+        .align 8; .global tohost; tohost: .dword 0;                     \
+        .align 8; .global fromhost; fromhost: .dword 0;                 \
+        .popsection;                                                    \
+        .align 4; .global begin_signature; begin_signature:
+
+#define RVTEST_DATA_END                                                 \
+        .align 4; .global end_signature; end_signature:                 \
+        .align 8; .global begin_regstate; begin_regstate:               \
+        .word 128;                                                      \
+        .align 8; .global end_regstate; end_regstate:                   \
+        .word 4;
+
+#endif
diff --git a/tests/riscv-compliance/riscv-test-env/riscv_test_macros.h b/tests/riscv-compliance/riscv-test-env/riscv_test_macros.h
new file mode 100644
index 0000000..1a04591
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/riscv_test_macros.h
@@ -0,0 +1,462 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+
+//
+// In general the following registers are reserved
+// ra, a0, t0, t1
+// Additionally on an assertion violation, t1, t2 are overwritten
+// x1, x10, x5, x6, x7 respectively
+// Floating registers reserved
+// f5
+//
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+// Base function for integer operations
+#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) \
+
+// Base functions for single precision floating point operations
+#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    lw t1, 8(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    lw t1, 0(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    lw t1, 4(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .float val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    flw reg3, 8(a0); \
+    lw t1, 12(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .float val3; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .float val; \
+    .popsection
+
+#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
+    la  a0, test_ ## test_num ## _data; \
+    li reg, val; \
+    code; \
+    fsw destreg, offset(swreg); \
+    lw a1, 0(a0); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+// Base functions for double precision floating point operations - rv32d
+#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 16(a0); \
+    lw t2, 20(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 0(a0); \
+    lw t2, 4(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .dword correctval; \
+    .popsection; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg, 0(a0); \
+    lw t1, 8(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .double val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    fld reg3, 16(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 24(a0); \
+    lw t2, 28(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .double val3; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li  reg1, MASK_XLEN(val1); \
+      li  reg2, MASK_XLEN(val2); \
+      inst destreg, reg1, reg2; \
+    )
+
+#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      li reg, MASK_XLEN(val2); \
+      inst destreg, destreg, reg; \
+    )
+
+#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg, destreg; \
+    )
+
+#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      inst destreg, destreg, destreg; \
+    )
+
+#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, x0, reg; \
+    )
+
+#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, x0; \
+    )
+
+#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      inst destreg, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, x0, 0, swreg, offset, \
+      li reg1, MASK_XLEN(val1); \
+      li reg2, MASK_XLEN(val2); \
+      inst x0, reg1, reg2; \
+    )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, destreg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      inst destreg, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, x0, 0, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst x0, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      inst destreg, SEXT_IMM(imm); \
+      )
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      1: \
+      inst destreg, imm; \
+      la swreg, 1b; \
+      sub destreg, destreg, swreg; \
+      )
+
+//Tests for a compressed instruction
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg; \
+      )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, imm; \
+      )
+
+#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg,x0, correctval, swreg, offset, \
+      inst imm; \
+      )
+
+//Tests for floating point instructions - single precision
+#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+//Tests for floating point instructions - double precision
+#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_CADDI16SP(correctval, imm, swreg, offset, testreg) \
+      TEST_CASE(testreg,x2, correctval, swreg, offset, \
+      c.addi16sp x2, imm; \
+      )
+
+#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset, testreg) \
+      TEST_CASE(testreg,destreg, correctval, swreg, offset, \
+        c.addi4spn destreg, x2, SEXT_IMM(imm); \
+        )
+
+#define TEST_CJL(inst, reg, val, swreg, offset) \
+      li x10, val; \
+      la reg, 1f; \
+      inst reg; \
+      li x10, 0x123ab; \
+1: \
+      sw x10, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
+
+#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
+
+#define TEST_CJ(inst, reg, val, swreg, offset) \
+      li reg, val; \
+      inst 1f; \
+      li reg, 0x123ab; \
+1: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CL(inst, reg, imm, swreg, offset) \
+      la reg, test_data; \
+      inst reg, imm(reg); \
+      sw reg, offset(swreg); \
+
+// lw reg, imm(x2)
+// c.lwsp reg, imm(x2)
+#define TEST_CLWSP(reg, imm, swreg, offset) \
+      la x2, test_data; \
+      c.lwsp reg, imm(x2); \
+      sw reg, offset(swreg); \
+
+#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
+      li reg1, val; \
+      la reg2, test_data; \
+      inst reg1, imm(reg2); \
+      lw reg1, imm(reg2); \
+      sw reg1, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
+
+#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
+      la x2, test_data; \
+      li reg, val; \
+      c.swsp reg, imm(x2); \
+      lw reg, imm(x2); \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CBEQZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.sub reg, reg; \
+      c.beqz reg, 3f; \
+      li reg, 0x123ab; \
+3: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
+
+#define TEST_CBNEZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.bnez reg, 4f; \
+      li reg, 0x0; \
+4: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.x.s destreg, reg; \
+        )
+
+#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.s.x destreg, reg; \
+        )
+
+#define SWSIG(a,b)
+
diff --git a/tests/riscv-compliance/riscv-test-env/test_macros.h b/tests/riscv-compliance/riscv-test-env/test_macros.h
new file mode 100644
index 0000000..f24fc7a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-env/test_macros.h
@@ -0,0 +1,462 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+
+//
+// In general the following registers are reserved
+// ra, a0, t0, t1
+// Additionally on an assertion violation, t1, t2 are overwritten
+// x1, x10, x5, x6, x7 respectively
+// Floating registers reserved
+// f5
+//
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+// Base function for integer operations
+#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+
+// Base functions for single precision floating point operations
+#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    lw t1, 8(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    lw t1, 0(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    lw t1, 4(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .float val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    flw reg3, 8(a0); \
+    lw t1, 12(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .float val3; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .float val; \
+    .popsection
+
+#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
+    la  a0, test_ ## test_num ## _data; \
+    li reg, val; \
+    code; \
+    fsw destreg, offset(swreg); \
+    lw a1, 0(a0); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+// Base functions for double precision floating point operations - rv32d
+#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 16(a0); \
+    lw t2, 20(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 0(a0); \
+    lw t2, 4(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .dword correctval; \
+    .popsection; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg, 0(a0); \
+    lw t1, 8(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .double val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    fld reg3, 16(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 24(a0); \
+    lw t2, 28(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .double val3; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li  reg1, MASK_XLEN(val1); \
+      li  reg2, MASK_XLEN(val2); \
+      inst destreg, reg1, reg2; \
+    )
+
+#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      li reg, MASK_XLEN(val2); \
+      inst destreg, destreg, reg; \
+    )
+
+#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg, destreg; \
+    )
+
+#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      inst destreg, destreg, destreg; \
+    )
+
+#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, x0, reg; \
+    )
+
+#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, x0; \
+    )
+
+#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      inst destreg, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \
+    TEST_CASE( x0, 0, swreg, offset, \
+      li reg1, MASK_XLEN(val1); \
+      li reg2, MASK_XLEN(val2); \
+      inst x0, reg1, reg2; \
+    )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, destreg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      inst destreg, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \
+    TEST_CASE ( x0, 0, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst x0, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      inst destreg, SEXT_IMM(imm); \
+      )
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      1: \
+      inst destreg, SEXT_IMM(imm); \
+      la swreg, 1b; \
+      sub destreg, destreg, swreg; \
+      )
+
+//Tests for a compressed instruction
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg; \
+      )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, imm; \
+      )
+
+#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \
+    TEST_CASE (x0, correctval, swreg, offset, \
+      inst imm; \
+      )
+
+//Tests for floating point instructions - single precision
+#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+//Tests for floating point instructions - double precision
+#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_CADDI16SP(correctval, imm, swreg, offset) \
+      TEST_CASE(x2, correctval, swreg, offset, \
+      c.addi16sp x2, imm; \
+      )
+
+#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \
+      TEST_CASE(destreg, correctval, swreg, offset, \
+        c.addi4spn destreg, x2, SEXT_IMM(imm); \
+        )
+
+#define TEST_CJL(inst, reg, val, swreg, offset) \
+      li x10, val; \
+      la reg, 1f; \
+      inst reg; \
+      li x10, 0x123ab; \
+1: \
+      sw x10, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
+
+#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
+
+#define TEST_CJ(inst, reg, val, swreg, offset) \
+      li reg, val; \
+      inst 1f; \
+      li reg, 0x123ab; \
+1: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CL(inst, reg, imm, swreg, offset) \
+      la reg, test_data; \
+      inst reg, imm(reg); \
+      sw reg, offset(swreg); \
+
+// lw reg, imm(x2)
+// c.lwsp reg, imm(x2)
+#define TEST_CLWSP(reg, imm, swreg, offset) \
+      la x2, test_data; \
+      c.lwsp reg, imm(x2); \
+      sw reg, offset(swreg); \
+
+#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
+      li reg1, val; \
+      la reg2, test_data; \
+      inst reg1, imm(reg2); \
+      lw reg1, imm(reg2); \
+      sw reg1, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
+
+#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
+      la x2, test_data; \
+      li reg, val; \
+      c.swsp reg, imm(x2); \
+      lw reg, imm(x2); \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CBEQZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.sub reg, reg; \
+      c.beqz reg, 3f; \
+      li reg, 0x123ab; \
+3: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
+
+#define TEST_CBNEZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.bnez reg, 4f; \
+      li reg, 0x0; \
+4: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.x.s destreg, reg; \
+        )
+
+#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.s.x destreg, reg; \
+        )
+
+#define SWSIG(a,b)
+
diff --git a/tests/riscv-compliance/riscv-test-suite/README.md b/tests/riscv-compliance/riscv-test-suite/README.md
new file mode 100644
index 0000000..fffdb12
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/README.md
@@ -0,0 +1,46 @@
+# RISC-V Test Suites
+
+Tests are grouped into different functional test suites targeting the different subsets of the full RISC-V specifications.  There will be ISA and privilege suites.
+
+For information on the test framework and other documentation on the compliance tests look at : [../doc/README.adoc](../doc/README.adoc) 
+
+Currently there are five solid test suites checked into this repository along with a few deprecated/WIP tests. 
+
+If you are looking to check compliance of RV32I in user mode then run the suites: RV32I, RV32ICSR and RV32IFENCEI
+
+To see the coverage of the suites see the riscv-test-suite coverage directory for the summary/detailed reports. These are generated by Imperas by using the github.com/google/riscv-dv UVM coverage testbench and the Mentor Questa SystemVerilog simulator.
+
+Test suites status:
+
+Pretty Solid:
+* RV32I (significant improvements (Nov2019) by Imperas)
+    * 48 focused tests, using the correct style/macros, excellent coverage of most instructions
+    * Coverage 97.23%
+* RV32IM (developed by Imperas)
+    * 8 focused tests, using the correct style/macros, excellent coverage
+    * Coverage 89.95%
+* RV32IMC (developed by Imperas)
+    * 25 focused tests, using the correct style/macros
+    * Coverage 59.68%
+* RV32ICSR
+    * 6 focused tests
+* RV32IFENCEI
+    * 1 test
+    
+Work in progress (64-bit tests):
+* RV64I (developed by Imperas)
+    * 8 focused tests, using the correct style/macros
+* RV64IM (developed by Imperas)
+    * 3 focused tests, using the correct style/macros
+
+To be worked on:
+* RV64C
+* RV32A
+* RV64A
+* RV64F
+* RV64D
+* RV32E
+* RV32EC
+* RV32EA
+* RV32EF
+* RV32ED
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/.gitignore b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefile b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefile
new file mode 100644
index 0000000..31990b9
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefile
@@ -0,0 +1,59 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+act_dir := .
+src_dir := $(act_dir)/src
+work_dir := $(ROOTDIR)/build_generated
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
+
+include $(act_dir)/Makefrag
+ifneq ($(RISCV_TEST),)
+    target_tests = $(RISCV_TEST).elf
+endif
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+vpath %.S $(act_dir)
+
+INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include
+ifeq ($(wildcard $(INCLUDE)),)
+    $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
+endif
+-include $(INCLUDE)
+
+#------------------------------------------------------------
+# Build and run assembly tests
+
+%.log: %.elf
+	$(V) echo "Execute $(@)"
+	#$(V) $(RUN_TARGET)
+
+
+define compile_template
+
+$(work_dir_isa)/%.elf: $(src_dir)/%.S
+	$(V) echo "Compile $$(@)"
+	@mkdir -p $$(@D)
+	$(V) $(COMPILE_TARGET)
+
+.PRECIOUS: $(work_dir_isa)/%.elf
+
+endef
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32))
+
+target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
+target_log = $(patsubst %.elf,%.log,$(target_elf))
+
+run: $(target_log)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(work_dir)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefrag b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefrag
new file mode 100644
index 0000000..0ecda64
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/Makefrag
@@ -0,0 +1,40 @@
+# RISC-V Compliance Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32Zicsr compliance tests
+
+rv32Zicsr_sc_tests = \
+    I-CSRRW-01 \
+    I-CSRRWI-01 \
+    I-CSRRS-01 \
+    I-CSRRSI-01 \
+    I-CSRRC-01 \
+    I-CSRRCI-01 \
+
+rv32Zicsr_tests = $(addsuffix .elf, $(rv32Zicsr_sc_tests))
+
+target_tests += $(rv32Zicsr_tests)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output
new file mode 100644
index 0000000..e684d3b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output
@@ -0,0 +1,24 @@
+00000000
+fffffffe
+ffffffff
+800f0000
+7fffffff
+00000000
+ffffffff
+fffffffe
+fffffffe
+800f0000
+000f0000
+00000000
+edcba987
+ffffffff
+00000000
+ffffffff
+ffffffff
+00000000
+42726e6f
+00000000
+f7ff8818
+ffffffff
+69c7ad8b
+49c1a903
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output
new file mode 100644
index 0000000..a7468e3
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output
@@ -0,0 +1,16 @@
+00000000
+fffffffe
+ffffffff
+ffffffe0
+ffffffef
+fffffff0
+ffffffff
+ffffffff
+fffffffe
+fffffffe
+ffffffe0
+ffffffe0
+ffffffe0
+ffffffff
+00000000
+32165490
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output
new file mode 100644
index 0000000..1beda24
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000001
+00000000
+7ff0ffff
+80000000
+ffffffff
+00000000
+00000001
+00000001
+7ff0ffff
+fff0ffff
+ffffffff
+12345678
+00000000
+12345678
+00000000
+12345678
+00000000
+42726e6f
+00000000
+f7ff8818
+00000000
+96385274
+b63e56fc
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output
new file mode 100644
index 0000000..e999a93
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output
@@ -0,0 +1,16 @@
+00000000
+00000001
+00000000
+0000001f
+00000010
+0000000f
+00000000
+00000000
+00000001
+00000001
+0000001f
+0000001f
+0000001f
+00000000
+3216549f
+32165498
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output
new file mode 100644
index 0000000..1e9ebf6
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output
@@ -0,0 +1,16 @@
+00000000
+00000001
+00000000
+ffffffff
+7fffffff
+80000000
+12345678
+9abcdef0
+12345678
+9abcdef0
+00000000
+00000000
+00000000
+14725836
+96385274
+32165498
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output
new file mode 100644
index 0000000..9017c05
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output
@@ -0,0 +1,8 @@
+00000000
+00000000
+00000001
+00000000
+0000001f
+0000000f
+00000010
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S
new file mode 100644
index 0000000..f6a8159
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S
@@ -0,0 +1,276 @@
+# RISC-V Compliance Test I-CSRRC-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRC.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of csrrc\n");
+
+    # Address for test results
+    la      x15, test_A1_res
+
+    # Register initialization
+    li      x1, 1
+    li      x2, 0
+    li      x3, 0x7FF0FFFF
+    li      x4, 0x80000000
+    li      x5, -1
+    csrrw   x0, mscratch, x5
+
+    # Test
+    csrrc   x1, mscratch, x1
+    csrrw   x1, mscratch, x5
+
+    csrrc   x2, mscratch, x2
+    csrrw   x2, mscratch, x5
+
+    csrrc   x3, mscratch, x3
+    csrrw   x3, mscratch, x5
+
+    csrrc   x4, mscratch, x4
+    csrrw   x4, mscratch, x5
+
+    csrrc   x5, mscratch, x5
+    csrrw   x5, mscratch, x0
+
+    # Store results
+    sw      x0, 0(x15)
+    sw      x1, 4(x15)
+    sw      x2, 8(x15)
+    sw      x3, 12(x15)
+    sw      x4, 16(x15)
+    sw      x5, 20(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x1, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x3, 0x800F0000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x5, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of csrrc\n");
+
+    # Address for test results
+    la      x5, test_A2_res
+
+    # Register initialization
+    li      x11, 1
+    li      x12, 0
+    li      x13, 0x7FF0FFFF
+    li      x14, 0x80000000
+    li      x15, -1
+    csrrw   x0, mscratch, x15
+
+    # Test
+    csrrc   x11, mscratch, x11
+    csrrc   x12, mscratch, x12
+    csrrc   x13, mscratch, x13
+    csrrc   x14, mscratch, x14
+    csrrc   x15, mscratch, x15
+    csrrc   x16, mscratch, x0
+
+
+    # Store results
+    sw      x11, 0(x5)
+    sw      x12, 4(x5)
+    sw      x13, 8(x5)
+    sw      x14, 12(x5)
+    sw      x15, 16(x5)
+    sw      x16, 20(x5)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x11, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x12, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x13, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x14, 0x800F0000)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x15, 0x000F0000)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x16, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n");
+
+    # Address for test results
+    la      x26, test_B_res
+
+    # Register initialization
+    li      x21, 0x12345678
+    li      x20, -1
+    csrrw   x0, mscratch, x20
+
+    # Test
+    csrrc   x22, mscratch, x21
+    csrrc   x21, mscratch, x22
+    csrrw   x23, mscratch, x20
+    csrrc   x24, mscratch, x23
+    csrrc   x25, mscratch, x0
+
+    # store results
+    sw      x21, 0(x26)
+    sw      x22, 4(x26)
+    sw      x23, 8(x26)
+    sw      x24, 12(x26)
+    sw      x25, 16(x26)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x21, 0xEDCBA987)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x22, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x23, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x24, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0xFFFFFFFF)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0 and reading from x0\n");
+
+    # Address for test results
+    la      x1, test_C_res
+
+    # Register initialization
+    li      x30, 0x42726E6F
+    csrrw   x0, mscratch, x30
+
+    # Test
+    csrrc   x0, mscratch, x30
+
+    # store results
+    sw      x0, 0(x1)
+    sw      x30, 4(x1)
+
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x30, 0x42726e6f)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n");
+
+    # Address for test results
+    la      x2, test_D_res
+
+    # Register initialization
+    li      x31, 0xF7FF8818
+    csrrw   x0, mscratch, x31
+
+    # Test
+    csrrc   x0, mscratch, x0
+    csrrc   x0, mscratch, x0
+    csrrc   x31, mscratch, x0
+
+    # store results
+    sw      x0, 0(x2)
+    sw      x31, 4(x2)
+
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0xF7FF8818)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part E - testing csrrc with same dst and src registers\n");
+
+    # Address for test results
+    la      x2, test_E_res
+
+    # Register initialization
+    li      x4, -1
+    li      x5, 0x96385274
+    li      x7, 0x32165498
+    csrrw   x0, mscratch, x4
+
+    # Test
+    csrrc   x5, mscratch, x5
+    csrrc   x7, mscratch, x7
+    csrrc   x8, mscratch, x8
+
+    # Store results
+    sw      x5, 0(x2)
+    sw      x7, 4(x2)
+    sw      x8, 8(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x69C7AD8B)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x49C1A903)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part B  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 6, 4, -1
+test_A2_res:
+    .fill 6, 4, -1
+test_B_res:
+    .fill 5, 4, -1
+test_C_res:
+    .fill 2, 4, -1
+test_D_res:
+    .fill 2, 4, -1
+test_E_res:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S
new file mode 100644
index 0000000..7686d0b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S
@@ -0,0 +1,182 @@
+# RISC-V Compliance Test I-CSRRCI-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRCI.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of csrrci\n");
+
+    # Address for test results
+    la      x15, test_A1_res
+
+    # Register initialization
+    li      x8, -1
+    csrrw   x0, mscratch, x8
+
+    # Test
+    csrrci  x1, mscratch, 1
+    csrrw   x1, mscratch, x8
+
+    csrrci  x2, mscratch, 0
+    csrrw   x2, mscratch, x8
+
+    csrrci  x3, mscratch, 0x1F
+    csrrw   x3, mscratch, x8
+
+    csrrci  x4, mscratch, 0x10
+    csrrw   x4, mscratch, x8
+
+    csrrci  x5, mscratch, 0xF
+    csrrw   x5, mscratch, x8
+
+
+    # Store results
+    sw      x0, 0(x15)
+    sw      x1, 4(x15)
+    sw      x2, 8(x15)
+    sw      x3, 12(x15)
+    sw      x4, 16(x15)
+    sw      x5, 20(x15)
+    sw      x8, 24(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x1, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x3, 0xFFFFFFE0)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4, 0xFFFFFFEF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x5, 0xFFFFFFF0)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x8, 0xFFFFFFFF)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of csrrci\n");
+
+    # Address for test results
+    la      x5, test_A2_res
+
+    # Register initialization
+    li      x8, -1
+    csrrw   x0, mscratch, x8
+
+    # Test
+    csrrci  x11, mscratch, 1
+    csrrci  x12, mscratch, 0
+    csrrci  x13, mscratch, 0x1F
+    csrrci  x14, mscratch, 0x10
+    csrrci  x15, mscratch, 0xF
+    csrrci  x16, mscratch, 0
+
+
+    # Store results
+    sw      x11, 0(x5)
+    sw      x12, 4(x5)
+    sw      x13, 8(x5)
+    sw      x14, 12(x5)
+    sw      x15, 16(x5)
+    sw      x16, 20(x5)
+    sw      x8, 24(x5)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x11, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x12, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x13, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x14, 0xFFFFFFE0)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x15, 0xFFFFFFE0)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x16, 0xFFFFFFE0)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x8, 0xFFFFFFFF)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n");
+
+    # Address for test results
+    la      x1, test_B_res
+
+    # Register initialization
+    li      x20, 0x32165498
+    csrrw   x0, mscratch, x20
+
+    # Test
+    csrrci   x0, mscratch, 0xF
+    csrrw    x20, mscratch, x20
+
+
+    # store results
+    sw      x0, 0(x1)
+    sw      x20, 4(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x20, 0x32165490)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 7, 4, -1
+test_A2_res:
+    .fill 7, 4, -1
+test_B_res:
+    .fill 2, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S
new file mode 100644
index 0000000..1692896
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S
@@ -0,0 +1,274 @@
+# RISC-V Compliance Test I-CSRRS-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRS.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of CSRRS\n");
+
+    # Address for test results
+    la      x15, test_A1_res
+
+    # Register initialization
+    li      x1, 1
+    li      x2, 0
+    li      x3, 0x7FF0FFFF
+    li      x4, 0x80000000
+    li      x5, -1
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrs   x1, mscratch, x1
+    csrrw   x1, mscratch, x0
+
+    csrrs   x2, mscratch, x2
+    csrrw   x2, mscratch, x0
+
+    csrrs   x3, mscratch, x3
+    csrrw   x3, mscratch, x0
+
+    csrrs   x4, mscratch, x4
+    csrrw   x4, mscratch, x0
+
+    csrrs   x5, mscratch, x5
+    csrrw   x5, mscratch, x0
+
+    # Store results
+    sw      x0, 0(x15)
+    sw      x1, 4(x15)
+    sw      x2, 8(x15)
+    sw      x3, 12(x15)
+    sw      x4, 16(x15)
+    sw      x5, 20(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x1, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x3, 0x7FF0FFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x5, 0xFFFFFFFF)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of CSRRS\n");
+
+    # Address for test results
+    la      x5, test_A2_res
+
+    # Register initialization
+    li      x11, 1
+    li      x12, 0
+    li      x13, 0x7FF0FFFF
+    li      x14, 0x80000000
+    li      x15, -1
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrs   x11, mscratch, x11
+    csrrs   x12, mscratch, x12
+    csrrs   x13, mscratch, x13
+    csrrs   x14, mscratch, x14
+    csrrs   x15, mscratch, x15
+    csrrs   x16, mscratch, x0
+
+
+    # Store results
+    sw      x11, 0(x5)
+    sw      x12, 4(x5)
+    sw      x13, 8(x5)
+    sw      x14, 12(x5)
+    sw      x15, 16(x5)
+    sw      x16, 20(x5)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x11, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x12, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x13, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x14, 0x7FF0FFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x15, 0xFFF0FFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x16, 0xFFFFFFFF)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n");
+
+    # Address for test results
+    la      x26, test_B_res
+
+    # Register initialization
+    li      x21, 0x12345678
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrs   x22, mscratch, x21
+    csrrs   x23, mscratch, x22
+    csrrw   x23, mscratch, x0
+    csrrs   x24, mscratch, x23
+    csrrs   x25, mscratch, x0
+
+    # store results
+    sw      x21, 0(x26)
+    sw      x22, 4(x26)
+    sw      x23, 8(x26)
+    sw      x24, 12(x26)
+    sw      x25, 16(x26)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x21, 0x12345678)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x22, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x23, 0x12345678)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x24, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x12345678)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0 and reading from x0\n");
+
+    # Address for test results
+    la      x1, test_C_res
+
+    # Register initialization
+    li      x30, 0x42726E6F
+    csrrw   x0, mscratch, x30
+
+    # Test
+    csrrs   x0, mscratch, x30
+
+    # store results
+    sw      x0, 0(x1)
+    sw      x30, 4(x1)
+
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x30, 0x42726E6F)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n");
+
+    # Address for test results
+    la      x2, test_D_res
+
+    # Register initialization
+    li      x31, 0xF7FF8818
+    csrrw   x0, mscratch, x31
+
+    # Test
+    csrrs   x0, mscratch, x0
+    csrrs   x0, mscratch, x0
+    csrrs   x31, mscratch, x0
+
+    # store results
+    sw      x0, 0(x2)
+    sw      x31, 4(x2)
+
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0xF7FF8818)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part E - testing csrrs with same dst and src registers\n");
+
+    # Address for test results
+    la      x2, test_E_res
+
+    # Register initialization
+    li      x7, 0x32165498
+    li      x5, 0x96385274
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrs   x5, mscratch, x5
+    csrrs   x7, mscratch, x7
+    csrrs   x8, mscratch, x8
+
+    # Store results
+    sw      x5, 0(x2)
+    sw      x7, 4(x2)
+    sw      x8, 8(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x96385274)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0xB63E56FC)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part B  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 6, 4, -1
+test_A2_res:
+    .fill 6, 4, -1
+test_B_res:
+    .fill 5, 4, -1
+test_C_res:
+    .fill 2, 4, -1
+test_D_res:
+    .fill 2, 4, -1
+test_E_res:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S
new file mode 100644
index 0000000..ee55e13
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S
@@ -0,0 +1,177 @@
+# RISC-V Compliance Test I-CSRRSI-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRSI.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of CSRRSI\n");
+
+    # Address for test results
+    la      x15, test_A1_res
+
+    # Register initialization
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrsi  x1, mscratch, 1
+    csrrw   x1, mscratch, x0
+
+    csrrsi  x2, mscratch, 0
+    csrrw   x2, mscratch, x0
+
+    csrrsi  x3, mscratch, 0x1F
+    csrrw   x3, mscratch, x0
+
+    csrrsi  x4, mscratch, 0x10
+    csrrw   x4, mscratch, x0
+
+    csrrsi  x5, mscratch, 0xF
+    csrrw   x5, mscratch, x0
+
+    # Store results
+    sw      x0, 0(x15)
+    sw      x1, 4(x15)
+    sw      x2, 8(x15)
+    sw      x3, 12(x15)
+    sw      x4, 16(x15)
+    sw      x5, 20(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x1, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x3, 0x0000001F)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4, 0x00000010)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x5, 0x0000000F)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of CSRRSI\n");
+
+    # Address for test results
+    la      x5, test_A2_res
+
+    # Register initialization
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrsi  x11, mscratch, 1
+    csrrsi  x12, mscratch, 0
+    csrrsi  x13, mscratch, 0x1F
+    csrrsi  x14, mscratch, 0x10
+    csrrsi  x15, mscratch, 0xF
+    csrrsi  x16, mscratch, 0
+
+    # Store results
+    sw      x0, 0(x5)
+    sw      x11, 4(x5)
+    sw      x12, 8(x5)
+    sw      x13, 12(x5)
+    sw      x14, 16(x5)
+    sw      x15, 20(x5)
+    sw      x16, 24(x5)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x11, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x12, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x13, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x14, 0x0000001F)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x15, 0x0000001F)
+    RVTEST_IO_ASSERT_GPR_EQ(x5, x16, 0x0000001F)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n");
+
+    # Address for test results
+    la      x1, test_B_res
+
+    # Register initialization
+    li      x20, 0x32165498
+    csrrw   x0, mscratch, x20
+
+    # Test
+    csrrsi   x0, mscratch, 0xF
+    csrrw    x21, mscratch, x20
+
+    # store results
+    sw      x0, 0(x1)
+    sw      x21, 4(x1)
+    sw      x20, 8(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x21, 0x3216549F)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x20, 0x32165498)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 6, 4, -1
+test_A2_res:
+    .fill 7, 4, -1
+test_B_res:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S
new file mode 100644
index 0000000..23079b8
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S
@@ -0,0 +1,220 @@
+# RISC-V Compliance Test I-CSRRW-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRW.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A - general test of CSRRW\n");
+
+    # Address for test results
+    la      x15, test_A_res
+
+    # Register initialization
+    li      x1, 1
+    li      x3, 0
+    li      x5, -1
+    li      x27, 0x7FFFFFFF
+    li      x29, 0x80000000
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrw   x2, mscratch, x1
+    csrrw   x4, mscratch, x3
+    csrrw   x6, mscratch, x5
+    csrrw   x28, mscratch, x27
+    csrrw   x30, mscratch, x29
+    csrrw   x31, mscratch, x0
+
+    # Store results
+    sw      x2, 0(x15)
+    sw      x4, 4(x15)
+    sw      x6, 8(x15)
+    sw      x28, 12(x15)
+    sw      x30, 16(x15)
+    sw      x31, 20(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4,  0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x6,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x28, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x30, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x31, 0x80000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n");
+
+    # Address for test results
+    la      x26, test_B_res
+
+    # Register initialization
+    li      x1, 0x12345678
+    li      x2, 0x9ABCDEF0
+
+    # Test
+    csrrw   x0, mscratch, x1
+    csrrw   x3, mscratch, x2
+    csrrw   x4, mscratch, x3
+    csrrw   x5, mscratch, x4
+    csrrw   x6, mscratch, x0
+
+    # store results
+    sw      x3, 0(x26)
+    sw      x4, 4(x26)
+    sw      x5, 8(x26)
+    sw      x6, 12(x26)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x12345678)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x4, 0x9ABCDEF0)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x5, 0x12345678)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x6, 0x9ABCDEF0)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n");
+
+    # Address for test results
+    la      x1, test_C_res
+
+    # Register initialization
+    li      x2, 0x42726E6F
+
+    # Test
+    csrrw   x0, mscratch, x2
+    csrrw   x0, mscratch, x0
+
+    # store results
+    sw      x0, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n");
+
+    # Address for test results
+    la      x2, test_D_res
+
+    # Register initialization
+    li      x27, 0xF7FF8818
+
+    # Test
+    csrrw   x0, mscratch, x27
+    csrrw   x0, mscratch, x0
+    csrrw   x0, mscratch, x0
+    csrrw   x5, mscratch, x0
+
+    # store results
+    sw      x0, 0(x2)
+    sw      x5, 4(x2)
+
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part E - testing csrrw with same dst and src registers\n");
+
+    # Address for test results
+    la      x2, test_E_res
+
+    # Register initialization
+    li      x7, 0x32165498
+    li      x6, 0x14725836
+    li      x5, 0x96385274
+
+    # Test
+    csrrw   x0, mscratch, x6
+    csrrw   x5, mscratch, x5
+    csrrw   x7, mscratch, x7
+    csrrw   x8, mscratch, x0
+
+    # Store results
+    sw      x5, 0(x2)
+    sw      x7, 4(x2)
+    sw      x8, 8(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x14725836)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x96385274)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x32165498)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res:
+    .fill 6, 4, -1
+test_B_res:
+    .fill 4, 4, -1
+test_C_res:
+    .fill 1, 4, -1
+test_D_res:
+    .fill 2, 4, -1
+test_E_res:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S
new file mode 100644
index 0000000..256eff5
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S
@@ -0,0 +1,124 @@
+# RISC-V Compliance Test I-CSRRWI-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction CSRRWI.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A - general test of CSRRWI\n");
+
+    # Address for test results
+    la      x15, test_A_res
+
+    # Register initialization
+    csrrw   x0, mscratch, x0
+
+    # Test
+    csrrwi  x2, mscratch, 1
+    csrrwi  x4, mscratch, 0
+    csrrwi  x6, mscratch, 0x1F
+    csrrwi  x28, mscratch, 0x0F
+    csrrwi  x30, mscratch, 0x10
+    csrrwi  x31, mscratch, 0
+
+    # Store results
+    sw      x0, 0(x15)
+    sw      x2, 4(x15)
+    sw      x4, 8(x15)
+    sw      x6, 12(x15)
+    sw      x28, 16(x15)
+    sw      x30, 20(x15)
+    sw      x31, 24(x15)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x2,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x4,  0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x6,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x28, 0x0000001F)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x30, 0x0000000F)
+    RVTEST_IO_ASSERT_GPR_EQ(x15, x31, 0x00000010)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n");
+
+    # Address for test results
+    la      x1, test_B_res
+
+    # Test
+    csrrwi  x0, mscratch, 0xF
+    csrrwi  x0, mscratch, 0
+
+    # store results
+    sw      x0, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res:
+    .fill 7, 4, -1
+test_B_res:
+    .fill 1, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/.gitignore b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefile b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefile
new file mode 100644
index 0000000..31990b9
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefile
@@ -0,0 +1,59 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+act_dir := .
+src_dir := $(act_dir)/src
+work_dir := $(ROOTDIR)/build_generated
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
+
+include $(act_dir)/Makefrag
+ifneq ($(RISCV_TEST),)
+    target_tests = $(RISCV_TEST).elf
+endif
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+vpath %.S $(act_dir)
+
+INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include
+ifeq ($(wildcard $(INCLUDE)),)
+    $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
+endif
+-include $(INCLUDE)
+
+#------------------------------------------------------------
+# Build and run assembly tests
+
+%.log: %.elf
+	$(V) echo "Execute $(@)"
+	#$(V) $(RUN_TARGET)
+
+
+define compile_template
+
+$(work_dir_isa)/%.elf: $(src_dir)/%.S
+	$(V) echo "Compile $$(@)"
+	@mkdir -p $$(@D)
+	$(V) $(COMPILE_TARGET)
+
+.PRECIOUS: $(work_dir_isa)/%.elf
+
+endef
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32))
+
+target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
+target_log = $(patsubst %.elf,%.log,$(target_elf))
+
+run: $(target_log)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(work_dir)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefrag b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefrag
new file mode 100644
index 0000000..2c2e125
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Compliance Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32Zifencei compliance tests
+
+rv32Zifencei_sc_tests = \
+    I-FENCE.I-01 \
+
+rv32Zifencei_tests = $(addsuffix .elf, $(rv32Zifencei_sc_tests))
+
+target_tests += $(rv32Zifencei_tests)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/references/I-FENCE.I-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/references/I-FENCE.I-01.reference_output
new file mode 100644
index 0000000..1a31ff3
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/references/I-FENCE.I-01.reference_output
@@ -0,0 +1,4 @@
+00000030
+00000012
+00000042
+001101b3
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S
new file mode 100644
index 0000000..60d7ccf
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S
@@ -0,0 +1,112 @@
+# RISC-V Compliance Test I-FENCE.I-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction FENCE.I.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A - test fence\n");
+
+    # Addresses for test data and results
+    la      x16, test_A_data
+    la      x17, test_A_res
+
+    # Register initialization
+    li      x3, 0
+
+    # Load testdata
+    lw      x1, 0(x16)
+    lw      x2, 4(x16)
+
+    # Test
+    la      x20, instr_A_src
+    la      x21, instr_A_dst
+    lw      x15, 0(x20)
+    sw      x15, 0(x21)
+    fence.i
+instr_A_dst:
+    lui     x2, 0
+
+    # Store results
+    sw      x1, 0(x17)
+    sw      x2, 4(x17)
+    sw      x3, 8(x17)
+    sw      x15, 12(x17)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x2,  0x00000012)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x3,  0x00000042)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x15, 0x001101B3)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+instr_A_src:
+    add     x3, x2, x1
+
+test_A_data:
+    .word 0x30
+    .word 0x12
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/.gitignore b/tests/riscv-compliance/riscv-test-suite/rv32i/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/Makefile b/tests/riscv-compliance/riscv-test-suite/rv32i/Makefile
new file mode 100644
index 0000000..101607b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/Makefile
@@ -0,0 +1,59 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+act_dir := .
+src_dir := $(act_dir)/src
+work_dir := $(ROOTDIR)/build_generated
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
+
+include $(act_dir)/Makefrag
+ifneq ($(RISCV_TEST),)
+    target_tests = $(RISCV_TEST).elf
+endif
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+vpath %.S $(act_dir)
+
+INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include
+ifeq ($(wildcard $(INCLUDE)),)
+    $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
+endif
+-include $(INCLUDE)
+
+#------------------------------------------------------------
+# Build and run assembly tests
+
+%.log: %.elf
+	$(V) echo "Execute $(@)"
+	#$(V) $(RUN_TARGET)
+
+
+define compile_template
+
+$(work_dir_isa)/%.elf: $(src_dir)/%.S
+	$(V) echo "Compile $$(@)"
+	@mkdir -p $$(@D)
+	$(V) $(COMPILE_TARGET)
+
+.PRECIOUS: $(work_dir_isa)/%.elf
+
+endef
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32))
+
+target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
+target_log = $(patsubst %.elf,%.log,$(target_elf))
+
+run: $(target_log)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(work_dir_isa)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/Makefrag b/tests/riscv-compliance/riscv-test-suite/rv32i/Makefrag
new file mode 100644
index 0000000..2157363
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/Makefrag
@@ -0,0 +1,83 @@
+# RISC-V Compliance Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I compliance tests
+
+rv32i_sc_tests = \
+    I-ENDIANESS-01 \
+    I-RF_x0-01 \
+    I-RF_size-01 \
+    I-RF_width-01 \
+    I-MISALIGN_JMP-01 \
+    I-MISALIGN_LDST-01 \
+    I-DELAY_SLOTS-01 \
+    I-JAL-01 \
+    I-JALR-01 \
+    I-LUI-01 \
+    I-AUIPC-01 \
+    I-LW-01 \
+    I-LH-01 \
+    I-LHU-01 \
+    I-LB-01 \
+    I-LBU-01 \
+    I-SW-01 \
+    I-SH-01 \
+    I-SB-01 \
+    I-ADD-01 \
+    I-ADDI-01 \
+    I-AND-01 \
+    I-OR-01 \
+    I-ORI-01 \
+    I-XORI-01 \
+    I-XOR-01 \
+    I-SUB-01 \
+    I-ANDI-01 \
+    I-SLTI-01 \
+    I-SLTIU-01 \
+    I-BEQ-01 \
+    I-BNE-01 \
+    I-BLT-01 \
+    I-BLTU-01 \
+    I-BGE-01 \
+    I-BGEU-01 \
+    I-SRLI-01 \
+    I-SLLI-01 \
+    I-SRAI-01 \
+    I-SLL-01 \
+    I-SRL-01 \
+    I-SRA-01 \
+    I-SLT-01 \
+    I-SLTU-01 \
+    I-NOP-01 \
+    I-ECALL-01 \
+    I-EBREAK-01 \
+    I-IO-01 \
+
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/report.txt b/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/report.txt
new file mode 100644
index 0000000..482c079
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/report.txt
@@ -0,0 +1,3938 @@
+This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv
+
+COVERGROUP COVERAGE:
+----------------------------------------------------------------------------------------------------------
+Covergroup                                             Metric       Goal    Status               
+                                                                                                         
+----------------------------------------------------------------------------------------------------------
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/add_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   110        110                      
+    missing/total bins:                                     0        110                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint add_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      6          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        7          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        6          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        6          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        6          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        6          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        4          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint add_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      8          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        3          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        2          1    Covered              
+        bin auto[A0]                                        2          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        3          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        3          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                      10          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint add_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      4          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        3          1    Covered              
+        bin auto[T0]                                        4          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        2          1    Covered              
+        bin auto[A0]                                        2          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        3          1    Covered              
+        bin auto[A5]                                        3          1    Covered              
+        bin auto[A6]                                        3          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        3          1    Covered              
+        bin auto[S10]                                       3          1    Covered              
+        bin auto[S11]                                       3          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint add_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 53          1    Covered              
+        bin auto[NEGATIVE]                                 23          1    Covered              
+    Coverpoint add_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 52          1    Covered              
+        bin auto[NEGATIVE]                                 24          1    Covered              
+    Coverpoint add_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 43          1    Covered              
+        bin auto[NEGATIVE]                                 33          1    Covered              
+    Cross add_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 8          8                      
+        missing/total bins:                                 0          8                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                           29          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                            5          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                            5          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                            4          1    Covered              
+        bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                            7          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                           11          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                           12          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                            3          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sub_cg 
+                                                       98.21%        100    Uncovered            
+    covered/total bins:                                   109        110                      
+    missing/total bins:                                     1        110                      
+    % Hit:                                             99.09%        100                      
+    Coverpoint sub_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      3          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        3          1    Covered              
+        bin auto[A0]                                        2          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       2          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint sub_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                       21          1    Covered              
+        bin auto[SP]                                        8          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        6          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        3          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sub_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      3          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        3          1    Covered              
+        bin auto[A0]                                        2          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       2          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint sub_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 26          1    Covered              
+        bin auto[NEGATIVE]                                 40          1    Covered              
+    Coverpoint sub_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 45          1    Covered              
+    Coverpoint sub_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 47          1    Covered              
+        bin auto[NEGATIVE]                                 19          1    Covered              
+    Cross sub_cg::cp_sign_cross                        87.50%        100    Uncovered            
+        covered/total bins:                                 7          8                      
+        missing/total bins:                                 1          8                      
+        % Hit:                                         87.50%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                            7          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                            1          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                            9          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                           30          1    Covered              
+        bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                            4          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                            9          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                            6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                            0          1    ZERO                 
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/addi_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    78         78                      
+    missing/total bins:                                     0         78                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint addi_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                   1237          1    Covered              
+        bin auto[RA]                                      556          1    Covered              
+        bin auto[SP]                                      178          1    Covered              
+        bin auto[GP]                                       50          1    Covered              
+        bin auto[TP]                                       23          1    Covered              
+        bin auto[T0]                                      376          1    Covered              
+        bin auto[T1]                                       26          1    Covered              
+        bin auto[T2]                                       36          1    Covered              
+        bin auto[S0]                                       48          1    Covered              
+        bin auto[S1]                                       38          1    Covered              
+        bin auto[A0]                                       86          1    Covered              
+        bin auto[A1]                                       26          1    Covered              
+        bin auto[A2]                                       11          1    Covered              
+        bin auto[A3]                                       23          1    Covered              
+        bin auto[A4]                                       10          1    Covered              
+        bin auto[A5]                                       10          1    Covered              
+        bin auto[A6]                                       13          1    Covered              
+        bin auto[A7]                                       12          1    Covered              
+        bin auto[S2]                                       10          1    Covered              
+        bin auto[S3]                                       35          1    Covered              
+        bin auto[S4]                                       13          1    Covered              
+        bin auto[S5]                                       35          1    Covered              
+        bin auto[S6]                                       27          1    Covered              
+        bin auto[S7]                                       23          1    Covered              
+        bin auto[S8]                                       48          1    Covered              
+        bin auto[S9]                                       39          1    Covered              
+        bin auto[S10]                                      39          1    Covered              
+        bin auto[S11]                                      29          1    Covered              
+        bin auto[T3]                                       10          1    Covered              
+        bin auto[T4]                                       23          1    Covered              
+        bin auto[T5]                                       34          1    Covered              
+        bin auto[T6]                                       15          1    Covered              
+    Coverpoint addi_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      9          1    Covered              
+        bin auto[RA]                                      549          1    Covered              
+        bin auto[SP]                                      208          1    Covered              
+        bin auto[GP]                                      170          1    Covered              
+        bin auto[TP]                                       46          1    Covered              
+        bin auto[T0]                                      494          1    Covered              
+        bin auto[T1]                                       77          1    Covered              
+        bin auto[T2]                                       73          1    Covered              
+        bin auto[S0]                                       60          1    Covered              
+        bin auto[S1]                                       60          1    Covered              
+        bin auto[A0]                                      156          1    Covered              
+        bin auto[A1]                                       60          1    Covered              
+        bin auto[A2]                                       47          1    Covered              
+        bin auto[A3]                                       59          1    Covered              
+        bin auto[A4]                                       60          1    Covered              
+        bin auto[A5]                                       60          1    Covered              
+        bin auto[A6]                                       63          1    Covered              
+        bin auto[A7]                                       61          1    Covered              
+        bin auto[S2]                                       59          1    Covered              
+        bin auto[S3]                                       60          1    Covered              
+        bin auto[S4]                                       35          1    Covered              
+        bin auto[S5]                                       57          1    Covered              
+        bin auto[S6]                                       60          1    Covered              
+        bin auto[S7]                                       59          1    Covered              
+        bin auto[S8]                                       60          1    Covered              
+        bin auto[S9]                                       61          1    Covered              
+        bin auto[S10]                                      61          1    Covered              
+        bin auto[S11]                                      63          1    Covered              
+        bin auto[T3]                                       46          1    Covered              
+        bin auto[T4]                                       59          1    Covered              
+        bin auto[T5]                                       83          1    Covered              
+        bin auto[T6]                                       64          1    Covered              
+    Coverpoint addi_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                               1995          1    Covered              
+        bin auto[NEGATIVE]                               1144          1    Covered              
+    Coverpoint addi_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                               1692          1    Covered              
+        bin auto[NEGATIVE]                               1447          1    Covered              
+    Coverpoint addi_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                               1531          1    Covered              
+        bin auto[NEGATIVE]                               1608          1    Covered              
+    Cross addi_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 8          8                      
+        missing/total bins:                                 0          8                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                         1148          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> 
+                                                            1          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                          456          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> 
+                                                           87          1    Covered              
+        bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                            2          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> 
+                                                          380          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                          389          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> 
+                                                          676          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lui_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    34         34                      
+    missing/total bins:                                     0         34                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint lui_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      5          1    Covered              
+        bin auto[RA]                                      274          1    Covered              
+        bin auto[SP]                                       46          1    Covered              
+        bin auto[GP]                                       29          1    Covered              
+        bin auto[TP]                                       32          1    Covered              
+        bin auto[T0]                                       34          1    Covered              
+        bin auto[T1]                                       20          1    Covered              
+        bin auto[T2]                                       18          1    Covered              
+        bin auto[S0]                                       43          1    Covered              
+        bin auto[S1]                                       32          1    Covered              
+        bin auto[A0]                                       80          1    Covered              
+        bin auto[A1]                                       20          1    Covered              
+        bin auto[A2]                                       18          1    Covered              
+        bin auto[A3]                                       18          1    Covered              
+        bin auto[A4]                                        4          1    Covered              
+        bin auto[A5]                                        4          1    Covered              
+        bin auto[A6]                                        4          1    Covered              
+        bin auto[A7]                                        5          1    Covered              
+        bin auto[S2]                                        5          1    Covered              
+        bin auto[S3]                                       29          1    Covered              
+        bin auto[S4]                                       32          1    Covered              
+        bin auto[S5]                                       32          1    Covered              
+        bin auto[S6]                                       21          1    Covered              
+        bin auto[S7]                                       18          1    Covered              
+        bin auto[S8]                                       42          1    Covered              
+        bin auto[S9]                                       32          1    Covered              
+        bin auto[S10]                                      32          1    Covered              
+        bin auto[S11]                                      23          1    Covered              
+        bin auto[T3]                                       18          1    Covered              
+        bin auto[T4]                                       17          1    Covered              
+        bin auto[T5]                                        4          1    Covered              
+        bin auto[T6]                                        4          1    Covered              
+    Coverpoint lui_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                723          1    Covered              
+        bin auto[NEGATIVE]                                272          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/auipc_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    34         34                      
+    missing/total bins:                                     0         34                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint auipc_cg::cp_rd                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                      196          1    Covered              
+        bin auto[SP]                                      106          1    Covered              
+        bin auto[GP]                                       22          1    Covered              
+        bin auto[TP]                                       17          1    Covered              
+        bin auto[T0]                                      331          1    Covered              
+        bin auto[T1]                                        7          1    Covered              
+        bin auto[T2]                                       19          1    Covered              
+        bin auto[S0]                                        8          1    Covered              
+        bin auto[S1]                                        8          1    Covered              
+        bin auto[A0]                                        7          1    Covered              
+        bin auto[A1]                                        7          1    Covered              
+        bin auto[A2]                                        7          1    Covered              
+        bin auto[A3]                                        7          1    Covered              
+        bin auto[A4]                                        7          1    Covered              
+        bin auto[A5]                                        7          1    Covered              
+        bin auto[A6]                                       10          1    Covered              
+        bin auto[A7]                                        8          1    Covered              
+        bin auto[S2]                                        7          1    Covered              
+        bin auto[S3]                                        7          1    Covered              
+        bin auto[S4]                                        7          1    Covered              
+        bin auto[S5]                                        7          1    Covered              
+        bin auto[S6]                                        7          1    Covered              
+        bin auto[S7]                                        7          1    Covered              
+        bin auto[S8]                                        7          1    Covered              
+        bin auto[S9]                                        8          1    Covered              
+        bin auto[S10]                                       8          1    Covered              
+        bin auto[S11]                                       7          1    Covered              
+        bin auto[T3]                                        7          1    Covered              
+        bin auto[T4]                                        7          1    Covered              
+        bin auto[T5]                                        7          1    Covered              
+        bin auto[T6]                                       12          1    Covered              
+    Coverpoint auipc_cg::cp_rd_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 54          1    Covered              
+        bin auto[NEGATIVE]                                827          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sra_cg 
+                                                       85.71%        100    Uncovered            
+    covered/total bins:                                   103        106                      
+    missing/total bins:                                     3        106                      
+    % Hit:                                             97.16%        100                      
+    Coverpoint sra_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sra_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sra_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sra_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint sra_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[POSITIVE]                                 33          1    Covered              
+        bin auto[NEGATIVE]                                  0          1    ZERO                 
+    Coverpoint sra_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 22          1    Covered              
+        bin auto[NEGATIVE]                                 11          1    Covered              
+    Cross sra_cg::cp_sign_cross                        50.00%        100    Uncovered            
+        covered/total bins:                                 2          4                      
+        missing/total bins:                                 2          4                      
+        % Hit:                                         50.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                21          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                12          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sll_cg 
+                                                       85.71%        100    Uncovered            
+    covered/total bins:                                   103        106                      
+    missing/total bins:                                     3        106                      
+    % Hit:                                             97.16%        100                      
+    Coverpoint sll_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sll_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sll_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sll_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint sll_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[POSITIVE]                                 33          1    Covered              
+        bin auto[NEGATIVE]                                  0          1    ZERO                 
+    Coverpoint sll_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 22          1    Covered              
+        bin auto[NEGATIVE]                                 11          1    Covered              
+    Cross sll_cg::cp_sign_cross                        50.00%        100    Uncovered            
+        covered/total bins:                                 2          4                      
+        missing/total bins:                                 2          4                      
+        % Hit:                                         50.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                21          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                12          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/srl_cg 
+                                                       85.71%        100    Uncovered            
+    covered/total bins:                                   103        106                      
+    missing/total bins:                                     3        106                      
+    % Hit:                                             97.16%        100                      
+    Coverpoint srl_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srl_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srl_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srl_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint srl_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[POSITIVE]                                 33          1    Covered              
+        bin auto[NEGATIVE]                                  0          1    ZERO                 
+    Coverpoint srl_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 30          1    Covered              
+        bin auto[NEGATIVE]                                  3          1    Covered              
+    Cross srl_cg::cp_sign_cross                        50.00%        100    Uncovered            
+        covered/total bins:                                 2          4                      
+        missing/total bins:                                 2          4                      
+        % Hit:                                         50.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                21          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                12          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 0          1    ZERO                 
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/srai_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    68         68                      
+    missing/total bins:                                     0         68                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint srai_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srai_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srai_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint srai_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 22          1    Covered              
+        bin auto[NEGATIVE]                                 11          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/slli_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    68         68                      
+    missing/total bins:                                     0         68                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint slli_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        2          1    Covered              
+        bin auto[A0]                                       50          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       2          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint slli_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        2          1    Covered              
+        bin auto[A0]                                       50          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       2          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint slli_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                100          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint slli_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 22          1    Covered              
+        bin auto[NEGATIVE]                                 90          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/srli_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    68         68                      
+    missing/total bins:                                     0         68                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint srli_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srli_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint srli_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint srli_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 30          1    Covered              
+        bin auto[NEGATIVE]                                  3          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/xor_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   110        110                      
+    missing/total bins:                                     0        110                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint xor_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint xor_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint xor_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint xor_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint xor_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 20          1    Covered              
+        bin auto[NEGATIVE]                                 13          1    Covered              
+    Coverpoint xor_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 14          1    Covered              
+        bin auto[NEGATIVE]                                 19          1    Covered              
+    Coverpoint xor_cg::cp_logical                     100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                   4          1    Covered              
+        bin auto[DIFFERENT]                                21          1    Covered              
+    Cross xor_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                11          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/or_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   110        110                      
+    missing/total bins:                                     0        110                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint or_cg::cp_rs1                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint or_cg::cp_rs2                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint or_cg::cp_rd                           100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint or_cg::cp_rs1_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint or_cg::cp_rs2_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint or_cg::cp_rd_sign                      100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 12          1    Covered              
+        bin auto[NEGATIVE]                                 21          1    Covered              
+    Coverpoint or_cg::cp_logical                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                   4          1    Covered              
+        bin auto[DIFFERENT]                                21          1    Covered              
+    Cross or_cg::cp_sign_cross                        100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                11          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/and_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   110        110                      
+    missing/total bins:                                     0        110                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint and_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint and_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint and_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint and_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint and_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint and_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 31          1    Covered              
+        bin auto[NEGATIVE]                                  2          1    Covered              
+    Coverpoint and_cg::cp_logical                     100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                   4          1    Covered              
+        bin auto[DIFFERENT]                                21          1    Covered              
+    Cross and_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                11          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/xori_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    78         78                      
+    missing/total bins:                                     0         78                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint xori_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint xori_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint xori_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint xori_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 10          1    Covered              
+        bin auto[NEGATIVE]                                 23          1    Covered              
+    Coverpoint xori_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 12          1    Covered              
+        bin auto[NEGATIVE]                                 21          1    Covered              
+    Coverpoint xori_cg::cp_logical                    100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                   2          1    Covered              
+        bin auto[DIFFERENT]                                23          1    Covered              
+    Cross xori_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 4          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 8          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                17          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/ori_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    78         78                      
+    missing/total bins:                                     0         78                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint ori_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint ori_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint ori_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint ori_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                  6          1    Covered              
+        bin auto[NEGATIVE]                                 27          1    Covered              
+    Coverpoint ori_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 13          1    Covered              
+        bin auto[NEGATIVE]                                 20          1    Covered              
+    Coverpoint ori_cg::cp_logical                     100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                   3          1    Covered              
+        bin auto[DIFFERENT]                                22          1    Covered              
+    Cross ori_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 5          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 8          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                16          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/andi_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    78         78                      
+    missing/total bins:                                     0         78                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint andi_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                       24          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint andi_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                       24          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint andi_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 35          1    Covered              
+    Coverpoint andi_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 52          1    Covered              
+        bin auto[NEGATIVE]                                  4          1    Covered              
+    Coverpoint andi_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 36          1    Covered              
+        bin auto[NEGATIVE]                                 20          1    Covered              
+    Coverpoint andi_cg::cp_logical                    100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin auto[IDENTICAL]                                 4          1    Covered              
+        bin auto[OPPOSITE]                                  4          1    Covered              
+        bin auto[SIMILAR]                                  12          1    Covered              
+        bin auto[DIFFERENT]                                36          1    Covered              
+    Cross andi_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 5          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                31          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                16          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/slt_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   106        106                      
+    missing/total bins:                                     0        106                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint slt_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint slt_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint slt_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint slt_cg::cp_result                      100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        20          1    Covered              
+        bin auto[1]                                        13          1    Covered              
+    Coverpoint slt_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint slt_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Cross slt_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                11          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltu_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                   106        106                      
+    missing/total bins:                                     0        106                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint sltu_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sltu_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sltu_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint sltu_cg::cp_result                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        19          1    Covered              
+        bin auto[1]                                        14          1    Covered              
+    Coverpoint sltu_cg::cp_rs2                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sltu_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Cross sltu_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                11          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/slti_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    74         74                      
+    missing/total bins:                                     0         74                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint slti_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint slti_cg::cp_rd                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint slti_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint slti_cg::cp_result                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        26          1    Covered              
+        bin auto[1]                                         7          1    Covered              
+    Coverpoint slti_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 13          1    Covered              
+        bin auto[NEGATIVE]                                 20          1    Covered              
+    Cross slti_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 5          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 8          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                16          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltiu_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    74         74                      
+    missing/total bins:                                     0         74                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint sltiu_cg::cp_rs1                       100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sltiu_cg::cp_rd                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sltiu_cg::cp_rs1_sign                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint sltiu_cg::cp_result                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        17          1    Covered              
+        bin auto[1]                                        16          1    Covered              
+    Coverpoint sltiu_cg::cp_imm_sign                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 13          1    Covered              
+        bin auto[NEGATIVE]                                 20          1    Covered              
+    Cross sltiu_cg::cp_sign_cross                     100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 5          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 8          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                16          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/beq_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint beq_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                       52          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint beq_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     49          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        3          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint beq_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 71          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint beq_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 71          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint beq_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 77          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint beq_cg::cp_branch_hit                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        29          1    Covered              
+        bin auto[1]                                        54          1    Covered              
+    Cross beq_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                61          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/bne_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint bne_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        4          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                       49          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bne_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     49          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bne_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 71          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bne_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 71          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bne_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 77          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint bne_cg::cp_branch_hit                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        30          1    Covered              
+        bin auto[1]                                        53          1    Covered              
+    Cross bne_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                61          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/blt_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint blt_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        4          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        2          1    Covered              
+        bin auto[A0]                                       50          1    Covered              
+        bin auto[A1]                                        2          1    Covered              
+        bin auto[A2]                                        2          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        2          1    Covered              
+        bin auto[A5]                                        2          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        2          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        2          1    Covered              
+        bin auto[S4]                                        2          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        2          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        2          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       2          1    Covered              
+        bin auto[S11]                                       2          1    Covered              
+        bin auto[T3]                                        2          1    Covered              
+        bin auto[T4]                                        2          1    Covered              
+        bin auto[T5]                                        2          1    Covered              
+        bin auto[T6]                                        2          1    Covered              
+    Coverpoint blt_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     80          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint blt_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 91          1    Covered              
+    Coverpoint blt_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                102          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint blt_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                108          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint blt_cg::cp_branch_hit                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        19          1    Covered              
+        bin auto[1]                                        95          1    Covered              
+    Cross blt_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                13          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                89          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/bge_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint bge_cg::cp_rs1                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bge_cg::cp_rs2                         100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        3          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bge_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bge_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bge_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 29          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint bge_cg::cp_branch_hit                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        19          1    Covered              
+        bin auto[1]                                        16          1    Covered              
+    Cross bge_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                13          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/bltu_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint bltu_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        3          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bltu_cg::cp_rs2                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bltu_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bltu_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bltu_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 29          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint bltu_cg::cp_branch_hit                 100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        19          1    Covered              
+        bin auto[1]                                        16          1    Covered              
+    Cross bltu_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                13          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/bgeu_cg 
+                                                      100.00%        100    Covered              
+    covered/total bins:                                    76         76                      
+    missing/total bins:                                     0         76                      
+    % Hit:                                            100.00%        100                      
+    Coverpoint bgeu_cg::cp_rs1                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        3          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bgeu_cg::cp_rs2                        100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        3          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint bgeu_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bgeu_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 23          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+    Coverpoint bgeu_cg::cp_imm_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 29          1    Covered              
+        bin auto[NEGATIVE]                                  6          1    Covered              
+    Coverpoint bgeu_cg::cp_branch_hit                 100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        19          1    Covered              
+        bin auto[1]                                        16          1    Covered              
+    Cross bgeu_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                13          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                10          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                10          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lb_cg 
+                                                       98.95%        100    Uncovered            
+    covered/total bins:                                    65         66                      
+    missing/total bins:                                     1         66                      
+    % Hit:                                             98.48%        100                      
+    Coverpoint lb_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        3          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lb_cg::cp_rd                           100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lb_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 21          1    Covered              
+        bin auto[NEGATIVE]                                 12          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lh_cg 
+                                                       99.21%        100    Uncovered            
+    covered/total bins:                                    67         68                      
+    missing/total bins:                                     1         68                      
+    % Hit:                                             98.52%        100                      
+    Coverpoint lh_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        3          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        5          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lh_cg::cp_rd                           100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        5          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lh_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 29          1    Covered              
+        bin auto[NEGATIVE]                                  8          1    Covered              
+    Coverpoint lh_cg::cp_align                        100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        35          1    Covered              
+        bin auto[1]                                         2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lw_cg 
+                                                       99.21%        100    Uncovered            
+    covered/total bins:                                    67         68                      
+    missing/total bins:                                     1         68                      
+    % Hit:                                             98.52%        100                      
+    Coverpoint lw_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                       11          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        5          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        2          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        2          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lw_cg::cp_rd                           100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        3          1    Covered              
+        bin auto[TP]                                        5          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        2          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        2          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        2          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        4          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lw_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 43          1    Covered              
+        bin auto[NEGATIVE]                                  4          1    Covered              
+    Coverpoint lw_cg::cp_align                        100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        44          1    Covered              
+        bin auto[1]                                         3          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lbu_cg 
+                                                       98.95%        100    Uncovered            
+    covered/total bins:                                    65         66                      
+    missing/total bins:                                     1         66                      
+    % Hit:                                             98.48%        100                      
+    Coverpoint lbu_cg::cp_rs1                          96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        3          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        6          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lbu_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      2          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        2          1    Covered              
+        bin auto[T0]                                        2          1    Covered              
+        bin auto[T1]                                        2          1    Covered              
+        bin auto[T2]                                        2          1    Covered              
+        bin auto[S0]                                        2          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lbu_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 25          1    Covered              
+        bin auto[NEGATIVE]                                 13          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/lhu_cg 
+                                                       99.21%        100    Uncovered            
+    covered/total bins:                                    67         68                      
+    missing/total bins:                                     1         68                      
+    % Hit:                                             98.52%        100                      
+    Coverpoint lhu_cg::cp_rs1                          96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        2          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        5          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        3          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lhu_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                      1          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        2          1    Covered              
+        bin auto[GP]                                        2          1    Covered              
+        bin auto[TP]                                        5          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint lhu_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 30          1    Covered              
+        bin auto[NEGATIVE]                                  8          1    Covered              
+    Coverpoint lhu_cg::cp_align                       100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        36          1    Covered              
+        bin auto[1]                                         2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sb_cg 
+                                                       98.95%        100    Uncovered            
+    covered/total bins:                                    65         66                      
+    missing/total bins:                                     1         66                      
+    % Hit:                                             98.48%        100                      
+    Coverpoint sb_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                       22          1    Covered              
+        bin auto[SP]                                        8          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        6          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sb_cg::cp_rs2                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     33          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sb_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 40          1    Covered              
+        bin auto[NEGATIVE]                                 24          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sh_cg 
+                                                       99.21%        100    Uncovered            
+    covered/total bins:                                    67         68                      
+    missing/total bins:                                     1         68                      
+    % Hit:                                             98.52%        100                      
+    Coverpoint sh_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                       22          1    Covered              
+        bin auto[SP]                                       12          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        6          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sh_cg::cp_rs2                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     33          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        5          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint sh_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 52          1    Covered              
+        bin auto[NEGATIVE]                                 16          1    Covered              
+    Coverpoint sh_cg::cp_misalign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                        66          1    Covered              
+        bin auto[1]                                         2          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/sw_cg 
+                                                       99.21%        100    Uncovered            
+    covered/total bins:                                    67         68                      
+    missing/total bins:                                     1         68                      
+    % Hit:                                             98.52%        100                      
+    Coverpoint sw_cg::cp_rs1                           96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                      701          1    Covered              
+        bin auto[SP]                                      354          1    Covered              
+        bin auto[GP]                                       44          1    Covered              
+        bin auto[TP]                                       21          1    Covered              
+        bin auto[T0]                                      146          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                       61          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                       33          1    Covered              
+        bin auto[A7]                                        9          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       9          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                       13          1    Covered              
+    Coverpoint sw_cg::cp_rs2                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                     81          1    Covered              
+        bin auto[RA]                                      214          1    Covered              
+        bin auto[SP]                                       70          1    Covered              
+        bin auto[GP]                                       36          1    Covered              
+        bin auto[TP]                                       47          1    Covered              
+        bin auto[T0]                                       43          1    Covered              
+        bin auto[T1]                                       38          1    Covered              
+        bin auto[T2]                                       34          1    Covered              
+        bin auto[S0]                                       35          1    Covered              
+        bin auto[S1]                                       34          1    Covered              
+        bin auto[A0]                                       33          1    Covered              
+        bin auto[A1]                                       33          1    Covered              
+        bin auto[A2]                                       33          1    Covered              
+        bin auto[A3]                                       34          1    Covered              
+        bin auto[A4]                                       33          1    Covered              
+        bin auto[A5]                                       33          1    Covered              
+        bin auto[A6]                                       33          1    Covered              
+        bin auto[A7]                                       33          1    Covered              
+        bin auto[S2]                                       34          1    Covered              
+        bin auto[S3]                                       33          1    Covered              
+        bin auto[S4]                                       33          1    Covered              
+        bin auto[S5]                                       33          1    Covered              
+        bin auto[S6]                                       33          1    Covered              
+        bin auto[S7]                                       34          1    Covered              
+        bin auto[S8]                                       33          1    Covered              
+        bin auto[S9]                                       33          1    Covered              
+        bin auto[S10]                                      34          1    Covered              
+        bin auto[S11]                                      35          1    Covered              
+        bin auto[T3]                                       34          1    Covered              
+        bin auto[T4]                                       33          1    Covered              
+        bin auto[T5]                                       80          1    Covered              
+        bin auto[T6]                                       33          1    Covered              
+    Coverpoint sw_cg::cp_imm_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                               1404          1    Covered              
+        bin auto[NEGATIVE]                                  8          1    Covered              
+    Coverpoint sw_cg::cp_misalign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[0]                                       943          1    Covered              
+        bin auto[1]                                       469          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/jal_cg 
+                                                       83.33%        100    Uncovered            
+    covered/total bins:                                    35         36                      
+    missing/total bins:                                     1         36                      
+    % Hit:                                             97.22%        100                      
+    Coverpoint jal_cg::cp_imm_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                  9          1    Covered              
+        bin auto[NEGATIVE]                                164          1    Covered              
+    Coverpoint jal_cg::cp_rd                          100.00%        100    Covered              
+        covered/total bins:                                32         32                      
+        missing/total bins:                                 0         32                      
+        % Hit:                                        100.00%        100                      
+        bin auto[ZERO]                                    142          1    Covered              
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint jal_cg::cp_rd_align                     50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[0]                                       173          1    Covered              
+        bin auto[1]                                         0          1    ZERO                 
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/jalr_cg 
+                                                       66.14%        100    Uncovered            
+    covered/total bins:                                    37         44                      
+    missing/total bins:                                     7         44                      
+    % Hit:                                             84.09%        100                      
+    Coverpoint jalr_cg::cp_imm_sign                    50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[POSITIVE]                                 31          1    Covered              
+        bin auto[NEGATIVE]                                  0          1    ZERO                 
+    Coverpoint jalr_cg::cp_rd                          96.87%        100    Uncovered            
+        covered/total bins:                                31         32                      
+        missing/total bins:                                 1         32                      
+        % Hit:                                         96.87%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        1          1    Covered              
+        bin auto[SP]                                        1          1    Covered              
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        1          1    Covered              
+        bin auto[T1]                                        1          1    Covered              
+        bin auto[T2]                                        1          1    Covered              
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        1          1    Covered              
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        1          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        1          1    Covered              
+    Coverpoint jalr_cg::cp_rd_align                    50.00%        100    Uncovered            
+        covered/total bins:                                 1          2                      
+        missing/total bins:                                 1          2                      
+        % Hit:                                         50.00%        100                      
+        bin auto[0]                                        31          1    Covered              
+        bin auto[1]                                         0          1    ZERO                 
+    Coverpoint jalr_cg::cp_rs1_link                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin ra                                              2          1    Covered              
+        bin t1                                              1          1    Covered              
+        default bin non_link                               28               Occurred             
+    Coverpoint jalr_cg::cp_rd_link                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin ra                                              1          1    Covered              
+        bin t1                                              1          1    Covered              
+        default bin non_link                               29               Occurred             
+    Cross jalr_cg::cp_ras                               0.00%        100    ZERO                 
+        covered/total bins:                                 0          4                      
+        missing/total bins:                                 4          4                      
+        % Hit:                                          0.00%        100                      
+        bin <ra,ra>                                         0          1    ZERO                 
+        bin <t1,ra>                                         0          1    ZERO                 
+        bin <ra,t1>                                         0          1    ZERO                 
+        bin <t1,t1>                                         0          1    ZERO                 
+
+TOTAL COVERGROUP COVERAGE: 97.23%  COVERGROUP TYPES: 37
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/summary.txt b/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/summary.txt
new file mode 100644
index 0000000..ab655e6
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/coverage/summary.txt
@@ -0,0 +1,174 @@
+This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv
+
+    Coverpoint add_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint add_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint add_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint add_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint add_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint add_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint sub_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint addi_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint addi_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint addi_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint addi_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint addi_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint lui_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint lui_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint auipc_cg::cp_rd                        100.00%        100    Covered              
+    Coverpoint auipc_cg::cp_rd_sign                   100.00%        100    Covered              
+    Coverpoint sra_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint sra_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint sra_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint sra_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint sra_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+    Coverpoint sra_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint sll_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint sll_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint sll_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint sll_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint sll_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+    Coverpoint sll_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint srl_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint srl_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint srl_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint srl_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint srl_cg::cp_rs2_sign                     50.00%        100    Uncovered            
+    Coverpoint srl_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint srai_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint srai_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint srai_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint srai_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint slli_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint slli_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint slli_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint slli_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint srli_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint srli_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint srli_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint srli_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint xor_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint or_cg::cp_rs1                          100.00%        100    Covered              
+    Coverpoint or_cg::cp_rs2                          100.00%        100    Covered              
+    Coverpoint or_cg::cp_rd                           100.00%        100    Covered              
+    Coverpoint or_cg::cp_rs1_sign                     100.00%        100    Covered              
+    Coverpoint or_cg::cp_rs2_sign                     100.00%        100    Covered              
+    Coverpoint or_cg::cp_rd_sign                      100.00%        100    Covered              
+    Coverpoint and_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint and_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint and_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint and_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint and_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint and_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint xori_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint xori_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint xori_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint xori_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint xori_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint ori_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint ori_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint ori_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint ori_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint ori_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint andi_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint andi_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint andi_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint andi_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint andi_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint slt_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint slt_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint slt_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint slt_cg::cp_result                      100.00%        100    Covered              
+    Coverpoint slt_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint slt_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_result                     100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_rs2                        100.00%        100    Covered              
+    Coverpoint sltu_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint slti_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint slti_cg::cp_rd                         100.00%        100    Covered              
+    Coverpoint slti_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint slti_cg::cp_result                     100.00%        100    Covered              
+    Coverpoint slti_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint sltiu_cg::cp_rs1                       100.00%        100    Covered              
+    Coverpoint sltiu_cg::cp_rd                        100.00%        100    Covered              
+    Coverpoint sltiu_cg::cp_rs1_sign                  100.00%        100    Covered              
+    Coverpoint sltiu_cg::cp_result                    100.00%        100    Covered              
+    Coverpoint sltiu_cg::cp_imm_sign                  100.00%        100    Covered              
+    Coverpoint beq_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint beq_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint beq_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint beq_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint beq_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint beq_cg::cp_branch_hit                  100.00%        100    Covered              
+    Coverpoint bne_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint bne_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint bne_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint bne_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint bne_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint bne_cg::cp_branch_hit                  100.00%        100    Covered              
+    Coverpoint blt_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint blt_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint blt_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint blt_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint blt_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint blt_cg::cp_branch_hit                  100.00%        100    Covered              
+    Coverpoint bge_cg::cp_rs1                         100.00%        100    Covered              
+    Coverpoint bge_cg::cp_rs2                         100.00%        100    Covered              
+    Coverpoint bge_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint bge_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint bge_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint bge_cg::cp_branch_hit                  100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_rs2                        100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint bltu_cg::cp_branch_hit                 100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_rs1                        100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_rs2                        100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_imm_sign                   100.00%        100    Covered              
+    Coverpoint bgeu_cg::cp_branch_hit                 100.00%        100    Covered              
+    Coverpoint lb_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint lb_cg::cp_rd                           100.00%        100    Covered              
+    Coverpoint lb_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint lh_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint lh_cg::cp_rd                           100.00%        100    Covered              
+    Coverpoint lh_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint lw_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint lw_cg::cp_rd                           100.00%        100    Covered              
+    Coverpoint lw_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint lbu_cg::cp_rs1                          96.87%        100    Uncovered            
+    Coverpoint lbu_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint lbu_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint lhu_cg::cp_rs1                          96.87%        100    Uncovered            
+    Coverpoint lhu_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint lhu_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint sb_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint sb_cg::cp_rs2                          100.00%        100    Covered              
+    Coverpoint sb_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint sh_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint sh_cg::cp_rs2                          100.00%        100    Covered              
+    Coverpoint sh_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint sw_cg::cp_rs1                           96.87%        100    Uncovered            
+    Coverpoint sw_cg::cp_rs2                          100.00%        100    Covered              
+    Coverpoint sw_cg::cp_imm_sign                     100.00%        100    Covered              
+    Coverpoint jal_cg::cp_imm_sign                    100.00%        100    Covered              
+    Coverpoint jal_cg::cp_rd                          100.00%        100    Covered              
+    Coverpoint jalr_cg::cp_imm_sign                    50.00%        100    Uncovered            
+    Coverpoint jalr_cg::cp_rd                          96.87%        100    Uncovered            
+    Coverpoint jalr_cg::cp_rs1_link                   100.00%        100    Covered              
+    Coverpoint jalr_cg::cp_rd_link                    100.00%        100    Covered              
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output
new file mode 100644
index 0000000..d9ab753
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output
@@ -0,0 +1,36 @@
+00000000
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output
new file mode 100644
index 0000000..354cd38
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output
new file mode 100644
index 0000000..a6c255f
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output
new file mode 100644
index 0000000..7f4f02a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output
new file mode 100644
index 0000000..deab1d6
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output
new file mode 100644
index 0000000..ed14a43
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output
new file mode 100644
index 0000000..7cf39c4
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output
new file mode 100644
index 0000000..5ac2956
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output
new file mode 100644
index 0000000..bc8d944
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output
new file mode 100644
index 0000000..ea34398
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output
new file mode 100644
index 0000000..836e69f
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-DELAY_SLOTS-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-DELAY_SLOTS-01.reference_output
new file mode 100644
index 0000000..b0a5086
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-DELAY_SLOTS-01.reference_output
@@ -0,0 +1,8 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output
new file mode 100644
index 0000000..b48c634
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-EBREAK-01.reference_output
@@ -0,0 +1,4 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output
new file mode 100644
index 0000000..c91123a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ECALL-01.reference_output
@@ -0,0 +1,4 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ENDIANESS-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ENDIANESS-01.reference_output
new file mode 100644
index 0000000..b3328cf
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-ENDIANESS-01.reference_output
@@ -0,0 +1,8 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-IO-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-IO-01.reference_output
new file mode 100644
index 0000000..e560ff4
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-IO-01.reference_output
@@ -0,0 +1,44 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output
new file mode 100644
index 0000000..5e6e467
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output
new file mode 100644
index 0000000..975966e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output
@@ -0,0 +1,36 @@
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diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output
new file mode 100644
index 0000000..f9590a9
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output
@@ -0,0 +1,36 @@
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+0000091a
+08000000
+00ffffed
+00000001
+0000ffff
+00000000
+ffffffff
+ffffffff
+ffffffff
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output
new file mode 100644
index 0000000..bbfdc30
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output
@@ -0,0 +1,36 @@
+00000000
+00000800
+00000001
+00001a33
+80000000
+fffff5cc
+07654322
+7ffffffe
+80000002
+f89abcde
+00000a34
+80000000
+ffffe5cd
+00000000
+fffff800
+00000000
+ffffffff
+00000800
+00000001
+00001a33
+80000000
+fffff5cc
+07654322
+7ffffffe
+80000002
+f89abcde
+00000a34
+80000000
+ffffe5cd
+00000000
+fffff800
+00000000
+ffffffff
+ffffffff
+ffffffff
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output
new file mode 100644
index 0000000..364db51
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output
@@ -0,0 +1,36 @@
+ffffffff
+00000001
+00000000
+000007ff
+00000000
+00000800
+07654321
+7fffffff
+00000001
+ffffffff
+00001234
+80000000
+ffffedcc
+ffffffff
+fffff801
+fffffffe
+00000000
+00000001
+00000000
+000007ff
+00000000
+00000800
+07654321
+7fffffff
+00000001
+ffffffff
+00001234
+80000000
+ffffedcc
+ffffffff
+fffff801
+fffffffe
+ffffffff
+ffffffff
+ffffffff
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output
new file mode 100644
index 0000000..e8b700b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output
@@ -0,0 +1,36 @@
+00000000
+fffff800
+ffffffff
+ffffea33
+80000000
+00001a34
+f89abcde
+7ffffffe
+7ffffffe
+f89abcde
+00001a34
+80000000
+ffffea33
+00000000
+fffff800
+00000000
+ffffffff
+fffff800
+ffffffff
+ffffea33
+80000000
+00001a34
+f89abcde
+7ffffffe
+7ffffffe
+f89abcde
+00001a34
+80000000
+ffffea33
+00000000
+fffff800
+00000000
+ffffffff
+ffffffff
+ffffffff
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output
new file mode 100644
index 0000000..4b85ed7
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output
@@ -0,0 +1,36 @@
+00000000
+fffff800
+ffffffff
+ffffffff
+fffff800
+fffff000
+f89abb21
+7ffffffe
+fffff801
+000007ff
+ffffea34
+80000000
+ffffea33
+00000000
+fffff800
+00000000
+ffffffff
+fffff800
+ffffffff
+ffffffff
+fffff800
+fffff000
+f89abb21
+7ffffffe
+fffff801
+000007ff
+ffffea34
+80000000
+ffffea33
+00000000
+fffff800
+00000000
+ffffffff
+ffffffff
+ffffffff
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S
new file mode 100644
index 0000000..f2f17b1
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test ADD-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'ADD'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(add, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(add, x1, x30, x15, 0xfffff802, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(add, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(add, x3, x28, x13, 0xfffff5cb, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(add, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(add, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(add, x6, x25, x10, 0x7654320, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(add, x7, x24, x9, 0x80000000, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(add, x8, x23, x8, 0x80000000, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(add, x9, x22, x7, 0x7654320, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(add, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(add, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(add, x12, x19, x4, 0xfffff5cb, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(add, x13, x18, x3, 0xfffffffe, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(add, x14, x17, x2, 0xfffff802, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(add, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(add, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(add, x17, x14, x31, 0xfffff802, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(add, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(add, x19, x12, x29, 0xfffff5cb, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(add, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(add, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(add, x22, x9, x26, 0x7654320, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(add, x23, x8, x25, 0x80000000, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(add, x24, x7, x24, 0x80000000, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(add, x25, x6, x23, 0x7654320, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(add, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(add, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(add, x28, x3, x20, 0xfffff5cb, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(add, x29, x2, x19, 0xfffffffe, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(add, x30, x1, x18, 0xfffff802, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(add, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S
new file mode 100644
index 0000000..264a439
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test ADDI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'ADDI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(addi, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(addi, x1, x30, 0xfffff802, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(addi, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(addi, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(addi, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(addi, x5, x26, 0x0, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(addi, x6, x25, 0x7653b21, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(addi, x7, x24, 0x80000000, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(addi, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(addi, x9, x22, 0xfffff7ff, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(addi, x10, x21, 0xa34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(addi, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(addi, x12, x19, 0xfffff5cb, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(addi, x13, x18, 0xfffffffe, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(addi, x14, x17, 0xfffff802, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(addi, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(addi, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(addi, x17, x14, 0xfffff802, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(addi, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(addi, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(addi, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(addi, x21, x10, 0x0, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(addi, x22, x9, 0x7653b21, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(addi, x23, x8, 0x80000000, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(addi, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(addi, x25, x6, 0xfffff7ff, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(addi, x26, x5, 0xa34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(addi, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(addi, x28, x3, 0xfffff5cb, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(addi, x29, x2, 0xfffffffe, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(addi, x30, x1, 0xfffff802, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(addi, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S
new file mode 100644
index 0000000..30124be
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test AND-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'AND'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(and, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(and, x1, x30, x15, 0x1, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(and, x2, x29, x14, 0x0, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(and, x3, x28, x13, 0x5cc, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(and, x4, x27, x12, 0x0, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(and, x5, x26, x11, 0x0, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(and, x6, x25, x10, 0x7654321, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(and, x7, x24, x9, 0x1, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(and, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(and, x9, x22, x7, 0x7654321, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(and, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(and, x11, x20, x5, 0x0, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(and, x12, x19, x4, 0x5cc, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(and, x13, x18, x3, 0xffffffff, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(and, x14, x17, x2, 0x1, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(and, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(and, x16, x15, x0, 0x0, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(and, x17, x14, x31, 0x1, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(and, x18, x13, x30, 0x0, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(and, x19, x12, x29, 0x5cc, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(and, x20, x11, x28, 0x0, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(and, x21, x10, x27, 0x0, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(and, x22, x9, x26, 0x7654321, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(and, x23, x8, x25, 0x1, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(and, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(and, x25, x6, x23, 0x7654321, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(and, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(and, x27, x4, x21, 0x0, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(and, x28, x3, x20, 0x5cc, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(and, x29, x2, x19, 0xffffffff, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(and, x30, x1, x18, 0x1, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(and, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S
new file mode 100644
index 0000000..39ff107
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test ANDI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'ANDI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(andi, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(andi, x1, x30, 0x1, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(andi, x2, x29, 0x0, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(andi, x3, x28, 0x0, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(andi, x4, x27, 0x0, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(andi, x5, x26, 0x800, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(andi, x6, x25, 0x7654000, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(andi, x7, x24, 0x1, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(andi, x8, x23, 0x0, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(andi, x9, x22, 0xfffff800, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(andi, x10, x21, 0x1000, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(andi, x11, x20, 0x0, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(andi, x12, x19, 0x5cc, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(andi, x13, x18, 0xffffffff, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(andi, x14, x17, 0x1, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(andi, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(andi, x16, x15, 0x0, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(andi, x17, x14, 0x1, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(andi, x18, x13, 0x0, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(andi, x19, x12, 0x0, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(andi, x20, x11, 0x0, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(andi, x21, x10, 0x800, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(andi, x22, x9, 0x7654000, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(andi, x23, x8, 0x1, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(andi, x24, x7, 0x0, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(andi, x25, x6, 0xfffff800, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(andi, x26, x5, 0x1000, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(andi, x27, x4, 0x0, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(andi, x28, x3, 0x5cc, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(andi, x29, x2, 0xffffffff, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(andi, x30, x1, 0x1, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(andi, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S
new file mode 100644
index 0000000..b8e5008
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S
@@ -0,0 +1,391 @@
+# RISC-V Compliance Test I-AUIPC-01
+#
+#
+# Copyright (c) 2019 Imperas Software Ltd., www.imperas.com
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied.
+#
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'AUIPC'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	# Testcase 0:  imm:0x0, result rd:x0(0x0)
+1: 
+    auipc x0, 0x0
+    la x7, 1b
+    sub  x0,  x0, x7
+	sw  x0, 0(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x0, 0x0)
+
+	# Testcase 1:  imm:0x0, result rd:x1(0x0)
+1: 
+    auipc x1, 0x0
+    la x7, 1b
+    sub  x1,  x1, x7
+	sw  x1, 4(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x1, 0x0)
+
+	# Testcase 2:  imm:0x7ff, result rd:x2(0x7ff000)
+1: 
+    auipc x2, 0x7ff
+    la x7, 1b
+    sub  x2,  x2, x7
+	sw  x2, 8(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x2, 0x7ff000)
+
+	# Testcase 3:  imm:0x1, result rd:x3(0x1000)
+1: 
+    auipc x3, 0x1
+    la x7, 1b
+    sub  x3,  x3, x7
+	sw  x3, 12(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x3, 0x1000)
+
+	# Testcase 4:  imm:0x1234, result rd:x4(0x1234000)
+1: 
+    auipc x4, 0x1234
+    la x7, 1b
+    sub  x4,  x4, x7
+	sw  x4, 16(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x4, 0x1234000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	# Testcase 5:  imm:0x80000, result rd:x5(0x80000000)
+1: 
+    auipc x5, 0x80000
+    la x3, 1b
+    sub  x5,  x5, x3
+	sw  x5, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x80000000)
+
+	# Testcase 6:  imm:0x1234, result rd:x6(0x1234000)
+1: 
+    auipc x6, 0x1234
+    la x3, 1b
+    sub  x6,  x6, x3
+	sw  x6, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x1234000)
+
+	# Testcase 7:  imm:0xfffff, result rd:x7(0xfffff000)
+1: 
+    auipc x7, 0xfffff
+    la x3, 1b
+    sub  x7,  x7, x3
+	sw  x7, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xfffff000)
+
+	# Testcase 8:  imm:0x1, result rd:x8(0x1000)
+1: 
+    auipc x8, 0x1
+    la x3, 1b
+    sub  x8,  x8, x3
+	sw  x8, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1000)
+
+	# Testcase 9:  imm:0x7ffff, result rd:x9(0x7ffff000)
+1: 
+    auipc x9, 0x7ffff
+    la x3, 1b
+    sub  x9,  x9, x3
+	sw  x9, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7ffff000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	# Testcase 10:  imm:0x54321, result rd:x10(0x54321000)
+1: 
+    auipc x10, 0x54321
+    la x8, 1b
+    sub  x10,  x10, x8
+	sw  x10, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x10, 0x54321000)
+
+	# Testcase 11:  imm:0x800, result rd:x11(0x800000)
+1: 
+    auipc x11, 0x800
+    la x8, 1b
+    sub  x11,  x11, x8
+	sw  x11, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x11, 0x800000)
+
+	# Testcase 12:  imm:0x0, result rd:x12(0x0)
+1: 
+    auipc x12, 0x0
+    la x8, 1b
+    sub  x12,  x12, x8
+	sw  x12, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x12, 0x0)
+
+	# Testcase 13:  imm:0x7ff, result rd:x13(0x7ff000)
+1: 
+    auipc x13, 0x7ff
+    la x8, 1b
+    sub  x13,  x13, x8
+	sw  x13, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x13, 0x7ff000)
+
+	# Testcase 14:  imm:0x0, result rd:x14(0x0)
+1: 
+    auipc x14, 0x0
+    la x8, 1b
+    sub  x14,  x14, x8
+	sw  x14, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x14, 0x0)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	# Testcase 15:  imm:0x1, result rd:x15(0x1000)
+1: 
+    auipc x15, 0x1
+    la x4, 1b
+    sub  x15,  x15, x4
+	sw  x15, 0(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x15, 0x1000)
+
+	# Testcase 16:  imm:0x0, result rd:x16(0x0)
+1: 
+    auipc x16, 0x0
+    la x4, 1b
+    sub  x16,  x16, x4
+	sw  x16, 4(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x16, 0x0)
+
+	# Testcase 17:  imm:0x0, result rd:x17(0x0)
+1: 
+    auipc x17, 0x0
+    la x4, 1b
+    sub  x17,  x17, x4
+	sw  x17, 8(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0)
+
+	# Testcase 18:  imm:0x7ff, result rd:x18(0x7ff000)
+1: 
+    auipc x18, 0x7ff
+    la x4, 1b
+    sub  x18,  x18, x4
+	sw  x18, 12(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x18, 0x7ff000)
+
+	# Testcase 19:  imm:0x1, result rd:x19(0x1000)
+1: 
+    auipc x19, 0x1
+    la x4, 1b
+    sub  x19,  x19, x4
+	sw  x19, 16(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x19, 0x1000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	# Testcase 20:  imm:0x1234, result rd:x20(0x1234000)
+1: 
+    auipc x20, 0x1234
+    la x3, 1b
+    sub  x20,  x20, x3
+	sw  x20, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x1234000)
+
+	# Testcase 21:  imm:0x80000, result rd:x21(0x80000000)
+1: 
+    auipc x21, 0x80000
+    la x3, 1b
+    sub  x21,  x21, x3
+	sw  x21, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x80000000)
+
+	# Testcase 22:  imm:0x1234, result rd:x22(0x1234000)
+1: 
+    auipc x22, 0x1234
+    la x3, 1b
+    sub  x22,  x22, x3
+	sw  x22, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x1234000)
+
+	# Testcase 23:  imm:0xfffff, result rd:x23(0xfffff000)
+1: 
+    auipc x23, 0xfffff
+    la x3, 1b
+    sub  x23,  x23, x3
+	sw  x23, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xfffff000)
+
+	# Testcase 24:  imm:0x1, result rd:x24(0x1000)
+1: 
+    auipc x24, 0x1
+    la x3, 1b
+    sub  x24,  x24, x3
+	sw  x24, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	# Testcase 25:  imm:0x7ffff, result rd:x25(0x7ffff000)
+1: 
+    auipc x25, 0x7ffff
+    la x8, 1b
+    sub  x25,  x25, x8
+	sw  x25, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x25, 0x7ffff000)
+
+	# Testcase 26:  imm:0x54321, result rd:x26(0x54321000)
+1: 
+    auipc x26, 0x54321
+    la x8, 1b
+    sub  x26,  x26, x8
+	sw  x26, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x26, 0x54321000)
+
+	# Testcase 27:  imm:0x800, result rd:x27(0x800000)
+1: 
+    auipc x27, 0x800
+    la x8, 1b
+    sub  x27,  x27, x8
+	sw  x27, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x27, 0x800000)
+
+	# Testcase 28:  imm:0x0, result rd:x28(0x0)
+1: 
+    auipc x28, 0x0
+    la x8, 1b
+    sub  x28,  x28, x8
+	sw  x28, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x28, 0x0)
+
+	# Testcase 29:  imm:0x7ff, result rd:x29(0x7ff000)
+1: 
+    auipc x29, 0x7ff
+    la x8, 1b
+    sub  x29,  x29, x8
+	sw  x29, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x29, 0x7ff000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	# Testcase 30:  imm:0x0, result rd:x30(0x0)
+1: 
+    auipc x30, 0x0
+    la x4, 1b
+    sub  x30,  x30, x4
+	sw  x30, 0(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0)
+
+	# Testcase 31:  imm:0x1, result rd:x31(0x1000)
+1: 
+    auipc x31, 0x1
+    la x4, 1b
+    sub  x31,  x31, x4
+	sw  x31, 4(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1000)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S
new file mode 100644
index 0000000..acf1cf0
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BEQ-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BEQ'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      beq x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      beq x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      beq x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      beq x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      beq x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      beq x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      beq x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      beq x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      beq x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      beq x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      beq x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      beq x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      beq x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      beq x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      beq x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      beq x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      beq x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      beq x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      beq x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      beq x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      beq x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      beq x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      beq x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      beq x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      beq x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      beq x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      beq x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      beq x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      beq x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      beq x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      beq x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      beq x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S
new file mode 100644
index 0000000..edbe3d0
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BGE-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BGE'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      bge x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      bge x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      bge x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      bge x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      bge x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      bge x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      bge x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      bge x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      bge x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      bge x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      bge x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      bge x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      bge x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      bge x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      bge x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      bge x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      bge x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      bge x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      bge x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      bge x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      bge x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      bge x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      bge x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      bge x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      bge x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      bge x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      bge x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      bge x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      bge x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      bge x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      bge x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      bge x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S
new file mode 100644
index 0000000..7497981
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BGEU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BGEU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      bgeu x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      bgeu x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      bgeu x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      bgeu x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      bgeu x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      bgeu x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      bgeu x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      bgeu x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      bgeu x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      bgeu x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      bgeu x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      bgeu x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      bgeu x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      bgeu x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      bgeu x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      bgeu x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      bgeu x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      bgeu x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      bgeu x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      bgeu x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      bgeu x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      bgeu x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      bgeu x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      bgeu x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      bgeu x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      bgeu x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      bgeu x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      bgeu x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      bgeu x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      bgeu x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      bgeu x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      bgeu x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S
new file mode 100644
index 0000000..2e402af
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BLT-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BLT'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      blt x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      blt x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      blt x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      blt x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      blt x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      blt x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      blt x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      blt x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      blt x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      blt x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      blt x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      blt x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      blt x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      blt x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      blt x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      blt x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      blt x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      blt x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      blt x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      blt x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      blt x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      blt x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      blt x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      blt x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      blt x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      blt x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      blt x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      blt x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      blt x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      blt x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      blt x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      blt x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S
new file mode 100644
index 0000000..5e5b285
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BLTU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BLTU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      bltu x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      bltu x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      bltu x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      bltu x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      bltu x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      bltu x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      bltu x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      bltu x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      bltu x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      bltu x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      bltu x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      bltu x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      bltu x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      bltu x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      bltu x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      bltu x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      bltu x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      bltu x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      bltu x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      bltu x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      bltu x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      bltu x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      bltu x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x1, 0x123ab, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      bltu x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      bltu x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      bltu x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      bltu x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      bltu x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      bltu x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      bltu x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      bltu x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      bltu x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S
new file mode 100644
index 0000000..96d2dcd
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S
@@ -0,0 +1,496 @@
+# RISC-V Compliance Test BNE-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'BNE'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x2, test_1_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x31, -0x1; \
+      li x16, 0x0; \
+      bne x31, x16, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x30, 0x1; \
+      li x15, -0x7ff; \
+      bne x30, x15, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x29, 0x0; \
+      li x14, -0x1; \
+      bne x29, x14, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x28, 0x7ff; \
+      li x13, -0x1234; \
+      bne x28, x13, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x27, 0x0; \
+      li x12, 0x80000000; \
+      bne x27, x12, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x2, test_2_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x26, 0x800; \
+      li x11, 0x1234; \
+      bne x26, x11, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x25, 0x7654321; \
+      li x10, 0xffffffff; \
+      bne x25, x10, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x24, 0x7fffffff; \
+      li x9, 0x1; \
+      bne x24, x9, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x23, 0x1; \
+      li x8, 0x7fffffff; \
+      bne x23, x8, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x22, 0xffffffff; \
+      li x7, 0x7654321; \
+      bne x22, x7, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x7, test_3_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x21, 0x1234; \
+      li x6, 0x800; \
+      bne x21, x6, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x20, 0x80000000; \
+      li x5, 0x0; \
+      bne x20, x5, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x19, -0x1234; \
+      li x4, 0x7ff; \
+      bne x19, x4, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 12, \
+      li x1, 0xcccc; \
+	  li x18, -0x1; \
+      li x3, -0x1; \
+      bne x18, x3, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 16, \
+      li x1, 0xcccc; \
+	  li x17, -0x7ff; \
+      li x2, 0x1; \
+      bne x17, x2, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x3, test_4_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x4, x2, 0x123ab, x3, 0, \
+      li x2, 0xcccc; \
+	  li x16, 0x0; \
+      li x1, 0x0; \
+      bne x16, x1, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 4, \
+      li x1, 0xcccc; \
+	  li x15, -0x1; \
+      li x0, 0x0; \
+      bne x15, x0, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 8, \
+      li x1, 0xcccc; \
+	  li x14, 0x1; \
+      li x31, -0x7ff; \
+      bne x14, x31, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 12, \
+      li x1, 0xcccc; \
+	  li x13, 0x0; \
+      li x30, -0x1; \
+      bne x13, x30, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x4, x1, 0xcccc, x3, 16, \
+      li x1, 0xcccc; \
+	  li x12, 0x7ff; \
+      li x29, -0x1234; \
+      bne x12, x29, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x2, test_5_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+	  li x11, 0x0; \
+      li x28, 0x80000000; \
+      bne x11, x28, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 4, \
+      li x1, 0xcccc; \
+	  li x10, 0x800; \
+      li x27, 0x1234; \
+      bne x10, x27, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 8, \
+      li x1, 0xcccc; \
+	  li x9, 0x7654321; \
+      li x26, 0xffffffff; \
+      bne x9, x26, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 12, \
+      li x1, 0xcccc; \
+	  li x8, 0x7fffffff; \
+      li x25, 0x1; \
+      bne x8, x25, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x3, x1, 0xcccc, x2, 16, \
+      li x1, 0xcccc; \
+	  li x7, 0x1; \
+      li x24, 0x7fffffff; \
+      bne x7, x24, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x7, test_6_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 0, \
+      li x1, 0xcccc; \
+	  li x6, 0xffffffff; \
+      li x23, 0x7654321; \
+      bne x6, x23, 1f; \
+      li x1, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 4, \
+      li x1, 0xcccc; \
+	  li x5, 0x1234; \
+      li x22, 0x800; \
+      bne x5, x22, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 8, \
+      li x1, 0xcccc; \
+	  li x4, 0x80000000; \
+      li x21, 0x0; \
+      bne x4, x21, 2b; \
+      li x1, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 1
+    TEST_CASE(x8, x1, 0xcccc, x7, 12, \
+      li x1, 0xcccc; \
+	  li x3, -0x1234; \
+      li x20, 0x7ff; \
+      bne x3, x20, 4f; \
+      li x1, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x8, x1, 0x123ab, x7, 16, \
+      li x1, 0xcccc; \
+	  li x2, -0x1; \
+      li x19, -0x1; \
+      bne x2, x19, 5f; \
+      li x1, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x3, test_7_res
+    
+ 
+    // Result = 1
+    TEST_CASE(x4, x2, 0xcccc, x3, 0, \
+      li x2, 0xcccc; \
+	  li x1, -0x7ff; \
+      li x18, 0x1; \
+      bne x1, x18, 1f; \
+      li x2, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x4, x1, 0x123ab, x3, 4, \
+      li x1, 0xcccc; \
+	  li x0, 0x0; \
+      li x17, 0x0; \
+      bne x0, x17, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S
new file mode 100644
index 0000000..8d166a4
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S
@@ -0,0 +1,261 @@
+# RISC-V Compliance Test I-DELAY_SLOTS-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing delay slots of jump and branch instructions.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test JAL\n");
+
+    # Address for test results
+    la      x1, test_A1_res
+
+    # Test
+    li      x2, 0x11111111
+    jal     x0, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x11111111)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test JALR\n");
+
+    # Address for test results
+    la      x1, test_A2_res
+
+    # Test
+    li      x2, 0x22222222
+    la      x4, 1f
+    jalr    x0, x4, 0
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x22222222)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B1 - test BEQ\n");
+
+    # Address for test results
+    la      x1, test_B1_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x33333333
+    beq     x5, x5, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x33333333)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B2 - test BNE\n");
+
+    # Address for test results
+    la      x1, test_B2_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x44444444
+    bne     x5, x6, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x44444444)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B3 - test BLT\n");
+
+    # Address for test results
+    la      x1, test_B3_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x55555555
+    blt     x5, x6, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x55555555)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B4 - test BLTU\n");
+
+    # Address for test results
+    la      x1, test_B4_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x66666666
+    bltu    x5, x6, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x66666666)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part B  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B5 - test BGE\n");
+
+    # Address for test results
+    la      x1, test_B5_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x77777777
+    bge     x6, x5, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x77777777)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part C  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B6 - test BGEU\n");
+
+    # Address for test results
+    la      x1, test_B6_res
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    li      x2, 0x88888888
+    bgeu    x6, x5, 1f
+    li      x2, 0
+1:
+
+    # Store results
+    sw      x2, 0(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x88888888)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part D  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 1, 4, -1
+test_A2_res:
+    .fill 1, 4, -1
+test_B1_res:
+    .fill 1, 4, -1
+test_B2_res:
+    .fill 1, 4, -1
+test_B3_res:
+    .fill 1, 4, -1
+test_B4_res:
+    .fill 1, 4, -1
+test_B5_res:
+    .fill 1, 4, -1
+test_B6_res:
+    .fill 1, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S
new file mode 100644
index 0000000..958eebc
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S
@@ -0,0 +1,118 @@
+# RISC-V Compliance Test I-EBREAK-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction EBREAK.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x30, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x30, "# Test Begin Reserved reg x31\n")
+
+    # Save and set trap handler address
+    la x1, _trap_handler
+    csrrw x31, mtvec, x1
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A - test EBREAK\n");
+
+    # Address for test results
+    la      x1, test_A_res_exc
+
+    # Test
+    li      x2, 0x11111111
+    ebreak
+    sw      x0, 0(x1)
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # restore mtvec and jump to the end
+    csrw mtvec, x31
+    jal x0, test_end
+
+    # ---------------------------------------------------------------------------------------------
+    # Exception handler
+_trap_handler:
+    # increment return address
+    csrr    x30, mepc
+    addi    x30, x30, 4
+    csrw    mepc, x30
+
+    # Store MCAUSE
+    csrr    x30, mcause
+    sw      x30, 0(x1)
+
+    # Store data from test
+    sw      x2, 4(x1)
+    sw      x0, 8(x1)
+
+    # increment data_exc address
+    addi    x1, x1, 12
+
+    # return
+    mret
+
+    # ---------------------------------------------------------------------------------------------
+
+test_end:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res_exc:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S
new file mode 100644
index 0000000..5278207
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S
@@ -0,0 +1,120 @@
+# RISC-V Compliance Test I-ECALL-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction ECALL.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x30, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x30, "# Test Begin Reserved reg x31\n")
+
+    # Save and set trap handler address
+    la x1, _trap_handler
+    csrrw x31, mtvec, x1
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A - test ECALL\n");
+
+    # Address for test results
+    la      x1, test_A_res_exc
+
+    # Test
+    li      x2, 0x11111111
+    ecall
+    sw      x0, 0(x1)
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # restore mtvec and jump to the end
+    csrw mtvec, x31
+    jal x0, test_end
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # Exception handler
+_trap_handler:
+    # increment return address
+    csrr    x30, mepc
+    addi    x30, x30, 4
+    csrw    mepc, x30
+
+    # Store MCAUSE
+    csrr    x30, mcause
+    sw      x30, 0(x1)
+
+    # Store data from test
+    sw      x2, 4(x1)
+    sw      x0, 8(x1)
+
+    # increment data_exc address
+    addi    x1, x1, 12
+
+    # return
+    mret
+
+    # ---------------------------------------------------------------------------------------------
+
+test_end:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res_exc:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S
new file mode 100644
index 0000000..ec0591d
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S
@@ -0,0 +1,110 @@
+# RISC-V Compliance Test I-ENDIANESS-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing ENDIANESS of RISC-V processor.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A - test loading word by LW, LH, LB\n");
+
+    # Addresses for test data and results
+    la      x16, test_A_data
+    la      x17, test_A_res
+
+    # Test
+    lw      x1, 0(x16)
+    lhu     x2, 0(x16)
+    lhu     x3, 2(x16)
+    lbu     x4, -1(x16)
+    lbu     x5, 0(x16)
+    lbu     x6, 1(x16)
+    lbu     x7, 2(x16)
+    lbu     x8, 3(x16)
+
+    # Store results
+    sw      x1, 0(x17)
+    sw      x2, 4(x17)
+    sw      x3, 8(x17)
+    sw      x4, 12(x17)
+    sw      x5, 16(x17)
+    sw      x6, 20(x17)
+    sw      x7, 24(x17)
+    sw      x8, 28(x17)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x1, 0x01234567)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x2, 0x00004567)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x3, 0x00000123)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x4, 0x00000089)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x5, 0x00000067)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x6, 0x00000045)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x7, 0x00000023)
+    RVTEST_IO_ASSERT_GPR_EQ(x17, x8, 0x00000001)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+    .word 0x89ABCDEF
+test_A_data:
+    .word 0x01234567
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A_res:
+    .fill 8, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-IO-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-IO-01.S
new file mode 100644
index 0000000..addd89a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-IO-01.S
@@ -0,0 +1,424 @@
+# RISC-V Compliance Test I-IO-01
+#
+# Additions Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction IO-S.
+
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");
+
+    # Addresses for test data and results
+    la      x1, test_A1_data
+    la      x2, test_A1_res
+
+    # Load testdata
+    lw      x3, 0(x1)
+
+    # Register initialization
+    li      x4, 0
+    li      x5, 1
+    li      x6, -1
+    li      x7, 0x7FFFFFFF
+    li      x8, 0x80000000
+
+    # Test
+    add     x4, x3, x4
+    add     x5, x3, x5
+    add     x6, x3, x6
+    add     x7, x3, x7
+    add     x8, x3, x8
+
+    # Store results
+    sw      x3, 0(x2)
+    sw      x4, 4(x2)
+    sw      x5, 8(x2)
+    sw      x6, 12(x2)
+    sw      x7, 16(x2)
+    sw      x8, 20(x2)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");
+
+    # Addresses for test data and results
+    la      x1, test_A2_data
+    la      x2, test_A2_res
+
+    # Load testdata
+    lw      x8, 0(x1)
+
+    # Register initialization
+    li      x9, 0
+    li      x10, 1
+    li      x11, -1
+    li      x12, 0x7FFFFFFF
+    li      x13, 0x80000000
+
+    # Test
+    add     x9, x8, x9
+    add     x10, x8, x10
+    add     x11, x8, x11
+    add     x12, x8, x12
+    add     x13, x8, x13
+
+    # Store results
+    sw      x8, 0(x2)
+    sw      x9, 4(x2)
+    sw      x10, 8(x2)
+    sw      x11, 12(x2)
+    sw      x12, 16(x2)
+    sw      x13, 20(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8,  0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x9,  0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000002)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001)
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");
+
+    # Addresses for test data and results
+    la      x1, test_A3_data
+    la      x2, test_A3_res
+
+    # Load testdata
+    lw      x13, 0(x1)
+
+    # Register initialization
+    li      x14, 0
+    li      x15, 1
+    li      x16, -1
+    li      x17, 0x7FFFFFFF
+    li      x18, 0x80000000
+
+    # Test
+    add     x14, x13, x14
+    add     x15, x13, x15
+    add     x16, x13, x16
+    add     x17, x13, x17
+    add     x18, x13, x18
+
+    # Store results
+    sw      x13, 0(x2)
+    sw      x14, 4(x2)
+    sw      x15, 8(x2)
+    sw      x16, 12(x2)
+    sw      x17, 16(x2)
+    sw      x18, 20(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x7FFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF)
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");
+
+    # Addresses for test data and results
+    la      x1, test_A4_data
+    la      x2, test_A4_res
+
+    # Load testdata
+    lw      x18, 0(x1)
+
+    # Register initialization
+    li      x19, 0
+    li      x20, 1
+    li      x21, -1
+    li      x22, 0x7FFFFFFF
+    li      x23, 0x80000000
+
+    # Test execution
+    add     x19, x18, x19
+    add     x20, x18, x20
+    add     x21, x18, x21
+    add     x22, x18, x22
+    add     x23, x18, x23
+
+    # Store results
+    sw      x18, 0(x2)
+    sw      x19, 4(x2)
+    sw      x20, 8(x2)
+    sw      x21, 12(x2)
+    sw      x22, 16(x2)
+    sw      x23, 20(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0xFFFFFFFE)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF)
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");
+
+    # Addresses for test data and results
+    la      x1, test_A5_data
+    la      x2, test_A5_res
+
+    # Load testdata
+    lw      x23, 0(x1)
+
+    # Register initialization
+    li      x24, 0
+    li      x25, 1
+    li      x26, -1
+    li      x27, 0x7FFFFFFF
+    li      x28, 0x80000000
+
+    # Test
+    add     x24, x23, x24
+    add     x25, x23, x25
+    add     x26, x23, x26
+    add     x27, x23, x27
+    add     x28, x23, x28
+
+    # Store results
+    sw      x23, 0(x2)
+    sw      x24, 4(x2)
+    sw      x25, 8(x2)
+    sw      x26, 12(x2)
+    sw      x27, 16(x2)
+    sw      x28, 20(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x80000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n");
+
+    # Addresses for test data and results
+    la      x25, test_B_data
+    la      x26, test_B_res
+
+    # Load testdata
+    lw      x28, 0(x25)
+
+    # Register initialization
+    li      x27, 0x1
+
+    # Test
+    add     x29, x28, x27
+    add     x30, x29, x27
+    add     x31, x30, x27
+    add     x1, x31, x27
+    add     x2, x1, x27
+    add     x3, x2, x27
+
+    # store results
+    sw      x27, 0(x26)
+    sw      x28, 4(x26)
+    sw      x29, 8(x26)
+    sw      x30, 12(x26)
+    sw      x31, 16(x26)
+    sw      x1, 20(x26)
+    sw      x2, 24(x26)
+    sw      x3, 28(x26)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x27, 0x00000001)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0x0000ABCD)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000ABCE)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000ABCF)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000ABD0)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x1,  0x0000ABD1)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x2,  0x0000ABD2)
+    RVTEST_IO_ASSERT_GPR_EQ(x26, x3,  0x0000ABD3)
+    RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n");
+
+    # Addresses for test data and results
+    la      x1, test_C_data
+    la      x2, test_C_res
+
+    # Load testdata
+    lw      x28, 0(x1)
+
+    # Register initialization
+    li      x27, 0xF7FF8818
+
+    # Test
+    add     x0, x28, x27
+
+    # store results
+    sw      x0, 0(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x0,  0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n");
+
+    # Addresses for test data and results
+    la      x1, test_D_data
+    la      x2, test_D_res
+
+    # Load testdata
+    lw      x28, 0(x1)
+
+    # Register initialization
+    li      x27, 0xF7FF8818
+
+    # Test
+    add     x0, x28, x27
+    add     x5, x0, x0
+
+    # store results
+    sw      x0, 0(x2)
+    sw      x5, 4(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x0,  0x00000000)
+  //RVTEST_IO_ASSERT_GPR_EQ(x2, x5,  0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (add with x0)\n");
+
+    # Addresses for test data and results
+    la      x1, test_E_data
+    la      x2, test_E_res
+
+    # Load testdata
+    lw      x3, 0(x1)
+
+    # Test
+    add     x4, x3, x0
+    add     x5, x4, x0
+    add     x6, x0, x5
+    add     x14, x6, x0
+    add     x15, x14, x0
+    add     x16, x15, x0
+    add     x25, x0, x16
+    add     x26, x0, x25
+    add     x27, x26, x0
+
+    # Store results
+    sw      x4, 0(x2)
+    sw      x26, 4(x2)
+    sw      x27, 8(x2)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x4,  0x36925814)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814)
+    RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+    # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+
+test_A1_data:
+    .word 0
+test_A2_data:
+    .word 1
+test_A3_data:
+    .word -1
+test_A4_data:
+    .word 0x7FFFFFFF
+test_A5_data:
+    .word 0x80000000
+test_B_data:
+    .word 0x0000ABCD
+test_C_data:
+    .word 0x12345678
+test_D_data:
+    .word 0xFEDCBA98
+test_E_data:
+    .word 0x36925814
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_A1_res:
+    .fill 6, 4, -1
+test_A2_res:
+    .fill 6, 4, -1
+test_A3_res:
+    .fill 6, 4, -1
+test_A4_res:
+    .fill 6, 4, -1
+test_A5_res:
+    .fill 6, 4, -1
+test_B_res:
+    .fill 8, 4, -1
+test_C_res:
+    .fill 1, 4, -1
+test_D_res:
+    .fill 2, 4, -1
+test_E_res:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S
new file mode 100644
index 0000000..79922b6
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S
@@ -0,0 +1,432 @@
+# RISC-V Compliance Test JAL-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'JAL'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x6, x0, 0, x5, 0, \
+      li x0, 0xcccc; \
+      jal x31, 1f; \
+      li x0, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x6, x1, 0xcccc, x5, 4, \
+      li x1, 0xcccc; \
+      jal x30, 2f; \
+      li x1, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x6, x2, 0xcccc, x5, 8, \
+      li x2, 0xcccc; \
+      jal x29, 2b; \
+      li x2, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x6, x3, 0xcccc, x5, 12, \
+      li x3, 0xcccc; \
+      jal x28, 4f; \
+      li x3, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x6, x4, 0xcccc, x5, 16, \
+      li x4, 0xcccc; \
+      jal x27, 5f; \
+      li x4, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x2, x5, 0xcccc, x1, 0, \
+      li x5, 0xcccc; \
+      jal x26, 1f; \
+      li x5, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x2, x6, 0xcccc, x1, 4, \
+      li x6, 0xcccc; \
+      jal x25, 2f; \
+      li x6, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x2, x7, 0xcccc, x1, 8, \
+      li x7, 0xcccc; \
+      jal x24, 2b; \
+      li x7, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x2, x8, 0xcccc, x1, 12, \
+      li x8, 0xcccc; \
+      jal x23, 4f; \
+      li x8, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x2, x9, 0xcccc, x1, 16, \
+      li x9, 0xcccc; \
+      jal x22, 5f; \
+      li x9, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x7, x10, 0xcccc, x1, 0, \
+      li x10, 0xcccc; \
+      jal x21, 1f; \
+      li x10, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x7, x11, 0xcccc, x1, 4, \
+      li x11, 0xcccc; \
+      jal x20, 2f; \
+      li x11, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x7, x12, 0xcccc, x1, 8, \
+      li x12, 0xcccc; \
+      jal x19, 2b; \
+      li x12, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x7, x13, 0xcccc, x1, 12, \
+      li x13, 0xcccc; \
+      jal x18, 4f; \
+      li x13, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x7, x14, 0xcccc, x1, 16, \
+      li x14, 0xcccc; \
+      jal x17, 5f; \
+      li x14, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x15, 0xcccc, x2, 0, \
+      li x15, 0xcccc; \
+      jal x16, 1f; \
+      li x15, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x16, 0xcccc, x2, 4, \
+      li x16, 0xcccc; \
+      jal x15, 2f; \
+      li x16, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x17, 0xcccc, x2, 8, \
+      li x17, 0xcccc; \
+      jal x14, 2b; \
+      li x17, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x3, x18, 0xcccc, x2, 12, \
+      li x18, 0xcccc; \
+      jal x13, 4f; \
+      li x18, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x19, 0xcccc, x2, 16, \
+      li x19, 0xcccc; \
+      jal x12, 5f; \
+      li x19, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x2, x20, 0xcccc, x1, 0, \
+      li x20, 0xcccc; \
+      jal x11, 1f; \
+      li x20, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x2, x21, 0xcccc, x1, 4, \
+      li x21, 0xcccc; \
+      jal x10, 2f; \
+      li x21, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x2, x22, 0xcccc, x1, 8, \
+      li x22, 0xcccc; \
+      jal x9, 2b; \
+      li x22, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x2, x23, 0xcccc, x1, 12, \
+      li x23, 0xcccc; \
+      jal x8, 4f; \
+      li x23, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x2, x24, 0xcccc, x1, 16, \
+      li x24, 0xcccc; \
+      jal x7, 5f; \
+      li x24, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x7, x25, 0xcccc, x1, 0, \
+      li x25, 0xcccc; \
+      jal x6, 1f; \
+      li x25, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x7, x26, 0xcccc, x1, 4, \
+      li x26, 0xcccc; \
+      jal x5, 2f; \
+      li x26, 0x123ab; \
+2: \
+    )
+ 
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x7, x27, 0xcccc, x1, 8, \
+      li x27, 0xcccc; \
+      jal x4, 2b; \
+      li x27, 0x123ab; \
+4: \
+    )
+
+ 
+    // Result = 0
+    TEST_CASE(x7, x28, 0xcccc, x1, 12, \
+      li x28, 0xcccc; \
+      jal x3, 4f; \
+      li x28, 0x123ab; \
+4: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x7, x29, 0xcccc, x1, 16, \
+      li x29, 0xcccc; \
+      jal x2, 5f; \
+      li x29, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+    
+ 
+    // Result = 0
+    TEST_CASE(x3, x30, 0xcccc, x2, 0, \
+      li x30, 0xcccc; \
+      jal x1, 1f; \
+      li x30, 0x123ab; \
+1: \
+    )
+ 
+    // Result = 0
+    TEST_CASE(x3, x31, 0xcccc, x2, 4, \
+      li x31, 0xcccc; \
+      jal x0, 2f; \
+      li x31, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S
new file mode 100644
index 0000000..5fcff87
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S
@@ -0,0 +1,464 @@
+# RISC-V Compliance Test JALR-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'JALR'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+    
+  
+    // Result = 0
+    TEST_CASE(x6, x31, 0xcccc, x5, 0, \
+      li x31, 0xcccc; \
+      la x16, 1f - 0; \
+      jalr x0, x16,  0; \
+      li x31, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x6, x30, 0xcccc, x5, 4, \
+      li x30, 0xcccc; \
+      la x15, 2f - 1; \
+      jalr x1, x15,  1; \
+      li x30, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x6, x29, 0xcccc, x5, 8, \
+      li x29, 0xcccc; \
+      la x14, 2b - 1; \
+      jalr x2, x14,  1; \
+      li x29, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x6, x28, 0xcccc, x5, 12, \
+      li x28, 0xcccc; \
+      la x13, 4f - 4; \
+      jalr x3, x13,  4; \
+      li x28, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x6, x27, 0xcccc, x5, 16, \
+      li x27, 0xcccc; \
+      la x12, 5f - 2; \
+      jalr x4, x12,  2; \
+      li x27, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+    
+  
+    // Result = 0
+    TEST_CASE(x2, x26, 0xcccc, x1, 0, \
+      li x26, 0xcccc; \
+      la x11, 1f - 4; \
+      jalr x5, x11,  4; \
+      li x26, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x2, x25, 0xcccc, x1, 4, \
+      li x25, 0xcccc; \
+      la x10, 2f - 3; \
+      jalr x6, x10,  3; \
+      li x25, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x2, x24, 0xcccc, x1, 8, \
+      li x24, 0xcccc; \
+      la x9, 2b - 2; \
+      jalr x7, x9,  2; \
+      li x24, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x2, x23, 0xcccc, x1, 12, \
+      li x23, 0xcccc; \
+      la x8, 4f - 0; \
+      jalr x8, x8,  0; \
+      li x23, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x2, x22, 0xcccc, x1, 16, \
+      li x22, 0xcccc; \
+      la x7, 5f - 1; \
+      jalr x9, x7,  1; \
+      li x22, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+    
+  
+    // Result = 0
+    TEST_CASE(x7, x21, 0xcccc, x1, 0, \
+      li x21, 0xcccc; \
+      la x6, 1f - 1; \
+      jalr x10, x6,  1; \
+      li x21, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x7, x20, 0xcccc, x1, 4, \
+      li x20, 0xcccc; \
+      la x5, 2f - 4; \
+      jalr x11, x5,  4; \
+      li x20, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x7, x19, 0xcccc, x1, 8, \
+      li x19, 0xcccc; \
+      la x4, 2b - 2; \
+      jalr x12, x4,  2; \
+      li x19, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x7, x18, 0xcccc, x1, 12, \
+      li x18, 0xcccc; \
+      la x3, 4f - 4; \
+      jalr x13, x3,  4; \
+      li x18, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x7, x17, 0xcccc, x1, 16, \
+      li x17, 0xcccc; \
+      la x2, 5f - 3; \
+      jalr x14, x2,  3; \
+      li x17, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+    
+  
+    // Result = 0
+    TEST_CASE(x3, x16, 0xcccc, x2, 0, \
+      li x16, 0xcccc; \
+      la x1, 1f - 2; \
+      jalr x15, x1,  2; \
+      li x16, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x3, x15, 0xcccc, x2, 4, \
+      li x15, 0xcccc; \
+      la x1, 2f - 0; \
+      jalr x16, x1,  0; \
+      li x15, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x3, x14, 0xcccc, x2, 8, \
+      li x14, 0xcccc; \
+      la x31, 2b - 1; \
+      jalr x17, x31,  1; \
+      li x14, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x3, x13, 0xcccc, x2, 12, \
+      li x13, 0xcccc; \
+      la x30, 4f - 1; \
+      jalr x18, x30,  1; \
+      li x13, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x3, x12, 0xcccc, x2, 16, \
+      li x12, 0xcccc; \
+      la x29, 5f - 4; \
+      jalr x19, x29,  4; \
+      li x12, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+    
+  
+    // Result = 0
+    TEST_CASE(x2, x11, 0xcccc, x1, 0, \
+      li x11, 0xcccc; \
+      la x28, 1f - 2; \
+      jalr x20, x28,  2; \
+      li x11, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x2, x10, 0xcccc, x1, 4, \
+      li x10, 0xcccc; \
+      la x27, 2f - 4; \
+      jalr x21, x27,  4; \
+      li x10, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x2, x9, 0xcccc, x1, 8, \
+      li x9, 0xcccc; \
+      la x26, 2b - 3; \
+      jalr x22, x26,  3; \
+      li x9, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x2, x8, 0xcccc, x1, 12, \
+      li x8, 0xcccc; \
+      la x25, 4f - 2; \
+      jalr x23, x25,  2; \
+      li x8, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x2, x7, 0xcccc, x1, 16, \
+      li x7, 0xcccc; \
+      la x24, 5f - 0; \
+      jalr x24, x24,  0; \
+      li x7, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+    
+  
+    // Result = 0
+    TEST_CASE(x7, x6, 0xcccc, x1, 0, \
+      li x6, 0xcccc; \
+      la x23, 1f - 1; \
+      jalr x25, x23,  1; \
+      li x6, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x7, x5, 0xcccc, x1, 4, \
+      li x5, 0xcccc; \
+      la x22, 2f - 1; \
+      jalr x26, x22,  1; \
+      li x5, 0x123ab; \
+2: \
+    )
+  
+
+    jal x0, 3f
+2:
+    jal x0, 4f
+3:
+    // Result = 0
+    TEST_CASE(x7, x4, 0xcccc, x1, 8, \
+      li x4, 0xcccc; \
+      la x21, 2b - 4; \
+      jalr x27, x21,  4; \
+      li x4, 0x123ab; \
+4: \
+    )
+
+  
+    // Result = 0
+    TEST_CASE(x7, x3, 0xcccc, x1, 12, \
+      li x3, 0xcccc; \
+      la x20, 4f - 2; \
+      jalr x28, x20,  2; \
+      li x3, 0x123ab; \
+4: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x7, x2, 0xcccc, x1, 16, \
+      li x2, 0xcccc; \
+      la x19, 5f - 4; \
+      jalr x29, x19,  4; \
+      li x2, 0x123ab; \
+5: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+    
+  
+    // Result = 0
+    TEST_CASE(x3, x1, 0xcccc, x2, 0, \
+      li x1, 0xcccc; \
+      la x18, 1f - 3; \
+      jalr x30, x18,  3; \
+      li x1, 0x123ab; \
+1: \
+    )
+  
+    // Result = 0
+    TEST_CASE(x3, x0, 0, x2, 4, \
+      li x0, 0xcccc; \
+      la x17, 2f - 2; \
+      jalr x31, x17,  2; \
+      li x0, 0x123ab; \
+2: \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S
new file mode 100644
index 0000000..646c7c0
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S
@@ -0,0 +1,284 @@
+# RISC-V Compliance Test LB-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LB'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test data and results
+	la	x5, test_1_res
+
+	TEST_CASE(x7, x0, 0x0, x5, 0, \
+    la  x31, test_data; \
+    lb x0, 0x0(x31); \
+    )
+	TEST_CASE(x7, x1, 0xffffffbb, x5, 4, \
+    la  x30, test_data; \
+    lb x1, -0x2(x30); \
+    )
+	TEST_CASE(x7, x2, 0xffffffdd, x5, 8, \
+    la  x29, test_data; \
+    lb x2, 0x3(x29); \
+    )
+	TEST_CASE(x7, x3, 0xc, x5, 12, \
+    la  x28, test_data; \
+    lb x3, -0x4(x28); \
+    )
+	TEST_CASE(x7, x4, 0xd, x5, 16, \
+    la  x27, test_data; \
+    lb x4, 0x2(x27); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_2_res
+
+	TEST_CASE(x3, x5, 0xfffffff0, x1, 0, \
+    la  x26, test_data; \
+    lb x5, 0x4(x26); \
+    )
+	TEST_CASE(x3, x6, 0xb, x1, 4, \
+    la  x25, test_data; \
+    lb x6, -0x1(x25); \
+    )
+	TEST_CASE(x3, x7, 0xe, x1, 8, \
+    la  x24, test_data; \
+    lb x7, 0x1(x24); \
+    )
+	TEST_CASE(x3, x8, 0xffffffee, x1, 12, \
+    la  x23, test_data; \
+    lb x8, 0x0(x23); \
+    )
+	TEST_CASE(x3, x9, 0xffffffbb, x1, 16, \
+    la  x22, test_data; \
+    lb x9, -0x2(x22); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_3_res
+
+	TEST_CASE(x8, x10, 0xffffffdd, x1, 0, \
+    la  x21, test_data; \
+    lb x10, 0x3(x21); \
+    )
+	TEST_CASE(x8, x11, 0xc, x1, 4, \
+    la  x20, test_data; \
+    lb x11, -0x4(x20); \
+    )
+	TEST_CASE(x8, x12, 0xd, x1, 8, \
+    la  x19, test_data; \
+    lb x12, 0x2(x19); \
+    )
+	TEST_CASE(x8, x13, 0xfffffff0, x1, 12, \
+    la  x18, test_data; \
+    lb x13, 0x4(x18); \
+    )
+	TEST_CASE(x8, x14, 0xb, x1, 16, \
+    la  x17, test_data; \
+    lb x14, -0x1(x17); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_4_res
+
+	TEST_CASE(x4, x15, 0xe, x2, 0, \
+    la  x16, test_data; \
+    lb x15, 0x1(x16); \
+    )
+	TEST_CASE(x4, x16, 0xffffffee, x2, 4, \
+    la  x15, test_data; \
+    lb x16, 0x0(x15); \
+    )
+	TEST_CASE(x4, x17, 0xffffffbb, x2, 8, \
+    la  x14, test_data; \
+    lb x17, -0x2(x14); \
+    )
+	TEST_CASE(x4, x18, 0xffffffdd, x2, 12, \
+    la  x13, test_data; \
+    lb x18, 0x3(x13); \
+    )
+	TEST_CASE(x4, x19, 0xc, x2, 16, \
+    la  x12, test_data; \
+    lb x19, -0x4(x12); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_5_res
+
+	TEST_CASE(x3, x20, 0xd, x1, 0, \
+    la  x11, test_data; \
+    lb x20, 0x2(x11); \
+    )
+	TEST_CASE(x3, x21, 0xfffffff0, x1, 4, \
+    la  x10, test_data; \
+    lb x21, 0x4(x10); \
+    )
+	TEST_CASE(x3, x22, 0xb, x1, 8, \
+    la  x9, test_data; \
+    lb x22, -0x1(x9); \
+    )
+	TEST_CASE(x3, x23, 0xe, x1, 12, \
+    la  x8, test_data; \
+    lb x23, 0x1(x8); \
+    )
+	TEST_CASE(x3, x24, 0xffffffee, x1, 16, \
+    la  x7, test_data; \
+    lb x24, 0x0(x7); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_6_res
+
+	TEST_CASE(x8, x25, 0xffffffbb, x1, 0, \
+    la  x6, test_data; \
+    lb x25, -0x2(x6); \
+    )
+	TEST_CASE(x8, x26, 0xffffffdd, x1, 4, \
+    la  x5, test_data; \
+    lb x26, 0x3(x5); \
+    )
+	TEST_CASE(x8, x27, 0xc, x1, 8, \
+    la  x4, test_data; \
+    lb x27, -0x4(x4); \
+    )
+	TEST_CASE(x8, x28, 0xd, x1, 12, \
+    la  x3, test_data; \
+    lb x28, 0x2(x3); \
+    )
+	TEST_CASE(x8, x29, 0xfffffff0, x1, 16, \
+    la  x2, test_data; \
+    lb x29, 0x4(x2); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_7_res
+
+	TEST_CASE(x4, x30, 0xb, x2, 0, \
+    la  x1, test_data; \
+    lb x30, -0x1(x1); \
+    )
+	TEST_CASE(x4, x31, 0xe, x2, 4, \
+    la  x1, test_data; \
+    lb x31, 0x1(x1); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+	.align 4
+test_data_start:
+
+	.word 0x11f1f222
+	.word 0xf33344f4
+	.word 0x55f5f666
+	.word 0xf77788f8
+	.word 0x99090aaa
+	.word 0xbbbcc0c
+test_data:
+	.word 0xdd0d0eee
+	.word 0xfff00f0
+	.word 0x12345678
+	.word 0x9abcdef0
+	.word 0x76543210
+	.word 0xfedcba98
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S
new file mode 100644
index 0000000..40aa90b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S
@@ -0,0 +1,284 @@
+# RISC-V Compliance Test LBU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LBU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test data and results
+	la	x5, test_1_res
+
+	TEST_CASE(x7, x0, 0x0, x5, 0, \
+    la  x31, test_data; \
+    lbu x0, 0x0(x31); \
+    )
+	TEST_CASE(x7, x1, 0xbb, x5, 4, \
+    la  x30, test_data; \
+    lbu x1, -0x2(x30); \
+    )
+	TEST_CASE(x7, x2, 0xdd, x5, 8, \
+    la  x29, test_data; \
+    lbu x2, 0x3(x29); \
+    )
+	TEST_CASE(x7, x3, 0xc, x5, 12, \
+    la  x28, test_data; \
+    lbu x3, -0x4(x28); \
+    )
+	TEST_CASE(x7, x4, 0xd, x5, 16, \
+    la  x27, test_data; \
+    lbu x4, 0x2(x27); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_2_res
+
+	TEST_CASE(x3, x5, 0xf0, x1, 0, \
+    la  x26, test_data; \
+    lbu x5, 0x4(x26); \
+    )
+	TEST_CASE(x3, x6, 0xb, x1, 4, \
+    la  x25, test_data; \
+    lbu x6, -0x1(x25); \
+    )
+	TEST_CASE(x3, x7, 0xe, x1, 8, \
+    la  x24, test_data; \
+    lbu x7, 0x1(x24); \
+    )
+	TEST_CASE(x3, x8, 0xee, x1, 12, \
+    la  x23, test_data; \
+    lbu x8, 0x0(x23); \
+    )
+	TEST_CASE(x3, x9, 0xbb, x1, 16, \
+    la  x22, test_data; \
+    lbu x9, -0x2(x22); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_3_res
+
+	TEST_CASE(x8, x10, 0xdd, x1, 0, \
+    la  x21, test_data; \
+    lbu x10, 0x3(x21); \
+    )
+	TEST_CASE(x8, x11, 0xc, x1, 4, \
+    la  x20, test_data; \
+    lbu x11, -0x4(x20); \
+    )
+	TEST_CASE(x8, x12, 0xd, x1, 8, \
+    la  x19, test_data; \
+    lbu x12, 0x2(x19); \
+    )
+	TEST_CASE(x8, x13, 0xf0, x1, 12, \
+    la  x18, test_data; \
+    lbu x13, 0x4(x18); \
+    )
+	TEST_CASE(x8, x14, 0xb, x1, 16, \
+    la  x17, test_data; \
+    lbu x14, -0x1(x17); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_4_res
+
+	TEST_CASE(x4, x15, 0xe, x2, 0, \
+    la  x16, test_data; \
+    lbu x15, 0x1(x16); \
+    )
+	TEST_CASE(x4, x16, 0xee, x2, 4, \
+    la  x15, test_data; \
+    lbu x16, 0x0(x15); \
+    )
+	TEST_CASE(x4, x17, 0xbb, x2, 8, \
+    la  x14, test_data; \
+    lbu x17, -0x2(x14); \
+    )
+	TEST_CASE(x4, x18, 0xdd, x2, 12, \
+    la  x13, test_data; \
+    lbu x18, 0x3(x13); \
+    )
+	TEST_CASE(x4, x19, 0xc, x2, 16, \
+    la  x12, test_data; \
+    lbu x19, -0x4(x12); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_5_res
+
+	TEST_CASE(x3, x20, 0xd, x1, 0, \
+    la  x11, test_data; \
+    lbu x20, 0x2(x11); \
+    )
+	TEST_CASE(x3, x21, 0xf0, x1, 4, \
+    la  x10, test_data; \
+    lbu x21, 0x4(x10); \
+    )
+	TEST_CASE(x3, x22, 0xb, x1, 8, \
+    la  x9, test_data; \
+    lbu x22, -0x1(x9); \
+    )
+	TEST_CASE(x3, x23, 0xe, x1, 12, \
+    la  x8, test_data; \
+    lbu x23, 0x1(x8); \
+    )
+	TEST_CASE(x3, x24, 0xee, x1, 16, \
+    la  x7, test_data; \
+    lbu x24, 0x0(x7); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_6_res
+
+	TEST_CASE(x8, x25, 0xbb, x1, 0, \
+    la  x6, test_data; \
+    lbu x25, -0x2(x6); \
+    )
+	TEST_CASE(x8, x26, 0xdd, x1, 4, \
+    la  x5, test_data; \
+    lbu x26, 0x3(x5); \
+    )
+	TEST_CASE(x8, x27, 0xc, x1, 8, \
+    la  x4, test_data; \
+    lbu x27, -0x4(x4); \
+    )
+	TEST_CASE(x8, x28, 0xd, x1, 12, \
+    la  x3, test_data; \
+    lbu x28, 0x2(x3); \
+    )
+	TEST_CASE(x8, x29, 0xf0, x1, 16, \
+    la  x2, test_data; \
+    lbu x29, 0x4(x2); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_7_res
+
+	TEST_CASE(x4, x30, 0xb, x2, 0, \
+    la  x1, test_data; \
+    lbu x30, -0x1(x1); \
+    )
+	TEST_CASE(x4, x31, 0xe, x2, 4, \
+    la  x1, test_data; \
+    lbu x31, 0x1(x1); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+	.align 4
+test_data_start:
+
+	.word 0x11f1f222
+	.word 0xf33344f4
+	.word 0x55f5f666
+	.word 0xf77788f8
+	.word 0x99090aaa
+	.word 0xbbbcc0c
+test_data:
+	.word 0xdd0d0eee
+	.word 0xfff00f0
+	.word 0x12345678
+	.word 0x9abcdef0
+	.word 0x76543210
+	.word 0xfedcba98
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S
new file mode 100644
index 0000000..caa25cf
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S
@@ -0,0 +1,284 @@
+# RISC-V Compliance Test LH-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LH'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test data and results
+	la	x5, test_1_res
+
+	TEST_CASE(x7, x0, 0x0, x5, 0, \
+    la  x31, test_data; \
+    lh x0, 0x0(x31); \
+    )
+	TEST_CASE(x7, x1, 0xbbb, x5, 4, \
+    la  x30, test_data; \
+    lh x1, -0x2(x30); \
+    )
+	TEST_CASE(x7, x2, 0xffffdd0d, x5, 8, \
+    la  x29, test_data; \
+    lh x2, 0x2(x29); \
+    )
+	TEST_CASE(x7, x3, 0xffffcc0c, x5, 12, \
+    la  x28, test_data; \
+    lh x3, -0x4(x28); \
+    )
+	TEST_CASE(x7, x4, 0xffffdd0d, x5, 16, \
+    la  x27, test_data; \
+    lh x4, 0x2(x27); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_2_res
+
+	TEST_CASE(x3, x5, 0xf0, x1, 0, \
+    la  x26, test_data; \
+    lh x5, 0x4(x26); \
+    )
+	TEST_CASE(x3, x6, 0xeee, x1, 4, \
+    la  x25, test_data; \
+    lh x6, 0x0(x25); \
+    )
+	TEST_CASE(x3, x7, 0xeee, x1, 8, \
+    la  x24, test_data; \
+    lh x7, 0x0(x24); \
+    )
+	TEST_CASE(x3, x8, 0xeee, x1, 12, \
+    la  x23, test_data; \
+    lh x8, 0x0(x23); \
+    )
+	TEST_CASE(x3, x9, 0xbbb, x1, 16, \
+    la  x22, test_data; \
+    lh x9, -0x2(x22); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_3_res
+
+	TEST_CASE(x8, x10, 0xffffdd0d, x1, 0, \
+    la  x21, test_data; \
+    lh x10, 0x2(x21); \
+    )
+	TEST_CASE(x8, x11, 0xffffcc0c, x1, 4, \
+    la  x20, test_data; \
+    lh x11, -0x4(x20); \
+    )
+	TEST_CASE(x8, x12, 0xffffdd0d, x1, 8, \
+    la  x19, test_data; \
+    lh x12, 0x2(x19); \
+    )
+	TEST_CASE(x8, x13, 0xf0, x1, 12, \
+    la  x18, test_data; \
+    lh x13, 0x4(x18); \
+    )
+	TEST_CASE(x8, x14, 0xeee, x1, 16, \
+    la  x17, test_data; \
+    lh x14, 0x0(x17); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_4_res
+
+	TEST_CASE(x4, x15, 0xeee, x2, 0, \
+    la  x16, test_data; \
+    lh x15, 0x0(x16); \
+    )
+	TEST_CASE(x4, x16, 0xeee, x2, 4, \
+    la  x15, test_data; \
+    lh x16, 0x0(x15); \
+    )
+	TEST_CASE(x4, x17, 0xbbb, x2, 8, \
+    la  x14, test_data; \
+    lh x17, -0x2(x14); \
+    )
+	TEST_CASE(x4, x18, 0xffffdd0d, x2, 12, \
+    la  x13, test_data; \
+    lh x18, 0x2(x13); \
+    )
+	TEST_CASE(x4, x19, 0xffffcc0c, x2, 16, \
+    la  x12, test_data; \
+    lh x19, -0x4(x12); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_5_res
+
+	TEST_CASE(x3, x20, 0xffffdd0d, x1, 0, \
+    la  x11, test_data; \
+    lh x20, 0x2(x11); \
+    )
+	TEST_CASE(x3, x21, 0xf0, x1, 4, \
+    la  x10, test_data; \
+    lh x21, 0x4(x10); \
+    )
+	TEST_CASE(x3, x22, 0xeee, x1, 8, \
+    la  x9, test_data; \
+    lh x22, 0x0(x9); \
+    )
+	TEST_CASE(x3, x23, 0xeee, x1, 12, \
+    la  x8, test_data; \
+    lh x23, 0x0(x8); \
+    )
+	TEST_CASE(x3, x24, 0xeee, x1, 16, \
+    la  x7, test_data; \
+    lh x24, 0x0(x7); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_6_res
+
+	TEST_CASE(x8, x25, 0xbbb, x1, 0, \
+    la  x6, test_data; \
+    lh x25, -0x2(x6); \
+    )
+	TEST_CASE(x8, x26, 0xffffdd0d, x1, 4, \
+    la  x5, test_data; \
+    lh x26, 0x2(x5); \
+    )
+	TEST_CASE(x8, x27, 0xffffcc0c, x1, 8, \
+    la  x4, test_data; \
+    lh x27, -0x4(x4); \
+    )
+	TEST_CASE(x8, x28, 0xffffdd0d, x1, 12, \
+    la  x3, test_data; \
+    lh x28, 0x2(x3); \
+    )
+	TEST_CASE(x8, x29, 0xf0, x1, 16, \
+    la  x2, test_data; \
+    lh x29, 0x4(x2); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_7_res
+
+	TEST_CASE(x4, x30, 0xeee, x2, 0, \
+    la  x1, test_data; \
+    lh x30, 0x0(x1); \
+    )
+	TEST_CASE(x4, x31, 0xeee, x2, 4, \
+    la  x1, test_data; \
+    lh x31, 0x0(x1); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+	.align 4
+test_data_start:
+
+	.word 0x11f1f222
+	.word 0xf33344f4
+	.word 0x55f5f666
+	.word 0xf77788f8
+	.word 0x99090aaa
+	.word 0xbbbcc0c
+test_data:
+	.word 0xdd0d0eee
+	.word 0xfff00f0
+	.word 0x12345678
+	.word 0x9abcdef0
+	.word 0x76543210
+	.word 0xfedcba98
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S
new file mode 100644
index 0000000..4abffc7
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S
@@ -0,0 +1,284 @@
+# RISC-V Compliance Test LHU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LHU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test data and results
+	la	x5, test_1_res
+
+	TEST_CASE(x7, x0, 0x0, x5, 0, \
+    la  x31, test_data; \
+    lhu x0, 0x0(x31); \
+    )
+	TEST_CASE(x7, x1, 0xbbb, x5, 4, \
+    la  x30, test_data; \
+    lhu x1, -0x2(x30); \
+    )
+	TEST_CASE(x7, x2, 0xdd0d, x5, 8, \
+    la  x29, test_data; \
+    lhu x2, 0x2(x29); \
+    )
+	TEST_CASE(x7, x3, 0xcc0c, x5, 12, \
+    la  x28, test_data; \
+    lhu x3, -0x4(x28); \
+    )
+	TEST_CASE(x7, x4, 0xdd0d, x5, 16, \
+    la  x27, test_data; \
+    lhu x4, 0x2(x27); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_2_res
+
+	TEST_CASE(x3, x5, 0xf0, x1, 0, \
+    la  x26, test_data; \
+    lhu x5, 0x4(x26); \
+    )
+	TEST_CASE(x3, x6, 0xeee, x1, 4, \
+    la  x25, test_data; \
+    lhu x6, 0x0(x25); \
+    )
+	TEST_CASE(x3, x7, 0xeee, x1, 8, \
+    la  x24, test_data; \
+    lhu x7, 0x0(x24); \
+    )
+	TEST_CASE(x3, x8, 0xeee, x1, 12, \
+    la  x23, test_data; \
+    lhu x8, 0x0(x23); \
+    )
+	TEST_CASE(x3, x9, 0xbbb, x1, 16, \
+    la  x22, test_data; \
+    lhu x9, -0x2(x22); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_3_res
+
+	TEST_CASE(x8, x10, 0xdd0d, x1, 0, \
+    la  x21, test_data; \
+    lhu x10, 0x2(x21); \
+    )
+	TEST_CASE(x8, x11, 0xcc0c, x1, 4, \
+    la  x20, test_data; \
+    lhu x11, -0x4(x20); \
+    )
+	TEST_CASE(x8, x12, 0xdd0d, x1, 8, \
+    la  x19, test_data; \
+    lhu x12, 0x2(x19); \
+    )
+	TEST_CASE(x8, x13, 0xf0, x1, 12, \
+    la  x18, test_data; \
+    lhu x13, 0x4(x18); \
+    )
+	TEST_CASE(x8, x14, 0xeee, x1, 16, \
+    la  x17, test_data; \
+    lhu x14, 0x0(x17); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_4_res
+
+	TEST_CASE(x4, x15, 0xeee, x2, 0, \
+    la  x16, test_data; \
+    lhu x15, 0x0(x16); \
+    )
+	TEST_CASE(x4, x16, 0xeee, x2, 4, \
+    la  x15, test_data; \
+    lhu x16, 0x0(x15); \
+    )
+	TEST_CASE(x4, x17, 0xbbb, x2, 8, \
+    la  x14, test_data; \
+    lhu x17, -0x2(x14); \
+    )
+	TEST_CASE(x4, x18, 0xdd0d, x2, 12, \
+    la  x13, test_data; \
+    lhu x18, 0x2(x13); \
+    )
+	TEST_CASE(x4, x19, 0xcc0c, x2, 16, \
+    la  x12, test_data; \
+    lhu x19, -0x4(x12); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_5_res
+
+	TEST_CASE(x3, x20, 0xdd0d, x1, 0, \
+    la  x11, test_data; \
+    lhu x20, 0x2(x11); \
+    )
+	TEST_CASE(x3, x21, 0xf0, x1, 4, \
+    la  x10, test_data; \
+    lhu x21, 0x4(x10); \
+    )
+	TEST_CASE(x3, x22, 0xeee, x1, 8, \
+    la  x9, test_data; \
+    lhu x22, 0x0(x9); \
+    )
+	TEST_CASE(x3, x23, 0xeee, x1, 12, \
+    la  x8, test_data; \
+    lhu x23, 0x0(x8); \
+    )
+	TEST_CASE(x3, x24, 0xeee, x1, 16, \
+    la  x7, test_data; \
+    lhu x24, 0x0(x7); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_6_res
+
+	TEST_CASE(x8, x25, 0xbbb, x1, 0, \
+    la  x6, test_data; \
+    lhu x25, -0x2(x6); \
+    )
+	TEST_CASE(x8, x26, 0xdd0d, x1, 4, \
+    la  x5, test_data; \
+    lhu x26, 0x2(x5); \
+    )
+	TEST_CASE(x8, x27, 0xcc0c, x1, 8, \
+    la  x4, test_data; \
+    lhu x27, -0x4(x4); \
+    )
+	TEST_CASE(x8, x28, 0xdd0d, x1, 12, \
+    la  x3, test_data; \
+    lhu x28, 0x2(x3); \
+    )
+	TEST_CASE(x8, x29, 0xf0, x1, 16, \
+    la  x2, test_data; \
+    lhu x29, 0x4(x2); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_7_res
+
+	TEST_CASE(x4, x30, 0xeee, x2, 0, \
+    la  x1, test_data; \
+    lhu x30, 0x0(x1); \
+    )
+	TEST_CASE(x4, x31, 0xeee, x2, 4, \
+    la  x1, test_data; \
+    lhu x31, 0x0(x1); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+	.align 4
+test_data_start:
+
+	.word 0x11f1f222
+	.word 0xf33344f4
+	.word 0x55f5f666
+	.word 0xf77788f8
+	.word 0x99090aaa
+	.word 0xbbbcc0c
+test_data:
+	.word 0xdd0d0eee
+	.word 0xfff00f0
+	.word 0x12345678
+	.word 0x9abcdef0
+	.word 0x76543210
+	.word 0xfedcba98
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S
new file mode 100644
index 0000000..dcf4f3a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S
@@ -0,0 +1,236 @@
+# RISC-V Compliance Test LUI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LUI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+    TEST_CASE(x6, x0, 0x0, x5, 0, \
+    lui x0, 0x0; \
+    )
+    TEST_CASE(x6, x1, 0x0, x5, 4, \
+    lui x1, 0x0; \
+    )
+    TEST_CASE(x6, x2, 0x7ff000, x5, 8, \
+    lui x2, 0x7ff; \
+    )
+    TEST_CASE(x6, x3, 0x1000, x5, 12, \
+    lui x3, 0x1; \
+    )
+    TEST_CASE(x6, x4, 0x1234000, x5, 16, \
+    lui x4, 0x1234; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+    TEST_CASE(x2, x5, 0x80000000, x1, 0, \
+    lui x5, 0x80000; \
+    )
+    TEST_CASE(x2, x6, 0x1234000, x1, 4, \
+    lui x6, 0x1234; \
+    )
+    TEST_CASE(x2, x7, 0xfffff000, x1, 8, \
+    lui x7, 0xfffff; \
+    )
+    TEST_CASE(x2, x8, 0x1000, x1, 12, \
+    lui x8, 0x1; \
+    )
+    TEST_CASE(x2, x9, 0x7ffff000, x1, 16, \
+    lui x9, 0x7ffff; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+    TEST_CASE(x7, x10, 0x54321000, x1, 0, \
+    lui x10, 0x54321; \
+    )
+    TEST_CASE(x7, x11, 0x800000, x1, 4, \
+    lui x11, 0x800; \
+    )
+    TEST_CASE(x7, x12, 0x0, x1, 8, \
+    lui x12, 0x0; \
+    )
+    TEST_CASE(x7, x13, 0x7ff000, x1, 12, \
+    lui x13, 0x7ff; \
+    )
+    TEST_CASE(x7, x14, 0x0, x1, 16, \
+    lui x14, 0x0; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+    TEST_CASE(x3, x15, 0x1000, x2, 0, \
+    lui x15, 0x1; \
+    )
+    TEST_CASE(x3, x16, 0x0, x2, 4, \
+    lui x16, 0x0; \
+    )
+    TEST_CASE(x3, x17, 0x0, x2, 8, \
+    lui x17, 0x0; \
+    )
+    TEST_CASE(x3, x18, 0x7ff000, x2, 12, \
+    lui x18, 0x7ff; \
+    )
+    TEST_CASE(x3, x19, 0x1000, x2, 16, \
+    lui x19, 0x1; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+    TEST_CASE(x2, x20, 0x1234000, x1, 0, \
+    lui x20, 0x1234; \
+    )
+    TEST_CASE(x2, x21, 0x80000000, x1, 4, \
+    lui x21, 0x80000; \
+    )
+    TEST_CASE(x2, x22, 0x1234000, x1, 8, \
+    lui x22, 0x1234; \
+    )
+    TEST_CASE(x2, x23, 0xfffff000, x1, 12, \
+    lui x23, 0xfffff; \
+    )
+    TEST_CASE(x2, x24, 0x1000, x1, 16, \
+    lui x24, 0x1; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+    TEST_CASE(x7, x25, 0x7ffff000, x1, 0, \
+    lui x25, 0x7ffff; \
+    )
+    TEST_CASE(x7, x26, 0x54321000, x1, 4, \
+    lui x26, 0x54321; \
+    )
+    TEST_CASE(x7, x27, 0x800000, x1, 8, \
+    lui x27, 0x800; \
+    )
+    TEST_CASE(x7, x28, 0x0, x1, 12, \
+    lui x28, 0x0; \
+    )
+    TEST_CASE(x7, x29, 0x7ff000, x1, 16, \
+    lui x29, 0x7ff; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+    TEST_CASE(x3, x30, 0x0, x2, 0, \
+    lui x30, 0x0; \
+    )
+    TEST_CASE(x3, x31, 0x1000, x2, 4, \
+    lui x31, 0x1; \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S
new file mode 100644
index 0000000..dff1b6f
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S
@@ -0,0 +1,284 @@
+# RISC-V Compliance Test LW-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'LW'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test data and results
+	la	x5, test_1_res
+
+	TEST_CASE(x7, x0, 0x0, x5, 0, \
+    la  x31, test_data; \
+    lw x0, 0x0(x31); \
+    )
+	TEST_CASE(x7, x1, 0xdd0d0eee, x5, 4, \
+    la  x30, test_data; \
+    lw x1, 0x0(x30); \
+    )
+	TEST_CASE(x7, x2, 0xdd0d0eee, x5, 8, \
+    la  x29, test_data; \
+    lw x2, 0x0(x29); \
+    )
+	TEST_CASE(x7, x3, 0xbbbcc0c, x5, 12, \
+    la  x28, test_data; \
+    lw x3, -0x4(x28); \
+    )
+	TEST_CASE(x7, x4, 0xdd0d0eee, x5, 16, \
+    la  x27, test_data; \
+    lw x4, 0x0(x27); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_2_res
+
+	TEST_CASE(x3, x5, 0xfff00f0, x1, 0, \
+    la  x26, test_data; \
+    lw x5, 0x4(x26); \
+    )
+	TEST_CASE(x3, x6, 0xdd0d0eee, x1, 4, \
+    la  x25, test_data; \
+    lw x6, 0x0(x25); \
+    )
+	TEST_CASE(x3, x7, 0xdd0d0eee, x1, 8, \
+    la  x24, test_data; \
+    lw x7, 0x0(x24); \
+    )
+	TEST_CASE(x3, x8, 0xdd0d0eee, x1, 12, \
+    la  x23, test_data; \
+    lw x8, 0x0(x23); \
+    )
+	TEST_CASE(x3, x9, 0xdd0d0eee, x1, 16, \
+    la  x22, test_data; \
+    lw x9, 0x0(x22); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_3_res
+
+	TEST_CASE(x8, x10, 0xdd0d0eee, x1, 0, \
+    la  x21, test_data; \
+    lw x10, 0x0(x21); \
+    )
+	TEST_CASE(x8, x11, 0xbbbcc0c, x1, 4, \
+    la  x20, test_data; \
+    lw x11, -0x4(x20); \
+    )
+	TEST_CASE(x8, x12, 0xdd0d0eee, x1, 8, \
+    la  x19, test_data; \
+    lw x12, 0x0(x19); \
+    )
+	TEST_CASE(x8, x13, 0xfff00f0, x1, 12, \
+    la  x18, test_data; \
+    lw x13, 0x4(x18); \
+    )
+	TEST_CASE(x8, x14, 0xdd0d0eee, x1, 16, \
+    la  x17, test_data; \
+    lw x14, 0x0(x17); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_4_res
+
+	TEST_CASE(x4, x15, 0xdd0d0eee, x2, 0, \
+    la  x16, test_data; \
+    lw x15, 0x0(x16); \
+    )
+	TEST_CASE(x4, x16, 0xdd0d0eee, x2, 4, \
+    la  x15, test_data; \
+    lw x16, 0x0(x15); \
+    )
+	TEST_CASE(x4, x17, 0xdd0d0eee, x2, 8, \
+    la  x14, test_data; \
+    lw x17, 0x0(x14); \
+    )
+	TEST_CASE(x4, x18, 0xdd0d0eee, x2, 12, \
+    la  x13, test_data; \
+    lw x18, 0x0(x13); \
+    )
+	TEST_CASE(x4, x19, 0xbbbcc0c, x2, 16, \
+    la  x12, test_data; \
+    lw x19, -0x4(x12); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_5_res
+
+	TEST_CASE(x3, x20, 0xdd0d0eee, x1, 0, \
+    la  x11, test_data; \
+    lw x20, 0x0(x11); \
+    )
+	TEST_CASE(x3, x21, 0xfff00f0, x1, 4, \
+    la  x10, test_data; \
+    lw x21, 0x4(x10); \
+    )
+	TEST_CASE(x3, x22, 0xdd0d0eee, x1, 8, \
+    la  x9, test_data; \
+    lw x22, 0x0(x9); \
+    )
+	TEST_CASE(x3, x23, 0xdd0d0eee, x1, 12, \
+    la  x8, test_data; \
+    lw x23, 0x0(x8); \
+    )
+	TEST_CASE(x3, x24, 0xdd0d0eee, x1, 16, \
+    la  x7, test_data; \
+    lw x24, 0x0(x7); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test data and results
+	la	x1, test_6_res
+
+	TEST_CASE(x8, x25, 0xdd0d0eee, x1, 0, \
+    la  x6, test_data; \
+    lw x25, 0x0(x6); \
+    )
+	TEST_CASE(x8, x26, 0xdd0d0eee, x1, 4, \
+    la  x5, test_data; \
+    lw x26, 0x0(x5); \
+    )
+	TEST_CASE(x8, x27, 0xbbbcc0c, x1, 8, \
+    la  x4, test_data; \
+    lw x27, -0x4(x4); \
+    )
+	TEST_CASE(x8, x28, 0xdd0d0eee, x1, 12, \
+    la  x3, test_data; \
+    lw x28, 0x0(x3); \
+    )
+	TEST_CASE(x8, x29, 0xfff00f0, x1, 16, \
+    la  x2, test_data; \
+    lw x29, 0x4(x2); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test data and results
+	la	x2, test_7_res
+
+	TEST_CASE(x4, x30, 0xdd0d0eee, x2, 0, \
+    la  x1, test_data; \
+    lw x30, 0x0(x1); \
+    )
+	TEST_CASE(x4, x31, 0xdd0d0eee, x2, 4, \
+    la  x1, test_data; \
+    lw x31, 0x0(x1); \
+    )
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+	.align 4
+test_data_start:
+
+	.word 0x11f1f222
+	.word 0xf33344f4
+	.word 0x55f5f666
+	.word 0xf77788f8
+	.word 0x99090aaa
+	.word 0xbbbcc0c
+test_data:
+	.word 0xdd0d0eee
+	.word 0xfff00f0
+	.word 0x12345678
+	.word 0x9abcdef0
+	.word 0x76543210
+	.word 0xfedcba98
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
new file mode 100644
index 0000000..0dc6869
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
@@ -0,0 +1,346 @@
+# RISC-V Compliance Test I-MISALIGN_JMP-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing MISALIGNED JUMP exception.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x30, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x30, "# Test Begin Reserved reg x31\n")
+
+    # Save and set trap handler address
+    la x1, _trap_handler
+    csrrw x31, mtvec, x1
+
+    # switch off C
+    csrrci   x0, misa, 4
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1 - test JAL\n");
+
+    # Address for test results
+    la      x1, test_A1_res_exc
+
+    # Test
+    li      x2, 0x11111111
+    jal     x0, 1f + 2
+    li      x2, 0
+1:
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2 - test JALR - NOT causing the exception\n");
+
+    # Address for test results
+    la      x1, test_A2_res
+
+    # Test
+    li      x2, 0x22222222
+    la      x4, 1f + 1
+    jalr    x0, x4, 0
+    li      x2, 0
+1:
+    sw      x2, 0(x1)
+    addi    x1, x1, 4
+
+    li      x2, 0x33333333
+    la      x4, 1f
+    jalr    x0, x4, 1
+    li      x2, 0
+1:
+    sw      x2, 0(x1)
+    addi    x1, x1, 4
+
+    li      x2, 0x44444444
+    la      x4, 1f
+    jalr    x0, x4, -3
+    li      x2, 0
+
+    sw      x2, 0(x1)
+1:
+    addi    x1, x1, 4
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A3 - test JALR - causing the exception\n");
+
+    # Address for test results
+    la      x1, test_A3_res_exc
+
+    # Test
+    li      x2, 0x55555555
+    la      x4, 1f + 2
+    jalr    x0, x4, 0
+    li      x2, 0
+1:
+
+    li      x2, 0x66666666
+    la      x4, 1f + 3
+    jalr    x0, x4, 0
+    li      x2, 0
+1:
+
+    # Test
+    li      x2, 0x77777777
+    la      x4, 1f
+    jalr    x0, x4, 2
+    li      x2, 0
+1:
+
+    li      x2, 0x88888888
+    la      x4, 1f
+    jalr    x0, x4, 3
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B1 - test BEQ\n");
+
+    # Address for test results
+    la      x1, test_B1_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    beq     x5, x6, 1f + 2
+    li      x2, 0x99999999
+1:
+    nop
+    nop
+    beq     x5, x5, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B2 - test BNE\n");
+
+    # Address for test results
+    la      x1, test_B2_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    bne     x5, x5, 1f + 2
+    li      x2, 0xAAAAAAAA
+1:
+    nop
+    nop
+    bne     x5, x6, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A5  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B3 - test BLT\n");
+
+    # Address for test results
+    la      x1, test_B3_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    blt     x6, x5, 1f + 2
+    li      x2, 0xBBBBBBBB
+1:
+    nop
+    nop
+    blt     x5, x6, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part B  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B4 - test BLTU\n");
+
+    # Address for test results
+    la      x1, test_B4_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    bltu    x6, x5, 1f + 2
+    li      x2, 0xCCCCCCCC
+1:
+    nop
+    nop
+    bltu    x5, x6, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part C  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B5 - test BGE\n");
+
+    # Address for test results
+    la      x1, test_B5_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    bge     x5, x6, 1f + 2
+    li      x2, 0xDDDDDDDD
+1:
+    nop
+    nop
+    bge     x6, x5, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part D  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B6 - test BGEU\n");
+
+    # Address for test results
+    la      x1, test_B6_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    bgeu    x5, x6, 1f + 2
+    li      x2, 0xEEEEEEEE
+1:
+    nop
+    nop
+    bgeu    x6, x5, 1f + 2
+    li      x2, 0
+1:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part E  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # restore mtvec and jump to the end
+    csrw mtvec, x31
+    jal x0, test_end
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # Exception handler
+_trap_handler:
+    # increment return address
+    csrr    x30, mtval
+    addi    x30, x30, -2
+    csrw    mepc, x30
+
+    # store low bits of mtval
+    csrr    x30, mtval
+    andi    x30, x30, 3
+    sw      x30, 0(x1)
+
+    # Store MCAUSE
+    csrr    x30, mcause
+    sw      x30, 4(x1)
+
+    # Store data from test
+    sw      x2, 8(x1)
+
+    # increment data_exc address
+    addi    x1, x1, 12
+
+    # return
+    mret
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+
+test_end:
+    RVTEST_IO_WRITE_STR(x30, "# Test part A3  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x30, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res_exc:
+    .fill 3, 4, -1
+test_A2_res:
+    .fill 3, 4, -1
+test_A3_res_exc:
+    .fill 12, 4, -1
+test_B1_res_exc:
+    .fill 3, 4, -1
+test_B2_res_exc:
+    .fill 3, 4, -1
+test_B3_res_exc:
+    .fill 3, 4, -1
+test_B4_res_exc:
+    .fill 3, 4, -1
+test_B5_res_exc:
+    .fill 3, 4, -1
+test_B6_res_exc:
+    .fill 3, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
new file mode 100644
index 0000000..8fba0c5
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
@@ -0,0 +1,256 @@
+# RISC-V Compliance Test I-MISALIGN_LDST-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing MISALIGNED LOAD/STORE exception.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x30, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x30, "# Test Begin Reserved reg x31\n")
+
+    # Save and set trap handler address
+    la x1, _trap_handler
+    csrrw x31, mtvec, x1
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1 - test LW\n");
+
+    # Addresses for test data and results
+    la      x3, test_A1_data
+    la      x2, test_A1_res
+    la      x1, test_A1_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    lw      x4, 0(x3)
+    sw      x4, 0(x2)
+
+    lw      x4, 1(x3)
+    sw      x4, 4(x2)
+
+    lw      x4, 2(x3)
+    sw      x4, 8(x2)
+
+    lw      x4, 3(x3)
+    sw      x4, 12(x2)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_WRITE_STR(x30, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2 - test LH and LHU\n");
+
+    # Addresses for test data and results
+    la      x3, test_A2_data
+    la      x2, test_A2_res
+    la      x1, test_A2_res_exc
+
+    # Register initialization
+    li      x5, 5
+    li      x6, 6
+
+    # Test
+    lh      x4, 0(x3)
+    sw      x4, 0(x2)
+
+    lh      x4, 1(x3)
+    sw      x4, 4(x2)
+
+    lh      x4, 2(x3)
+    sw      x4, 8(x2)
+
+    lh      x4, 3(x3)
+    sw      x4, 12(x2)
+
+    lhu     x4, 0(x3)
+    sw      x4, 16(x2)
+
+    lhu     x4, 1(x3)
+    sw      x4, 20(x2)
+
+    lhu     x4, 2(x3)
+    sw      x4, 24(x2)
+
+    lhu     x4, 3(x3)
+    sw      x4, 28(x2)
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B1 - test SW\n");
+
+    # Addresses for test data and results
+    la      x2, test_B1_res
+    la      x1, test_B1_res_exc
+
+    # Register initialization
+    li      x6, 0x0
+    li      x5, 0x99999999
+
+    # Init memory
+    sw      x5, 0(x2)
+    sw      x5, 4(x2)
+    sw      x5, 8(x2)
+    sw      x5, 12(x2)
+
+    # Test
+    sw      x6, 0(x2)
+    addi    x2, x2, 4
+
+    sw      x6, 1(x2)
+    addi    x2, x2, 4
+
+    sw      x6, 2(x2)
+    addi    x2, x2, 4
+
+    sw      x6, 3(x2)
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x30, "# Test part B2 - test SH\n");
+
+    # Addresses for test data and results
+    la      x2, test_B2_res
+    la      x1, test_B2_res_exc
+
+    # Register initialization
+    li      x6, 0x0
+    li      x5, 0x99999999
+
+    # Init memory
+    sw      x5, 0(x2)
+    sw      x5, 4(x2)
+    sw      x5, 8(x2)
+    sw      x5, 12(x2)
+
+    # Test
+    sh      x6, 0(x2)
+    addi    x2, x2, 4
+
+    sh      x6, 1(x2)
+    addi    x2, x2, 4
+
+    sh      x6, 2(x2)
+    addi    x2, x2, 4
+
+    sh      x6, 3(x2)
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # restore mtvec and jump to the end
+    csrw mtvec, x31
+    jal x0, test_end
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part A5  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    # Exception handler
+_trap_handler:
+    # increment return address
+    csrr    x30, mepc
+    addi    x30, x30, 4
+    csrw    mepc, x30
+
+    # store low bits of mtval
+    csrr    x30, mtval
+    andi    x30, x30, 3
+    sw      x30, 0(x1)
+
+    # Store MCAUSE
+    csrr    x30, mcause
+    sw      x30, 4(x1)
+
+    # increment data_exc address
+    addi    x1, x1, 8
+
+    # return
+    mret
+
+    RVTEST_IO_WRITE_STR(x30, "# Test part B  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+
+test_end:
+
+    RVTEST_IO_WRITE_STR(x30, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+test_A1_data:
+    .word 0x91A1B1C1
+test_A2_data:
+    .word 0xD2E2F202
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 4, 4, -1
+test_A1_res_exc:
+    .fill 6, 4, -1
+test_A2_res:
+    .fill 8, 4, -1
+test_A2_res_exc:
+    .fill 8, 4, -1
+test_B1_res:
+    .fill 4, 4, -1
+test_B1_res_exc:
+    .fill 6, 4, -1
+test_B2_res:
+    .fill 4, 4, -1
+test_B2_res_exc:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S
new file mode 100644
index 0000000..a7ac2af
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S
@@ -0,0 +1,211 @@
+# RISC-V Compliance Test I-NOP-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing pseudo instruction NOP.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region.
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test, instruction should not change any register\n");
+
+    # Addresses for test data and results
+    la      x1, test_A1_res
+
+    # Register initialization
+    li      x2, 2
+    li      x3, 3
+    li      x4, 4
+    li      x5, 5
+    li      x6, 6
+    li      x7, 7
+    li      x8, 8
+    li      x9, 9
+    li      x10, 10
+    li      x11, 11
+    li      x12, 12
+    li      x13, 13
+    li      x14, 14
+    li      x15, 15
+    li      x16, 16
+    li      x17, 17
+    li      x18, 18
+    li      x19, 19
+    li      x20, 20
+    li      x21, 21
+    li      x22, 22
+    li      x23, 23
+    li      x24, 24
+    li      x25, 25
+    li      x26, 26
+    li      x27, 27
+    li      x28, 28
+    li      x29, 29
+    li      x30, 30
+    li      x31, 31
+
+    #Test
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
+
+    # Store results
+    sw      x0, 0( x1 )
+    sw      x2, 4( x1 )
+    sw      x3, 8( x1 )
+    sw      x4, 12( x1 )
+    sw      x5, 16( x1 )
+    sw      x6, 20( x1 )
+    sw      x7, 24( x1 )
+    sw      x8, 28( x1 )
+    sw      x9, 32( x1 )
+    sw      x10, 36( x1 )
+    sw      x11, 40( x1 )
+    sw      x12, 44( x1 )
+    sw      x13, 48( x1 )
+    sw      x14, 52( x1 )
+    sw      x15, 56( x1 )
+    sw      x16, 60( x1 )
+    sw      x17, 64( x1 )
+    sw      x18, 68( x1 )
+    sw      x19, 72( x1 )
+    sw      x20, 76( x1 )
+    sw      x21, 80( x1 )
+    sw      x22, 84( x1 )
+    sw      x23, 88( x1 )
+    sw      x24, 92( x1 )
+    sw      x25, 96( x1 )
+    sw      x26, 100( x1 )
+    sw      x27, 104( x1 )
+    sw      x28, 108( x1 )
+    sw      x29, 112( x1 )
+    sw      x30, 116( x1 )
+    sw      x31, 120( x1 )
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x2,  0x00000002)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x3,  0x00000003)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x4,  0x00000004)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x5,  0x00000005)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x6,  0x00000006)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x7,  0x00000007)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x8,  0x00000008)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x9,  0x00000009)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x10, 0x0000000A)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x11, 0x0000000B)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x12, 0x0000000C)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x13, 0x0000000D)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x14, 0x0000000E)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x15, 0x0000000F)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x16, 0x00000010)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x17, 0x00000011)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x18, 0x00000012)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x19, 0x00000013)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x20, 0x00000014)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x21, 0x00000015)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x22, 0x00000016)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x23, 0x00000017)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x24, 0x00000018)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x25, 0x00000019)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x26, 0x0000001A)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x27, 0x0000001B)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x28, 0x0000001C)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x29, 0x0000001D)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x30, 0x0000001E)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x31, 0x0000001F)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test, only 5 cycles are executed\n");
+
+    # Addresses for test data and results
+    la          x3, test_A2_res
+
+    # Register initialization
+    auipc   x8, 0
+
+    #Test
+    nop
+    nop
+    nop
+    nop
+    nop
+
+    # Store results
+    auipc   x9, 0
+    sub     x9, x9, x8
+
+    # Store results
+    sw      x9, 0( x3 )
+
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x9, 0x00000018)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 31, 4, -1
+test_A2_res:
+    .fill 1, 4, -1
+
+RV_COMPLIANCE_DATA_END     # End of test output data region.
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S
new file mode 100644
index 0000000..0740530
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test OR-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'OR'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(or, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(or, x1, x30, x15, 0xfffff801, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(or, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(or, x3, x28, x13, 0xffffefff, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(or, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(or, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(or, x6, x25, x10, 0xffffffff, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(or, x7, x24, x9, 0x7fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(or, x8, x23, x8, 0x7fffffff, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(or, x9, x22, x7, 0xffffffff, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(or, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(or, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(or, x12, x19, x4, 0xffffefff, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(or, x13, x18, x3, 0xffffffff, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(or, x14, x17, x2, 0xfffff801, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(or, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(or, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(or, x17, x14, x31, 0xfffff801, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(or, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(or, x19, x12, x29, 0xffffefff, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(or, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(or, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(or, x22, x9, x26, 0xffffffff, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(or, x23, x8, x25, 0x7fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(or, x24, x7, x24, 0x7fffffff, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(or, x25, x6, x23, 0xffffffff, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(or, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(or, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(or, x28, x3, x20, 0xffffefff, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(or, x29, x2, x19, 0xffffffff, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(or, x30, x1, x18, 0xfffff801, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(or, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S
new file mode 100644
index 0000000..d6ceb8c
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test ORI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'ORI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(ori, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(ori, x1, x30, 0xfffff801, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(ori, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(ori, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(ori, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(ori, x5, x26, 0xfffff800, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(ori, x6, x25, 0xfffffb21, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(ori, x7, x24, 0x7fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(ori, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(ori, x9, x22, 0xffffffff, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(ori, x10, x21, 0xfffffa34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(ori, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(ori, x12, x19, 0xffffefff, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(ori, x13, x18, 0xffffffff, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(ori, x14, x17, 0xfffff801, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(ori, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(ori, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(ori, x17, x14, 0xfffff801, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(ori, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(ori, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(ori, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(ori, x21, x10, 0xfffff800, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(ori, x22, x9, 0xfffffb21, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(ori, x23, x8, 0x7fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(ori, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(ori, x25, x6, 0xffffffff, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(ori, x26, x5, 0xfffffa34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(ori, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(ori, x28, x3, 0xffffefff, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(ori, x29, x2, 0xffffffff, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(ori, x30, x1, 0xfffff801, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(ori, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S
new file mode 100644
index 0000000..9a0dfc0
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S
@@ -0,0 +1,209 @@
+# RISC-V Compliance Test I-RF_size-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing size of register file.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test registers x0 - x15\n");
+
+    # Address for test results
+    la      x16, test_A1_res
+
+    # Test
+    li      x0, 0x42726e6f
+    li      x1, 0x56333249
+    li      x2, 0x2d562052
+    li      x3, 0x52697363
+    li      x4, 0x736b7920
+    li      x5, 0x73746572
+    li      x6, 0x6e204e6f
+    li      x7, 0x4d696c61
+    li      x8, 0x6f646173
+    li      x9, 0x6b794063
+    li      x10, 0x74657273
+    li      x11, 0x286e6f73
+    li      x12, 0x656b2048
+    li      x13, 0x20526164
+    li      x14, 0x6f6d292c
+    li      x15, 0x69702e63
+
+    # Store results
+    sw      x0, 0(x16)
+    sw      x1, 4(x16)
+    sw      x2, 8(x16)
+    sw      x3, 12(x16)
+    sw      x4, 16(x16)
+    sw      x5, 20(x16)
+    sw      x6, 24(x16)
+    sw      x7, 28(x16)
+    sw      x8, 32(x16)
+    sw      x9, 36(x16)
+    sw      x10, 40(x16)
+    sw      x11, 44(x16)
+    sw      x12, 48(x16)
+    sw      x13, 52(x16)
+    sw      x14, 56(x16)
+    sw      x15, 60(x16)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x0, 0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x1, 0x56333249)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x2, 0x2D562052)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x3, 0x52697363)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x4, 0x736B7920)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x5, 0x73746572)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x6, 0x6E204E6F)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x7, 0x4D696C61)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x8, 0x6F646173)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x9, 0x6B794063)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x10, 0x74657273)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x11, 0x286E6F73)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x12, 0x656B2048)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x13, 0x20526164)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x14, 0x6F6D292C)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x15, 0x69702E63)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test registers x16 - x30\n");
+
+    # Address for test results
+    la      x4, test_A2_res
+
+    # Test
+    li      x16, 0x636f6461
+    li      x17, 0x6a656b40
+    li      x18, 0x20286861
+    li      x19, 0x616a656b
+    li      x20, 0x61766520
+    li      x21, 0x2e204c65
+    li      x22, 0x636f6d29
+    li      x23, 0x7369702e
+    li      x24, 0x6620796f
+    li      x25, 0x67652069
+    li      x26, 0x65737361
+    li      x27, 0x7573206d
+    li      x28, 0x3a290d0a
+    li      x29, 0x68697320
+    li      x30, 0x61642074
+    li      x31, 0x75207265
+
+    # Store results
+    sw      x16, 0(x4)
+    sw      x17, 4(x4)
+    sw      x18, 8(x4)
+    sw      x19, 12(x4)
+    sw      x20, 16(x4)
+    sw      x21, 20(x4)
+    sw      x22, 24(x4)
+    sw      x23, 28(x4)
+    sw      x24, 32(x4)
+    sw      x25, 36(x4)
+    sw      x26, 40(x4)
+    sw      x27, 44(x4)
+    sw      x28, 48(x4)
+    sw      x29, 52(x4)
+    sw      x30, 56(x4)
+    sw      x31, 60(x4)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x16, 0x636F6461)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x17, 0x6A656B40)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x18, 0x20286861)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x19, 0x616A656B)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x20, 0x61766520)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x21, 0x2E204C65)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x22, 0x636F6D29)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x23, 0x7369702E)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x24, 0x6620796F)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x25, 0x67652069)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x26, 0x65737361)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x27, 0x7573206D)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x28, 0x3A290D0A)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x29, 0x68697320)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x30, 0x61642074)
+    RVTEST_IO_ASSERT_GPR_EQ(x4, x31, 0x75207265)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test registers x0 - x3 again (were not overwritten)\n");
+
+    # Address for test results
+    la      x4, test_A3_res
+
+    # Test
+    sw      x0, 0(x4)
+    sw      x1, 4(x4)
+    sw      x2, 8(x4)
+    sw      x3, 12(x4)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 16, 4, -1
+test_A2_res:
+    .fill 16, 4, -1
+test_A3_res:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S
new file mode 100644
index 0000000..2291707
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S
@@ -0,0 +1,353 @@
+# RISC-V Compliance Test I-RF_width-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing width of register file.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test x1 - x15 are 32 bits\n");
+
+    # Address for test results
+    la      x16, test_A1_res
+
+    # Init registers
+    li      x0, 1
+    li      x1, 1
+    li      x2, 1
+    li      x3, 1
+    li      x4, 1
+    li      x5, 1
+    li      x6, 1
+    li      x7, 1
+    li      x8, 1
+    li      x9, 1
+    li      x10, 1
+    li      x11, 1
+    li      x12, 1
+    li      x13, 1
+    li      x14, 1
+    li      x15, 1
+
+
+    # Test
+    slli    x1, x1, 31
+    bltz    x1, 1f
+    li      x1, 0
+
+1:
+    slli    x2, x2, 31
+    bltz    x2, 1f
+    li      x2, 0
+
+1:
+    slli    x3, x3, 31
+    bltz    x3, 1f
+    li      x3, 0
+
+1:
+    slli    x4, x4, 31
+    bltz    x4, 1f
+    li      x4, 0
+
+1:
+    slli    x5, x5, 31
+    bltz    x5, 1f
+    li      x5, 0
+
+1:
+    slli    x6, x6, 31
+    bltz    x6, 1f
+    li      x6, 0
+
+1:
+    slli    x7, x7, 31
+    bltz    x7, 1f
+    li      x7, 0
+
+1:
+    slli    x8, x8, 31
+    bltz    x8, 1f
+    li      x8, 0
+
+1:
+    slli    x9, x9, 31
+    bltz    x9, 1f
+    li      x9, 0
+
+1:
+    slli    x10, x10, 31
+    bltz    x10, 1f
+    li      x10, 0
+
+1:
+    slli    x11, x11, 31
+    bltz    x11, 1f
+    li      x11, 0
+
+1:
+    slli    x12, x12, 31
+    bltz    x12, 1f
+    li      x12, 0
+
+1:
+    slli    x13, x13, 31
+    bltz    x13, 1f
+    li      x13, 0
+
+1:
+    slli    x14, x14, 31
+    bltz    x14, 1f
+    li      x14, 0
+
+1:
+    slli    x15, x15, 31
+    bltz    x15, 1f
+    li      x15, 0
+
+1:
+
+    # Store results
+    sw      x0, 0(x16)
+    sw      x1, 4(x16)
+    sw      x2, 8(x16)
+    sw      x3, 12(x16)
+    sw      x4, 16(x16)
+    sw      x5, 20(x16)
+    sw      x6, 24(x16)
+    sw      x7, 28(x16)
+    sw      x8, 32(x16)
+    sw      x9, 36(x16)
+    sw      x10, 40(x16)
+    sw      x11, 44(x16)
+    sw      x12, 48(x16)
+    sw      x13, 52(x16)
+    sw      x14, 56(x16)
+    sw      x15, 60(x16)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x0,  0x00000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x1,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x2,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x3,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x4,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x5,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x6,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x7,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x8,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x9,  0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x10, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x11, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x12, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x13, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x14, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x16, x15, 0x80000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test x16 - x30 are 32 bits\n");
+
+    # Address for test results
+    la      x1, test_A2_res
+
+    # Init registers
+    li      x16, 1
+    li      x17, 1
+    li      x18, 1
+    li      x19, 1
+    li      x20, 1
+    li      x21, 1
+    li      x22, 1
+    li      x23, 1
+    li      x24, 1
+    li      x25, 1
+    li      x26, 1
+    li      x27, 1
+    li      x28, 1
+    li      x29, 1
+    li      x30, 1
+    li      x31, 1
+
+    # Test
+    slli    x16, x16, 31
+    bltz    x16, 1f
+    li      x16, 0
+
+1:
+    slli    x17, x17, 31
+    bltz    x17, 1f
+    li      x17, 0
+
+1:
+    slli    x18, x18, 31
+    bltz    x18, 1f
+    li      x18, 0
+
+1:
+    slli    x19, x19, 31
+    bltz    x19, 1f
+    li      x19, 0
+
+1:
+    slli    x20, x20, 31
+    bltz    x20, 1f
+    li      x20, 0
+
+1:
+    slli    x21, x21, 31
+    bltz    x21, 1f
+    li      x21, 0
+
+1:
+    slli    x22, x22, 31
+    bltz    x22, 1f
+    li      x22, 0
+
+1:
+    slli    x23, x23, 31
+    bltz    x23, 1f
+    li      x23, 0
+
+1:
+    slli    x24, x24, 31
+    bltz    x24, 1f
+    li      x24, 0
+
+1:
+    slli    x25, x25, 31
+    bltz    x25, 1f
+    li      x25, 0
+
+1:
+    slli    x26, x26, 31
+    bltz    x26, 1f
+    li      x26, 0
+
+1:
+    slli    x27, x27, 31
+    bltz    x27, 1f
+    li      x27, 0
+
+1:
+    slli    x28, x28, 31
+    bltz    x28, 1f
+    li      x28, 0
+
+1:
+    slli    x29, x29, 31
+    bltz    x29, 1f
+    li      x29, 0
+
+1:
+    slli    x30, x30, 31
+    bltz    x30, 1f
+    li      x30, 0
+
+1:
+    slli    x31, x31, 31
+    bltz    x31, 1f
+    li      x31, 0
+
+1:
+
+    # Store results
+    sw      x16, 0(x1)
+    sw      x17, 4(x1)
+    sw      x18, 8(x1)
+    sw      x19, 12(x1)
+    sw      x20, 16(x1)
+    sw      x21, 20(x1)
+    sw      x22, 24(x1)
+    sw      x23, 28(x1)
+    sw      x24, 32(x1)
+    sw      x25, 36(x1)
+    sw      x26, 40(x1)
+    sw      x27, 44(x1)
+    sw      x28, 48(x1)
+    sw      x29, 52(x1)
+    sw      x30, 56(x1)
+    sw      x31, 60(x1)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x16, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x17, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x18, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x19, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x20, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x21, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x22, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x23, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x24, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x25, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x26, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x27, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x28, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x29, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x30, 0x80000000)
+    RVTEST_IO_ASSERT_GPR_EQ(x1, x31, 0x80000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 16, 4, -1
+test_A2_res:
+    .fill 16, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S
new file mode 100644
index 0000000..8f282d5
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S
@@ -0,0 +1,201 @@
+# RISC-V Compliance Test I-RF_x0-01
+#
+# Copyright (c) 2017, Codasip Ltd.
+# Copyright (c) 2018, Imperas Software Ltd. Additions
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.0
+# Description: Testing x0 is hardwired 0.
+
+#include "compliance_test.h"
+#include "compliance_io.h"
+#include "test_macros.h"
+
+# Test Virtual Machine (TVM) used by program.
+RV_COMPLIANCE_RV32M
+
+# Test code region
+RV_COMPLIANCE_CODE_BEGIN
+
+    RVTEST_IO_INIT
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test computational instructions - register-immediate\n");
+
+    # Address for test results
+    la      x31, test_A1_res
+
+    # Test
+    lui     x0, 0xABCDE
+    addi    x0, x0, 1
+    ori     x0, x0, 0x7F0
+    andi    x0, x0, 0x53F
+    xori    x0, x0, 0xFFFFF803
+    slli    x0, x0, 5
+    srai    x0, x0, 2
+    srli    x0, x0, 4
+
+    # Store results
+    sw      x0, 0(x31)
+
+    //
+    // Assert
+    //
+    RVTEST_IO_CHECK()
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test computational instructions - register-register\n");
+
+    # Address for test results
+    la      x31, test_A2_res
+
+    # Register initialization
+    li      x1,  0x1
+    li      x2,  0x7F0
+    li      x3,  0x53F
+    li      x4,  0xFFFFF803
+    li      x5,  0x5
+    li      x6,  0x2
+    li      x7,  0x4
+    li      x8,  0x18
+
+    # Test
+    auipc   x0, 0xABCDE
+    add     x0, x0, x1
+    or      x0, x0, x2
+    and     x0, x0, x3
+    xor     x0, x0, x4
+    sll     x0, x0, x5
+    sra     x0, x0, x6
+    srl     x0, x0, x7
+    sub     x0, x0, x8
+
+    # Store results
+    sw      x0, 0(x31)
+
+    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A2  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test compare instructions\n");
+
+    # Address for test results
+    la      x31, test_A3_res
+
+    # Register initialization
+    li     x1,  0x1
+    li     x2,  0x2
+
+    # Test and store
+    slt     x0, x1, x2
+    sw      x0, 0(x31)
+
+    sltu    x0, x1, x2
+    sw      x0, 4(x31)
+
+    slti    x0, x1, 2
+    sw      x0, 8(x31)
+
+    sltiu   x0, x1, 2
+    sw      x0, 12(x31)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A3  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test jump and link instructions\n");
+
+    # Address for test results
+    la      x31, test_A4_res
+
+    # Test and store
+    jal     x0, 1f
+1:
+    sw      x0, 0(x31)
+
+    la      x1, 1f
+    jalr    x0, x1, 0
+1:
+    sw      x0, 4(x31)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A4  - Complete\n");
+
+    # ---------------------------------------------------------------------------------------------
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test load instructions\n");
+
+    # Addresses for test data and results
+    la      x1, test_A5_data
+    la      x31, test_A5_res
+
+    # Test and store
+    lw      x0, 0(x1)
+    sw      x0, 0(x31)
+
+    lh      x0, 0(x1)
+    sw      x0, 4(x31)
+
+    lb      x0, 0(x1)
+    sw      x0, 8(x31)
+
+    lbu     x0, 0(x1)
+    sw      x0, 12(x31)
+
+    RVTEST_IO_WRITE_STR(x31, "# Test part A5  - Complete\n");
+
+    RVTEST_IO_WRITE_STR(x31, "# Test End\n")
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+    .data
+    .align 4
+test_A5_data:
+    .word 0x42524E4F
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+    .align 4
+
+test_A1_res:
+    .fill 1, 4, -1
+test_A2_res:
+    .fill 1, 4, -1
+test_A3_res:
+    .fill 4, 4, -1
+test_A4_res:
+    .fill 2, 4, -1
+test_A5_res:
+    .fill 4, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S
new file mode 100644
index 0000000..8341fae
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S
@@ -0,0 +1,428 @@
+# RISC-V Compliance Test SB-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SB'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test results
+	la	x5, test_1_res
+
+    # Clear memory
+    sb      x0, 0x0(x5)
+    # Test
+    li      x16, -0x1
+    addi    x31, x5, 0
+    sb      x16, 0x0(x31)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x31, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x16, -0x1)
+    # Clear memory
+    sb      x0, -0x2(x5)
+    # Test
+    li      x15, 0x1
+    addi    x30, x5, 0
+    sb      x15, -0x2(x30)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x30, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x15, 0x1)
+    # Clear memory
+    sb      x0, 0x3(x5)
+    # Test
+    li      x14, 0x0
+    addi    x29, x5, 0
+    sb      x14, 0x3(x29)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x29, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x14, 0x0)
+    # Clear memory
+    sb      x0, -0x4(x5)
+    # Test
+    li      x13, 0x7ff
+    addi    x28, x5, 0
+    sb      x13, -0x4(x28)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x28, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x13, 0x7ff)
+    # Clear memory
+    sb      x0, 0x2(x5)
+    # Test
+    li      x12, 0x0
+    addi    x27, x5, 0
+    sb      x12, 0x2(x27)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x27, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x12, 0x0)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test results
+	la	x1, test_2_res
+
+    # Clear memory
+    sb      x0, 0x4(x1)
+    # Test
+    li      x11, 0x800
+    addi    x26, x1, 0
+    sb      x11, 0x4(x26)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x26, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x800)
+    # Clear memory
+    sb      x0, -0x1(x1)
+    # Test
+    li      x10, 0x7654321
+    addi    x25, x1, 0
+    sb      x10, -0x1(x25)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x25, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7654321)
+    # Clear memory
+    sb      x0, 0x1(x1)
+    # Test
+    li      x9, 0x7fffffff
+    addi    x24, x1, 0
+    sb      x9, 0x1(x24)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x24, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7fffffff)
+    # Clear memory
+    sb      x0, 0x0(x1)
+    # Test
+    li      x8, 0x1
+    addi    x23, x1, 0
+    sb      x8, 0x0(x23)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x23, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1)
+    # Clear memory
+    sb      x0, -0x2(x1)
+    # Test
+    li      x7, 0xffffffff
+    addi    x22, x1, 0
+    sb      x7, -0x2(x22)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x22, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xffffffff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test results
+	la	x1, test_3_res
+
+    # Clear memory
+    sb      x0, 0x3(x1)
+    # Test
+    li      x6, 0x1234
+    addi    x21, x1, 0
+    sb      x6, 0x3(x21)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x21, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x6, 0x1234)
+    # Clear memory
+    sb      x0, -0x4(x1)
+    # Test
+    li      x5, 0x80000000
+    addi    x20, x1, 0
+    sb      x5, -0x4(x20)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x20, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x5, 0x80000000)
+    # Clear memory
+    sb      x0, 0x2(x1)
+    # Test
+    li      x4, -0x1234
+    addi    x19, x1, 0
+    sb      x4, 0x2(x19)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x19, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x4, -0x1234)
+    # Clear memory
+    sb      x0, 0x4(x1)
+    # Test
+    li      x3, -0x1
+    addi    x18, x1, 0
+    sb      x3, 0x4(x18)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x18, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x3, -0x1)
+    # Clear memory
+    sb      x0, -0x1(x1)
+    # Test
+    li      x2, -0x7ff
+    addi    x17, x1, 0
+    sb      x2, -0x1(x17)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x17, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x2, -0x7ff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test results
+	la	x2, test_4_res
+
+    # Clear memory
+    sb      x0, 0x1(x2)
+    # Test
+    li      x1, 0x0
+    addi    x16, x2, 0
+    sb      x1, 0x1(x16)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x16, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x1, 0x0)
+    # Clear memory
+    sb      x0, 0x0(x2)
+    # Test
+    li      x0, -0x1
+    addi    x15, x2, 0
+    sb      x0, 0x0(x15)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x15, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x0, 0)
+    # Clear memory
+    sb      x0, -0x2(x2)
+    # Test
+    li      x31, 0x1
+    addi    x14, x2, 0
+    sb      x31, -0x2(x14)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x14, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1)
+    # Clear memory
+    sb      x0, 0x3(x2)
+    # Test
+    li      x30, 0x0
+    addi    x13, x2, 0
+    sb      x30, 0x3(x13)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x13, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0)
+    # Clear memory
+    sb      x0, -0x4(x2)
+    # Test
+    li      x29, 0x7ff
+    addi    x12, x2, 0
+    sb      x29, -0x4(x12)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x12, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x29, 0x7ff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test results
+	la	x1, test_5_res
+
+    # Clear memory
+    sb      x0, 0x2(x1)
+    # Test
+    li      x28, 0x0
+    addi    x11, x1, 0
+    sb      x28, 0x2(x11)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x11, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x0)
+    # Clear memory
+    sb      x0, 0x4(x1)
+    # Test
+    li      x27, 0x800
+    addi    x10, x1, 0
+    sb      x27, 0x4(x10)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x10, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x800)
+    # Clear memory
+    sb      x0, -0x1(x1)
+    # Test
+    li      x26, 0x7654321
+    addi    x9, x1, 0
+    sb      x26, -0x1(x9)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x9, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7654321)
+    # Clear memory
+    sb      x0, 0x1(x1)
+    # Test
+    li      x25, 0x7fffffff
+    addi    x8, x1, 0
+    sb      x25, 0x1(x8)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x8, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x7fffffff)
+    # Clear memory
+    sb      x0, 0x0(x1)
+    # Test
+    li      x24, 0x1
+    addi    x7, x1, 0
+    sb      x24, 0x0(x7)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x7, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test results
+	la	x1, test_6_res
+
+    # Clear memory
+    sb      x0, -0x2(x1)
+    # Test
+    li      x23, 0xffffffff
+    addi    x6, x1, 0
+    sb      x23, -0x2(x6)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x6, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x23, 0xffffffff)
+    # Clear memory
+    sb      x0, 0x3(x1)
+    # Test
+    li      x22, 0x1234
+    addi    x5, x1, 0
+    sb      x22, 0x3(x5)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x5, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x22, 0x1234)
+    # Clear memory
+    sb      x0, -0x4(x1)
+    # Test
+    li      x21, 0x80000000
+    addi    x4, x1, 0
+    sb      x21, -0x4(x4)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x4, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x21, 0x80000000)
+    # Clear memory
+    sb      x0, 0x2(x1)
+    # Test
+    li      x20, -0x1234
+    addi    x3, x1, 0
+    sb      x20, 0x2(x3)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x3, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x20, -0x1234)
+    # Clear memory
+    sb      x0, 0x4(x1)
+    # Test
+    li      x19, -0x1
+    addi    x2, x1, 0
+    sb      x19, 0x4(x2)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x2, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x19, -0x1)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test results
+	la	x2, test_7_res
+
+    # Clear memory
+    sb      x0, -0x1(x2)
+    # Test
+    li      x18, -0x7ff
+    addi    x1, x2, 0
+    sb      x18, -0x1(x1)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x18, -0x7ff)
+    # Clear memory
+    sb      x0, 0x1(x2)
+    # Test
+    li      x17, 0x0
+    addi    x1, x2, 0
+    sb      x17, 0x1(x1)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0)
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+	.fill 1, 4, -1    //padding because negative offsets are used
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S
new file mode 100644
index 0000000..fadcd49
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S
@@ -0,0 +1,428 @@
+# RISC-V Compliance Test SH-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SH'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test results
+	la	x5, test_1_res
+
+    # Clear memory
+    sh      x0, 0x0(x5)
+    # Test
+    li      x16, -0x1
+    addi    x31, x5, 0
+    sh      x16, 0x0(x31)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x31, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x16, -0x1)
+    # Clear memory
+    sh      x0, -0x2(x5)
+    # Test
+    li      x15, 0x1
+    addi    x30, x5, 0
+    sh      x15, -0x2(x30)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x30, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x15, 0x1)
+    # Clear memory
+    sh      x0, 0x2(x5)
+    # Test
+    li      x14, 0x0
+    addi    x29, x5, 0
+    sh      x14, 0x2(x29)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x29, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x14, 0x0)
+    # Clear memory
+    sh      x0, -0x4(x5)
+    # Test
+    li      x13, 0x7ff
+    addi    x28, x5, 0
+    sh      x13, -0x4(x28)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x28, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x13, 0x7ff)
+    # Clear memory
+    sh      x0, 0x2(x5)
+    # Test
+    li      x12, 0x0
+    addi    x27, x5, 0
+    sh      x12, 0x2(x27)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x6, x27, test_1_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x12, 0x0)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test results
+	la	x1, test_2_res
+
+    # Clear memory
+    sh      x0, 0x4(x1)
+    # Test
+    li      x11, 0x800
+    addi    x26, x1, 0
+    sh      x11, 0x4(x26)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x26, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x800)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x10, 0x7654321
+    addi    x25, x1, 0
+    sh      x10, 0x0(x25)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x25, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7654321)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x9, 0x7fffffff
+    addi    x24, x1, 0
+    sh      x9, 0x0(x24)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x24, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7fffffff)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x8, 0x1
+    addi    x23, x1, 0
+    sh      x8, 0x0(x23)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x23, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1)
+    # Clear memory
+    sh      x0, -0x2(x1)
+    # Test
+    li      x7, 0xffffffff
+    addi    x22, x1, 0
+    sh      x7, -0x2(x22)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x22, test_2_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xffffffff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test results
+	la	x1, test_3_res
+
+    # Clear memory
+    sh      x0, 0x2(x1)
+    # Test
+    li      x6, 0x1234
+    addi    x21, x1, 0
+    sh      x6, 0x2(x21)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x21, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x6, 0x1234)
+    # Clear memory
+    sh      x0, -0x4(x1)
+    # Test
+    li      x5, 0x80000000
+    addi    x20, x1, 0
+    sh      x5, -0x4(x20)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x20, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x5, 0x80000000)
+    # Clear memory
+    sh      x0, 0x2(x1)
+    # Test
+    li      x4, -0x1234
+    addi    x19, x1, 0
+    sh      x4, 0x2(x19)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x19, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x4, -0x1234)
+    # Clear memory
+    sh      x0, 0x4(x1)
+    # Test
+    li      x3, -0x1
+    addi    x18, x1, 0
+    sh      x3, 0x4(x18)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x18, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x3, -0x1)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x2, -0x7ff
+    addi    x17, x1, 0
+    sh      x2, 0x0(x17)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x17, test_3_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x2, -0x7ff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test results
+	la	x2, test_4_res
+
+    # Clear memory
+    sh      x0, 0x0(x2)
+    # Test
+    li      x1, 0x0
+    addi    x16, x2, 0
+    sh      x1, 0x0(x16)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x16, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x1, 0x0)
+    # Clear memory
+    sh      x0, 0x0(x2)
+    # Test
+    li      x0, -0x1
+    addi    x15, x2, 0
+    sh      x0, 0x0(x15)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x15, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x0, 0)
+    # Clear memory
+    sh      x0, -0x2(x2)
+    # Test
+    li      x31, 0x1
+    addi    x14, x2, 0
+    sh      x31, -0x2(x14)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x14, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1)
+    # Clear memory
+    sh      x0, 0x2(x2)
+    # Test
+    li      x30, 0x0
+    addi    x13, x2, 0
+    sh      x30, 0x2(x13)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x13, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0)
+    # Clear memory
+    sh      x0, -0x4(x2)
+    # Test
+    li      x29, 0x7ff
+    addi    x12, x2, 0
+    sh      x29, -0x4(x12)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x12, test_4_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x29, 0x7ff)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test results
+	la	x1, test_5_res
+
+    # Clear memory
+    sh      x0, 0x2(x1)
+    # Test
+    li      x28, 0x0
+    addi    x11, x1, 0
+    sh      x28, 0x2(x11)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x11, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x0)
+    # Clear memory
+    sh      x0, 0x4(x1)
+    # Test
+    li      x27, 0x800
+    addi    x10, x1, 0
+    sh      x27, 0x4(x10)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x10, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x800)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x26, 0x7654321
+    addi    x9, x1, 0
+    sh      x26, 0x0(x9)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x9, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7654321)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x25, 0x7fffffff
+    addi    x8, x1, 0
+    sh      x25, 0x0(x8)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x8, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x7fffffff)
+    # Clear memory
+    sh      x0, 0x0(x1)
+    # Test
+    li      x24, 0x1
+    addi    x7, x1, 0
+    sh      x24, 0x0(x7)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x2, x7, test_5_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test results
+	la	x1, test_6_res
+
+    # Clear memory
+    sh      x0, -0x2(x1)
+    # Test
+    li      x23, 0xffffffff
+    addi    x6, x1, 0
+    sh      x23, -0x2(x6)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x6, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x23, 0xffffffff)
+    # Clear memory
+    sh      x0, 0x2(x1)
+    # Test
+    li      x22, 0x1234
+    addi    x5, x1, 0
+    sh      x22, 0x2(x5)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x5, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x22, 0x1234)
+    # Clear memory
+    sh      x0, -0x4(x1)
+    # Test
+    li      x21, 0x80000000
+    addi    x4, x1, 0
+    sh      x21, -0x4(x4)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x4, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x21, 0x80000000)
+    # Clear memory
+    sh      x0, 0x2(x1)
+    # Test
+    li      x20, -0x1234
+    addi    x3, x1, 0
+    sh      x20, 0x2(x3)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x3, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x20, -0x1234)
+    # Clear memory
+    sh      x0, 0x4(x1)
+    # Test
+    li      x19, -0x1
+    addi    x2, x1, 0
+    sh      x19, 0x4(x2)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x7, x2, test_6_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x19, -0x1)
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test results
+	la	x2, test_7_res
+
+    # Clear memory
+    sh      x0, 0x0(x2)
+    # Test
+    li      x18, -0x7ff
+    addi    x1, x2, 0
+    sh      x18, 0x0(x1)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x18, -0x7ff)
+    # Clear memory
+    sh      x0, 0x0(x2)
+    # Test
+    li      x17, 0x0
+    addi    x1, x2, 0
+    sh      x17, 0x0(x1)
+
+    #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0)
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+	.fill 1, 4, -1    //padding because negative offsets are used
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S
new file mode 100644
index 0000000..ab88d62
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLL-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLL'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(sll, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(sll, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(sll, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(sll, x3, x28, x13, 0x7ff0, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(sll, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(sll, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(sll, x6, x25, x10, 0x43210000, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(sll, x7, x24, x9, 0xfffffffe, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(sll, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(sll, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(sll, x10, x21, x6, 0x2468, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(sll, x11, x20, x5, 0x0, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(sll, x12, x19, x4, 0xffedcc00, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(sll, x13, x18, x3, 0x80000000, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(sll, x14, x17, x2, 0xf8010000, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(sll, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(sll, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(sll, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(sll, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(sll, x19, x12, x29, 0x7ff0, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(sll, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(sll, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(sll, x22, x9, x26, 0x43210000, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(sll, x23, x8, x25, 0xfffffffe, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(sll, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(sll, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(sll, x26, x5, x22, 0x2468, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(sll, x27, x4, x21, 0x0, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(sll, x28, x3, x20, 0xffedcc00, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(sll, x29, x2, x19, 0x80000000, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(sll, x30, x1, x18, 0xf8010000, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(sll, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S
new file mode 100644
index 0000000..75128a5
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLLI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLLI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(slli, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(slli, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(slli, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(slli, x3, x28, 0x7ff0, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(slli, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(slli, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(slli, x6, x25, 0x43210000, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(slli, x7, x24, 0xfffffffe, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(slli, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(slli, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(slli, x10, x21, 0x2468, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(slli, x11, x20, 0x0, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(slli, x12, x19, 0xffedcc00, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(slli, x13, x18, 0x80000000, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(slli, x14, x17, 0xf8010000, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(slli, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(slli, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(slli, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(slli, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(slli, x19, x12, 0x7ff0, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(slli, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(slli, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(slli, x22, x9, 0x43210000, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(slli, x23, x8, 0xfffffffe, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(slli, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(slli, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(slli, x26, x5, 0x2468, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(slli, x27, x4, 0x0, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(slli, x28, x3, 0xffedcc00, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(slli, x29, x2, 0x80000000, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(slli, x30, x1, 0xf8010000, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(slli, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S
new file mode 100644
index 0000000..e76faff
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLT-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLT'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(slt, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(slt, x1, x30, x15, 0x0, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(slt, x2, x29, x14, 0x0, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(slt, x3, x28, x13, 0x0, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(slt, x4, x27, x12, 0x0, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(slt, x5, x26, x11, 0x1, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(slt, x6, x25, x10, 0x0, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(slt, x7, x24, x9, 0x0, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(slt, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(slt, x9, x22, x7, 0x1, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(slt, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(slt, x11, x20, x5, 0x1, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(slt, x12, x19, x4, 0x1, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(slt, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(slt, x14, x17, x2, 0x1, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(slt, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(slt, x16, x15, x0, 0x1, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(slt, x17, x14, x31, 0x0, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(slt, x18, x13, x30, 0x0, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(slt, x19, x12, x29, 0x0, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(slt, x20, x11, x28, 0x0, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(slt, x21, x10, x27, 0x1, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(slt, x22, x9, x26, 0x0, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(slt, x23, x8, x25, 0x0, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(slt, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(slt, x25, x6, x23, 0x1, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(slt, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(slt, x27, x4, x21, 0x1, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(slt, x28, x3, x20, 0x1, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(slt, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(slt, x30, x1, x18, 0x1, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(slt, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S
new file mode 100644
index 0000000..67740af
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLTI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLTI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(slti, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(slti, x1, x30, 0x0, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(slti, x2, x29, 0x0, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(slti, x3, x28, 0x0, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(slti, x4, x27, 0x0, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(slti, x5, x26, 0x0, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(slti, x6, x25, 0x0, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(slti, x7, x24, 0x0, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(slti, x8, x23, 0x0, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(slti, x9, x22, 0x0, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(slti, x10, x21, 0x0, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(slti, x11, x20, 0x1, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(slti, x12, x19, 0x1, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(slti, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(slti, x14, x17, 0x1, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(slti, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(slti, x16, x15, 0x1, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(slti, x17, x14, 0x0, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(slti, x18, x13, 0x0, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(slti, x19, x12, 0x0, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(slti, x20, x11, 0x0, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(slti, x21, x10, 0x0, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(slti, x22, x9, 0x0, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(slti, x23, x8, 0x0, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(slti, x24, x7, 0x0, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(slti, x25, x6, 0x0, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(slti, x26, x5, 0x0, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(slti, x27, x4, 0x1, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(slti, x28, x3, 0x1, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(slti, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(slti, x30, x1, 0x1, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(slti, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S
new file mode 100644
index 0000000..e55c176
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLTIU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLTIU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(sltiu, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(sltiu, x1, x30, 0x1, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(sltiu, x2, x29, 0x1, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(sltiu, x3, x28, 0x1, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(sltiu, x4, x27, 0x1, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(sltiu, x5, x26, 0x1, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(sltiu, x6, x25, 0x1, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(sltiu, x7, x24, 0x0, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(sltiu, x8, x23, 0x1, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(sltiu, x9, x22, 0x0, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(sltiu, x10, x21, 0x1, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(sltiu, x11, x20, 0x0, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(sltiu, x12, x19, 0x0, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(sltiu, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(sltiu, x14, x17, 0x0, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(sltiu, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(sltiu, x16, x15, 0x0, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(sltiu, x17, x14, 0x1, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(sltiu, x18, x13, 0x1, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(sltiu, x19, x12, 0x1, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(sltiu, x20, x11, 0x1, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(sltiu, x21, x10, 0x1, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(sltiu, x22, x9, 0x1, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(sltiu, x23, x8, 0x0, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(sltiu, x24, x7, 0x1, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(sltiu, x25, x6, 0x0, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(sltiu, x26, x5, 0x1, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(sltiu, x27, x4, 0x0, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(sltiu, x28, x3, 0x0, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(sltiu, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(sltiu, x30, x1, 0x0, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(sltiu, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S
new file mode 100644
index 0000000..b57a894
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SLTU-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SLTU'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(sltu, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(sltu, x1, x30, x15, 0x1, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(sltu, x2, x29, x14, 0x1, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(sltu, x3, x28, x13, 0x1, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(sltu, x4, x27, x12, 0x1, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(sltu, x5, x26, x11, 0x1, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(sltu, x6, x25, x10, 0x1, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(sltu, x7, x24, x9, 0x0, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(sltu, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(sltu, x9, x22, x7, 0x0, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(sltu, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(sltu, x11, x20, x5, 0x0, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(sltu, x12, x19, x4, 0x0, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(sltu, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(sltu, x14, x17, x2, 0x0, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(sltu, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(sltu, x16, x15, x0, 0x0, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(sltu, x17, x14, x31, 0x1, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(sltu, x18, x13, x30, 0x1, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(sltu, x19, x12, x29, 0x1, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(sltu, x20, x11, x28, 0x1, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(sltu, x21, x10, x27, 0x1, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(sltu, x22, x9, x26, 0x1, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(sltu, x23, x8, x25, 0x0, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(sltu, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(sltu, x25, x6, x23, 0x0, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(sltu, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(sltu, x27, x4, x21, 0x0, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(sltu, x28, x3, x20, 0x0, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(sltu, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(sltu, x30, x1, x18, 0x0, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(sltu, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S
new file mode 100644
index 0000000..30f6ae0
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SRA-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SRA'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(sra, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(sra, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(sra, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(sra, x3, x28, x13, 0x7f, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(sra, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(sra, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(sra, x6, x25, x10, 0x765, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(sra, x7, x24, x9, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(sra, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(sra, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(sra, x10, x21, x6, 0x91a, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(sra, x11, x20, x5, 0xf8000000, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(sra, x12, x19, x4, 0xffffffed, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(sra, x13, x18, x3, 0xffffffff, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(sra, x14, x17, x2, 0xffffffff, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(sra, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(sra, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(sra, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(sra, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(sra, x19, x12, x29, 0x7f, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(sra, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(sra, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(sra, x22, x9, x26, 0x765, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(sra, x23, x8, x25, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(sra, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(sra, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(sra, x26, x5, x22, 0x91a, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(sra, x27, x4, x21, 0xf8000000, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(sra, x28, x3, x20, 0xffffffed, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(sra, x29, x2, x19, 0xffffffff, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(sra, x30, x1, x18, 0xffffffff, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(sra, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S
new file mode 100644
index 0000000..d83222b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SRAI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SRAI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(srai, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(srai, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(srai, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(srai, x3, x28, 0x7f, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(srai, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(srai, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(srai, x6, x25, 0x765, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(srai, x7, x24, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(srai, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(srai, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(srai, x10, x21, 0x91a, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(srai, x11, x20, 0xf8000000, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(srai, x12, x19, 0xffffffed, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(srai, x13, x18, 0xffffffff, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(srai, x14, x17, 0xffffffff, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(srai, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(srai, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(srai, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(srai, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(srai, x19, x12, 0x7f, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(srai, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(srai, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(srai, x22, x9, 0x765, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(srai, x23, x8, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(srai, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(srai, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(srai, x26, x5, 0x91a, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(srai, x27, x4, 0xf8000000, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(srai, x28, x3, 0xffffffed, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(srai, x29, x2, 0xffffffff, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(srai, x30, x1, 0xffffffff, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(srai, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S
new file mode 100644
index 0000000..9cd51ae
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SRL-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SRL'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(srl, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(srl, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(srl, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(srl, x3, x28, x13, 0x7f, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(srl, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(srl, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(srl, x6, x25, x10, 0x765, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(srl, x7, x24, x9, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(srl, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(srl, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(srl, x10, x21, x6, 0x91a, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(srl, x11, x20, x5, 0x8000000, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(srl, x12, x19, x4, 0xffffed, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(srl, x13, x18, x3, 0x1, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(srl, x14, x17, x2, 0xffff, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(srl, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(srl, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(srl, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(srl, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(srl, x19, x12, x29, 0x7f, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(srl, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(srl, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(srl, x22, x9, x26, 0x765, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(srl, x23, x8, x25, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(srl, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(srl, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(srl, x26, x5, x22, 0x91a, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(srl, x27, x4, x21, 0x8000000, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(srl, x28, x3, x20, 0xffffed, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(srl, x29, x2, x19, 0x1, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(srl, x30, x1, x18, 0xffff, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(srl, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S
new file mode 100644
index 0000000..8012626
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SRLI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SRLI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(srli, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(srli, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(srli, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(srli, x3, x28, 0x7f, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(srli, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(srli, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(srli, x6, x25, 0x765, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(srli, x7, x24, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(srli, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(srli, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(srli, x10, x21, 0x91a, 0x1234, 0x1, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(srli, x11, x20, 0x8000000, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(srli, x12, x19, 0xffffed, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(srli, x13, x18, 0x1, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(srli, x14, x17, 0xffff, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(srli, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(srli, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(srli, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(srli, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(srli, x19, x12, 0x7f, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(srli, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(srli, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(srli, x22, x9, 0x765, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(srli, x23, x8, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(srli, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(srli, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(srli, x26, x5, 0x91a, 0x1234, 0x1, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(srli, x27, x4, 0x8000000, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(srli, x28, x3, 0xffffed, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(srli, x29, x2, 0x1, -0x1, 0x1f, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(srli, x30, x1, 0xffff, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(srli, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S
new file mode 100644
index 0000000..be59eb4
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test SUB-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SUB'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(sub, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(sub, x1, x30, x15, 0x800, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(sub, x2, x29, x14, 0x1, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(sub, x3, x28, x13, 0x1a33, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(sub, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(sub, x5, x26, x11, 0xfffff5cc, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(sub, x6, x25, x10, 0x7654322, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(sub, x7, x24, x9, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(sub, x8, x23, x8, 0x80000002, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(sub, x9, x22, x7, 0xf89abcde, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(sub, x10, x21, x6, 0xa34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(sub, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(sub, x12, x19, x4, 0xffffe5cd, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(sub, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(sub, x14, x17, x2, 0xfffff800, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(sub, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(sub, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(sub, x17, x14, x31, 0x800, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(sub, x18, x13, x30, 0x1, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(sub, x19, x12, x29, 0x1a33, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(sub, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(sub, x21, x10, x27, 0xfffff5cc, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(sub, x22, x9, x26, 0x7654322, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(sub, x23, x8, x25, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(sub, x24, x7, x24, 0x80000002, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(sub, x25, x6, x23, 0xf89abcde, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(sub, x26, x5, x22, 0xa34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(sub, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(sub, x28, x3, x20, 0xffffe5cd, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(sub, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(sub, x30, x1, x18, 0xfffff800, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(sub, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S
new file mode 100644
index 0000000..afabbb7
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S
@@ -0,0 +1,519 @@
+# RISC-V Compliance Test I-SW-01
+#
+#
+# Copyright (c) 2019 Imperas Software Ltd., www.imperas.com
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied.
+#
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'SW'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # Addresses for test results
+	la	x5, test_1_res
+
+    # Clear memory
+    sw      x0, 0(x5)
+    # Load values and compute offsets
+    li      x16, -0x1
+    addi    x31, x5,0
+    addi    x31, x31, 0x7d0
+    # Test Instruction 
+    sw      x16, -0x7d0(x31)
+    # Check results:  mem[test_1_res+0] = -0x1
+    lw x7, 0(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x7, -0x1)
+
+    # Clear memory
+    sw      x0, 4(x5)
+    # Load values and compute offsets
+    li      x15, 0x1
+    addi    x30, x5,4
+    addi    x30, x30, 0x0
+    # Test Instruction 
+    sw      x15, 0x0(x30)
+    # Check results:  mem[test_1_res+4] = 0x1
+    lw x7, 4(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x1)
+
+    # Clear memory
+    sw      x0, 8(x5)
+    # Load values and compute offsets
+    li      x14, 0x0
+    addi    x29, x5,8
+    addi    x29, x29, 0x1
+    # Test Instruction 
+    sw      x14, -0x1(x29)
+    # Check results:  mem[test_1_res+8] = 0x0
+    lw x7, 8(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x0)
+
+    # Clear memory
+    sw      x0, 12(x5)
+    # Load values and compute offsets
+    li      x13, 0x7ff
+    addi    x28, x5,12
+    addi    x28, x28, 0x7d0
+    # Test Instruction 
+    sw      x13, -0x7d0(x28)
+    # Check results:  mem[test_1_res+12] = 0x7ff
+    lw x7, 12(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x7ff)
+
+    # Clear memory
+    sw      x0, 16(x5)
+    # Load values and compute offsets
+    li      x12, 0x0
+    addi    x27, x5,16
+    addi    x27, x27, -0x7d0
+    # Test Instruction 
+    sw      x12, 0x7d0(x27)
+    # Check results:  mem[test_1_res+16] = 0x0
+    lw x7, 16(x5)
+    RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x0)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # Addresses for test results
+	la	x1, test_2_res
+
+    # Clear memory
+    sw      x0, 0(x1)
+    # Load values and compute offsets
+    li      x11, 0x800
+    addi    x26, x1,0
+    addi    x26, x26, -0x7d0
+    # Test Instruction 
+    sw      x11, 0x7d0(x26)
+    # Check results:  mem[test_2_res+0] = 0x800
+    lw x3, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x800)
+
+    # Clear memory
+    sw      x0, 4(x1)
+    # Load values and compute offsets
+    li      x10, 0x7654321
+    addi    x25, x1,4
+    addi    x25, x25, -0x7d0
+    # Test Instruction 
+    sw      x10, 0x7d0(x25)
+    # Check results:  mem[test_2_res+4] = 0x7654321
+    lw x3, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7654321)
+
+    # Clear memory
+    sw      x0, 8(x1)
+    # Load values and compute offsets
+    li      x9, 0x7fffffff
+    addi    x24, x1,8
+    addi    x24, x24, -0x1
+    # Test Instruction 
+    sw      x9, 0x1(x24)
+    # Check results:  mem[test_2_res+8] = 0x7fffffff
+    lw x3, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7fffffff)
+
+    # Clear memory
+    sw      x0, 12(x1)
+    # Load values and compute offsets
+    li      x8, 0x1
+    addi    x23, x1,12
+    addi    x23, x23, -0x7d0
+    # Test Instruction 
+    sw      x8, 0x7d0(x23)
+    # Check results:  mem[test_2_res+12] = 0x1
+    lw x3, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x1)
+
+    # Clear memory
+    sw      x0, 16(x1)
+    # Load values and compute offsets
+    li      x7, 0xffffffff
+    addi    x22, x1,16
+    addi    x22, x22, -0x7d0
+    # Test Instruction 
+    sw      x7, 0x7d0(x22)
+    # Check results:  mem[test_2_res+16] = 0xffffffff
+    lw x3, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0xffffffff)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # Addresses for test results
+	la	x1, test_3_res
+
+    # Clear memory
+    sw      x0, 0(x1)
+    # Load values and compute offsets
+    li      x6, 0x1234
+    addi    x21, x1,0
+    addi    x21, x21, -0x7d0
+    # Test Instruction 
+    sw      x6, 0x7d0(x21)
+    # Check results:  mem[test_3_res+0] = 0x1234
+    lw x8, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x1234)
+
+    # Clear memory
+    sw      x0, 4(x1)
+    # Load values and compute offsets
+    li      x5, 0x80000000
+    addi    x20, x1,4
+    addi    x20, x20, 0x0
+    # Test Instruction 
+    sw      x5, 0x0(x20)
+    # Check results:  mem[test_3_res+4] = 0x80000000
+    lw x8, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x80000000)
+
+    # Clear memory
+    sw      x0, 8(x1)
+    # Load values and compute offsets
+    li      x4, -0x1234
+    addi    x19, x1,8
+    addi    x19, x19, -0x7d0
+    # Test Instruction 
+    sw      x4, 0x7d0(x19)
+    # Check results:  mem[test_3_res+8] = -0x1234
+    lw x8, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1234)
+
+    # Clear memory
+    sw      x0, 12(x1)
+    # Load values and compute offsets
+    li      x3, -0x1
+    addi    x18, x1,12
+    addi    x18, x18, 0x1
+    # Test Instruction 
+    sw      x3, -0x1(x18)
+    # Check results:  mem[test_3_res+12] = -0x1
+    lw x8, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1)
+
+    # Clear memory
+    sw      x0, 16(x1)
+    # Load values and compute offsets
+    li      x2, -0x7ff
+    addi    x17, x1,16
+    addi    x17, x17, 0x0
+    # Test Instruction 
+    sw      x2, 0x0(x17)
+    # Check results:  mem[test_3_res+16] = -0x7ff
+    lw x8, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x7ff)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # Addresses for test results
+	la	x2, test_4_res
+
+    # Clear memory
+    sw      x0, 0(x2)
+    # Load values and compute offsets
+    li      x1, -0x2
+    addi    x16, x2,0
+    addi    x16, x16, -0x1
+    # Test Instruction 
+    sw      x1, 0x1(x16)
+    # Check results:  mem[test_4_res+0] = -0x2
+    lw x4, 0(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x2)
+
+    # Clear memory
+    sw      x0, 4(x2)
+    # Load values and compute offsets
+    li      x0, -0x1
+    addi    x15, x2,4
+    addi    x15, x15, 0x7d0
+    # Test Instruction 
+    sw      x0, -0x7d0(x15)
+    # Check results:  mem[test_4_res+4] = 0
+    lw x4, 4(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0)
+
+    # Clear memory
+    sw      x0, 8(x2)
+    # Load values and compute offsets
+    li      x31, 0x1
+    addi    x14, x2,8
+    addi    x14, x14, 0x0
+    # Test Instruction 
+    sw      x31, 0x0(x14)
+    # Check results:  mem[test_4_res+8] = 0x1
+    lw x4, 8(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x1)
+
+    # Clear memory
+    sw      x0, 12(x2)
+    # Load values and compute offsets
+    li      x30, 0x0
+    addi    x13, x2,12
+    addi    x13, x13, 0x1
+    # Test Instruction 
+    sw      x30, -0x1(x13)
+    # Check results:  mem[test_4_res+12] = 0x0
+    lw x4, 12(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x0)
+
+    # Clear memory
+    sw      x0, 16(x2)
+    # Load values and compute offsets
+    li      x29, 0x7ff
+    addi    x12, x2,16
+    addi    x12, x12, 0x7d0
+    # Test Instruction 
+    sw      x29, -0x7d0(x12)
+    # Check results:  mem[test_4_res+16] = 0x7ff
+    lw x4, 16(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x7ff)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # Addresses for test results
+	la	x1, test_5_res
+
+    # Clear memory
+    sw      x0, 0(x1)
+    # Load values and compute offsets
+    li      x28, 0x0
+    addi    x11, x1,0
+    addi    x11, x11, -0x7d0
+    # Test Instruction 
+    sw      x28, 0x7d0(x11)
+    # Check results:  mem[test_5_res+0] = 0x0
+    lw x3, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x0)
+
+    # Clear memory
+    sw      x0, 4(x1)
+    # Load values and compute offsets
+    li      x27, 0x800
+    addi    x10, x1,4
+    addi    x10, x10, -0x7d0
+    # Test Instruction 
+    sw      x27, 0x7d0(x10)
+    # Check results:  mem[test_5_res+4] = 0x800
+    lw x3, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x800)
+
+    # Clear memory
+    sw      x0, 8(x1)
+    # Load values and compute offsets
+    li      x26, 0x7654321
+    addi    x9, x1,8
+    addi    x9, x9, -0x7d0
+    # Test Instruction 
+    sw      x26, 0x7d0(x9)
+    # Check results:  mem[test_5_res+8] = 0x7654321
+    lw x3, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7654321)
+
+    # Clear memory
+    sw      x0, 12(x1)
+    # Load values and compute offsets
+    li      x25, 0x7fffffff
+    addi    x8, x1,12
+    addi    x8, x8, -0x1
+    # Test Instruction 
+    sw      x25, 0x1(x8)
+    # Check results:  mem[test_5_res+12] = 0x7fffffff
+    lw x3, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7fffffff)
+
+    # Clear memory
+    sw      x0, 16(x1)
+    # Load values and compute offsets
+    li      x24, 0x1
+    addi    x7, x1,16
+    addi    x7, x7, -0x7d0
+    # Test Instruction 
+    sw      x24, 0x7d0(x7)
+    # Check results:  mem[test_5_res+16] = 0x1
+    lw x3, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x1)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # Addresses for test results
+	la	x1, test_6_res
+
+    # Clear memory
+    sw      x0, 0(x1)
+    # Load values and compute offsets
+    li      x23, 0xffffffff
+    addi    x6, x1,0
+    addi    x6, x6, -0x7d0
+    # Test Instruction 
+    sw      x23, 0x7d0(x6)
+    # Check results:  mem[test_6_res+0] = 0xffffffff
+    lw x8, 0(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0xffffffff)
+
+    # Clear memory
+    sw      x0, 4(x1)
+    # Load values and compute offsets
+    li      x22, 0x1234
+    addi    x5, x1,4
+    addi    x5, x5, -0x7d0
+    # Test Instruction 
+    sw      x22, 0x7d0(x5)
+    # Check results:  mem[test_6_res+4] = 0x1234
+    lw x8, 4(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x1234)
+
+    # Clear memory
+    sw      x0, 8(x1)
+    # Load values and compute offsets
+    li      x21, 0x80000000
+    addi    x4, x1,8
+    addi    x4, x4, 0x0
+    # Test Instruction 
+    sw      x21, 0x0(x4)
+    # Check results:  mem[test_6_res+8] = 0x80000000
+    lw x8, 8(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x80000000)
+
+    # Clear memory
+    sw      x0, 12(x1)
+    # Load values and compute offsets
+    li      x20, -0x1234
+    addi    x3, x1,12
+    addi    x3, x3, -0x7d0
+    # Test Instruction 
+    sw      x20, 0x7d0(x3)
+    # Check results:  mem[test_6_res+12] = -0x1234
+    lw x8, 12(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1234)
+
+    # Clear memory
+    sw      x0, 16(x1)
+    # Load values and compute offsets
+    li      x19, -0x1
+    addi    x2, x1,16
+    addi    x2, x2, 0x1
+    # Test Instruction 
+    sw      x19, -0x1(x2)
+    # Check results:  mem[test_6_res+16] = -0x1
+    lw x8, 16(x1)
+    RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # Addresses for test results
+	la	x2, test_7_res
+
+    # Clear memory
+    sw      x0, 0(x2)
+    # Load values and compute offsets
+    li      x18, -0x7ff
+    addi    x1, x2,0
+    addi    x1, x1, 0x0
+    # Test Instruction 
+    sw      x18, 0x0(x1)
+    # Check results:  mem[test_7_res+0] = -0x7ff
+    lw x4, 0(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x7ff)
+
+    # Clear memory
+    sw      x0, 4(x2)
+    # Load values and compute offsets
+    li      x17, -0x2
+    addi    x1, x2,4
+    addi    x1, x1, -0x1
+    # Test Instruction 
+    sw      x17, 0x1(x1)
+    # Check results:  mem[test_7_res+4] = -0x2
+    lw x4, 4(x2)
+    RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x2)
+
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S
new file mode 100644
index 0000000..af35340
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test XOR-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'XOR'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_RR_OP(xor, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_RR_OP(xor, x1, x30, x15, 0xfffff800, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_RR_OP(xor, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_RR_OP(xor, x3, x28, x13, 0xffffea33, 0x7ff, -0x1234, x5, 12, x6)   # Testcase 3
+	TEST_RR_OP(xor, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_RR_OP(xor, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2)   # Testcase 5
+	TEST_RR_OP(xor, x6, x25, x10, 0xf89abcde, 0x7654321, 0xffffffff, x1, 4, x2)   # Testcase 6
+	TEST_RR_OP(xor, x7, x24, x9, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_RR_OP(xor, x8, x23, x8, 0x7ffffffe, 0x1, 0x7fffffff, x1, 12, x2)   # Testcase 8
+	TEST_RR_OP(xor, x9, x22, x7, 0xf89abcde, 0xffffffff, 0x7654321, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_RR_OP(xor, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_RR_OP(xor, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_RR_OP(xor, x12, x19, x4, 0xffffea33, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_RR_OP(xor, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_RR_OP(xor, x14, x17, x2, 0xfffff800, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_RR_OP(xor, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_RR_OP(xor, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_RR_OP(xor, x17, x14, x31, 0xfffff800, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_RR_OP(xor, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_RR_OP(xor, x19, x12, x29, 0xffffea33, 0x7ff, -0x1234, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_RR_OP(xor, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2)   # Testcase 20
+	TEST_RR_OP(xor, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2)   # Testcase 21
+	TEST_RR_OP(xor, x22, x9, x26, 0xf89abcde, 0x7654321, 0xffffffff, x1, 8, x2)   # Testcase 22
+	TEST_RR_OP(xor, x23, x8, x25, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_RR_OP(xor, x24, x7, x24, 0x7ffffffe, 0x1, 0x7fffffff, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_RR_OP(xor, x25, x6, x23, 0xf89abcde, 0xffffffff, 0x7654321, x1, 0, x7)   # Testcase 25
+	TEST_RR_OP(xor, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_RR_OP(xor, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_RR_OP(xor, x28, x3, x20, 0xffffea33, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_RR_OP(xor, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_RR_OP(xor, x30, x1, x18, 0xfffff800, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_RR_OP(xor, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S
new file mode 100644
index 0000000..7137385
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S
@@ -0,0 +1,172 @@
+# RISC-V Compliance Test XORI-01
+#
+# Copyright (c) 2019, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32I Base Integer Instruction Set, Version 2.1
+# Description: Testing instruction 'XORI'.
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
+
+
+    # address for test results
+	la	x5, test_1_res
+
+	TEST_IMM_OP(xori, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
+	TEST_IMM_OP(xori, x1, x30, 0xfffff800, 0x1, -0x7ff, x5, 4, x6)   # Testcase 1
+	TEST_IMM_OP(xori, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6)   # Testcase 2
+	TEST_IMM_OP(xori, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6)   # Testcase 3
+	TEST_IMM_OP(xori, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6)   # Testcase 4
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
+
+
+    # address for test results
+	la	x1, test_2_res
+
+	TEST_IMM_OP(xori, x5, x26, 0xfffff000, 0x800, 0x800, x1, 0, x2)   # Testcase 5
+	TEST_IMM_OP(xori, x6, x25, 0xf89abb21, 0x7654321, 0x800, x1, 4, x2)   # Testcase 6
+	TEST_IMM_OP(xori, x7, x24, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2)   # Testcase 7
+	TEST_IMM_OP(xori, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2)   # Testcase 8
+	TEST_IMM_OP(xori, x9, x22, 0x7ff, 0xffffffff, 0x800, x1, 16, x2)   # Testcase 9
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
+
+
+    # address for test results
+	la	x1, test_3_res
+
+	TEST_IMM_OP(xori, x10, x21, 0xffffea34, 0x1234, 0x800, x1, 0, x7)   # Testcase 10
+	TEST_IMM_OP(xori, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7)   # Testcase 11
+	TEST_IMM_OP(xori, x12, x19, 0xffffea33, -0x1234, 0x7ff, x1, 8, x7)   # Testcase 12
+	TEST_IMM_OP(xori, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7)   # Testcase 13
+	TEST_IMM_OP(xori, x14, x17, 0xfffff800, -0x7ff, 0x1, x1, 16, x7)   # Testcase 14
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
+
+
+    # address for test results
+	la	x2, test_4_res
+
+	TEST_IMM_OP(xori, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3)   # Testcase 15
+	TEST_IMM_OP(xori, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
+	TEST_IMM_OP(xori, x17, x14, 0xfffff800, 0x1, -0x7ff, x2, 8, x3)   # Testcase 17
+	TEST_IMM_OP(xori, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3)   # Testcase 18
+	TEST_IMM_OP(xori, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3)   # Testcase 19
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
+
+
+    # address for test results
+	la	x1, test_5_res
+
+	TEST_IMM_OP(xori, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2)   # Testcase 20
+	TEST_IMM_OP(xori, x21, x10, 0xfffff000, 0x800, 0x800, x1, 4, x2)   # Testcase 21
+	TEST_IMM_OP(xori, x22, x9, 0xf89abb21, 0x7654321, 0x800, x1, 8, x2)   # Testcase 22
+	TEST_IMM_OP(xori, x23, x8, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2)   # Testcase 23
+	TEST_IMM_OP(xori, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2)   # Testcase 24
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
+
+
+    # address for test results
+	la	x1, test_6_res
+
+	TEST_IMM_OP(xori, x25, x6, 0x7ff, 0xffffffff, 0x800, x1, 0, x7)   # Testcase 25
+	TEST_IMM_OP(xori, x26, x5, 0xffffea34, 0x1234, 0x800, x1, 4, x7)   # Testcase 26
+	TEST_IMM_OP(xori, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7)   # Testcase 27
+	TEST_IMM_OP(xori, x28, x3, 0xffffea33, -0x1234, 0x7ff, x1, 12, x7)   # Testcase 28
+	TEST_IMM_OP(xori, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7)   # Testcase 29
+
+
+	# ---------------------------------------------------------------------------------------------
+	RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
+
+
+    # address for test results
+	la	x2, test_7_res
+
+	TEST_IMM_OP(xori, x30, x1, 0xfffff800, -0x7ff, 0x1, x2, 0, x3)   # Testcase 30
+	TEST_IMM_OP(xori, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3)   # Testcase 31
+
+
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
+
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/.gitignore b/tests/riscv-compliance/riscv-test-suite/rv32im/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/Makefile b/tests/riscv-compliance/riscv-test-suite/rv32im/Makefile
new file mode 100644
index 0000000..8782fbe
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/Makefile
@@ -0,0 +1,59 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+act_dir := .
+src_dir := $(act_dir)/src
+work_dir := $(ROOTDIR)/build_generated
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
+
+include $(act_dir)/Makefrag
+ifneq ($(RISCV_TEST),)
+    target_tests = $(RISCV_TEST).elf
+endif
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+vpath %.S $(act_dir)
+
+INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include
+ifeq ($(wildcard $(INCLUDE)),)
+    $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
+endif
+-include $(INCLUDE)
+
+#------------------------------------------------------------
+# Build and run assembly tests
+
+%.log: %.elf
+	$(V) echo "Execute $(@)"
+	#$(V) $(RUN_TARGET)
+
+
+define compile_template
+
+$(work_dir_isa)/%.elf: $(src_dir)/%.S
+	$(V) echo "Compile $$(@)"
+	@mkdir -p $$(@D)
+	$(V) $(COMPILE_TARGET)
+
+.PRECIOUS: $(work_dir_isa)/%.elf
+
+endef
+
+$(eval $(call compile_template,-march=rv32im -mabi=ilp32))
+
+target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
+target_log = $(patsubst %.elf,%.log,$(target_elf))
+
+run: $(target_log)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(work_dir_isa)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/Makefrag b/tests/riscv-compliance/riscv-test-suite/rv32im/Makefrag
new file mode 100644
index 0000000..0a5ce44
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/Makefrag
@@ -0,0 +1,46 @@
+# RISC-V Compliance Test RV32IM Makefrag
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32IM compliance tests
+
+rv32im_sc_tests = \
+    MULHU \
+    MULH \
+    MULHSU \
+    DIV \
+    REM \
+    REMU \
+    MUL \
+    DIVU \
+    REMU \
+
+xx_rv32im_sc_tests = \
+	DIV \
+
+rv32im_tests = $(addsuffix .elf, $(rv32im_sc_tests))
+
+target_tests += $(rv32im_tests)
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/report.txt b/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/report.txt
new file mode 100644
index 0000000..d4dc572
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/report.txt
@@ -0,0 +1,1149 @@
+This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv
+
+COVERGROUP COVERAGE:
+----------------------------------------------------------------------------------------------------------
+Covergroup                                             Metric       Goal    Status               
+                                                                                                         
+----------------------------------------------------------------------------------------------------------
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/mul_cg 
+                                                       89.28%        100    Uncovered            
+    covered/total bins:                                    82        106                      
+    missing/total bins:                                    24        106                      
+    % Hit:                                             77.35%        100                      
+    Coverpoint mul_cg::cp_rs1                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mul_cg::cp_rs2                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mul_cg::cp_rd                           75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mul_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mul_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mul_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Cross mul_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulh_cg 
+                                                       89.28%        100    Uncovered            
+    covered/total bins:                                    82        106                      
+    missing/total bins:                                    24        106                      
+    % Hit:                                             77.35%        100                      
+    Coverpoint mulh_cg::cp_rs1                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulh_cg::cp_rs2                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulh_cg::cp_rd                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulh_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulh_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulh_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 17          1    Covered              
+        bin auto[NEGATIVE]                                  8          1    Covered              
+    Cross mulh_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulhsu_cg 
+                                                       89.28%        100    Uncovered            
+    covered/total bins:                                    82        106                      
+    missing/total bins:                                    24        106                      
+    % Hit:                                             77.35%        100                      
+    Coverpoint mulhsu_cg::cp_rs1                       75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhsu_cg::cp_rs2                       75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhsu_cg::cp_rd                        75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhsu_cg::cp_rs1_sign                 100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulhsu_cg::cp_rs2_sign                 100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulhsu_cg::cp_rd_sign                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 17          1    Covered              
+        bin auto[NEGATIVE]                                  8          1    Covered              
+    Cross mulhsu_cg::cp_sign_cross                    100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulhu_cg 
+                                                       89.28%        100    Uncovered            
+    covered/total bins:                                    82        106                      
+    missing/total bins:                                    24        106                      
+    % Hit:                                             77.35%        100                      
+    Coverpoint mulhu_cg::cp_rs1                        75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhu_cg::cp_rs2                        75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhu_cg::cp_rd                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint mulhu_cg::cp_rs1_sign                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulhu_cg::cp_rs2_sign                  100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint mulhu_cg::cp_rd_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 24          1    Covered              
+        bin auto[NEGATIVE]                                  1          1    Covered              
+    Cross mulhu_cg::cp_sign_cross                     100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/div_cg 
+                                                       90.62%        100    Uncovered            
+    covered/total bins:                                    85        109                      
+    missing/total bins:                                    24        109                      
+    % Hit:                                             77.98%        100                      
+    Coverpoint div_cg::cp_rs1                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint div_cg::cp_rs2                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint div_cg::cp_rd                           75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint div_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint div_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint div_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 14          1    Covered              
+        bin auto[NEGATIVE]                                 11          1    Covered              
+    Coverpoint div_cg::cp_div_result                  100.00%        100    Covered              
+        covered/total bins:                                 3          3                      
+        missing/total bins:                                 0          3                      
+        % Hit:                                        100.00%        100                      
+        bin auto[DIV_NORMAL]                               19          1    Covered              
+        bin auto[DIV_BY_ZERO]                               5          1    Covered              
+        bin auto[DIV_OVERFLOW]                              1          1    Covered              
+    Cross div_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/divu_cg 
+                                                       90.62%        100    Uncovered            
+    covered/total bins:                                    85        109                      
+    missing/total bins:                                    24        109                      
+    % Hit:                                             77.98%        100                      
+    Coverpoint divu_cg::cp_rs1                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint divu_cg::cp_rs2                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint divu_cg::cp_rd                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint divu_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint divu_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint divu_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 18          1    Covered              
+        bin auto[NEGATIVE]                                  7          1    Covered              
+    Coverpoint divu_cg::cp_div_result                 100.00%        100    Covered              
+        covered/total bins:                                 3          3                      
+        missing/total bins:                                 0          3                      
+        % Hit:                                        100.00%        100                      
+        bin auto[DIV_NORMAL]                               19          1    Covered              
+        bin auto[DIV_BY_ZERO]                               5          1    Covered              
+        bin auto[DIV_OVERFLOW]                              1          1    Covered              
+    Cross divu_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/rem_cg 
+                                                       90.62%        100    Uncovered            
+    covered/total bins:                                    85        109                      
+    missing/total bins:                                    24        109                      
+    % Hit:                                             77.98%        100                      
+    Coverpoint rem_cg::cp_rs1                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint rem_cg::cp_rs2                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint rem_cg::cp_rd                           75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint rem_cg::cp_rs1_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint rem_cg::cp_rs2_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint rem_cg::cp_rd_sign                     100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 20          1    Covered              
+        bin auto[NEGATIVE]                                  5          1    Covered              
+    Coverpoint rem_cg::cp_div_result                  100.00%        100    Covered              
+        covered/total bins:                                 3          3                      
+        missing/total bins:                                 0          3                      
+        % Hit:                                        100.00%        100                      
+        bin auto[DIV_NORMAL]                               19          1    Covered              
+        bin auto[DIV_BY_ZERO]                               5          1    Covered              
+        bin auto[DIV_OVERFLOW]                              1          1    Covered              
+    Cross rem_cg::cp_sign_cross                       100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+ TYPE /riscv_instr_pkg/riscv_instr_cover_group/remu_cg 
+                                                       90.62%        100    Uncovered            
+    covered/total bins:                                    85        109                      
+    missing/total bins:                                    24        109                      
+    % Hit:                                             77.98%        100                      
+    Coverpoint remu_cg::cp_rs1                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint remu_cg::cp_rs2                         75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint remu_cg::cp_rd                          75.00%        100    Uncovered            
+        covered/total bins:                                24         32                      
+        missing/total bins:                                 8         32                      
+        % Hit:                                         75.00%        100                      
+        bin auto[ZERO]                                      0          1    ZERO                 
+        bin auto[RA]                                        0          1    ZERO                 
+        bin auto[SP]                                        0          1    ZERO                 
+        bin auto[GP]                                        1          1    Covered              
+        bin auto[TP]                                        1          1    Covered              
+        bin auto[T0]                                        0          1    ZERO                 
+        bin auto[T1]                                        0          1    ZERO                 
+        bin auto[T2]                                        0          1    ZERO                 
+        bin auto[S0]                                        1          1    Covered              
+        bin auto[S1]                                        1          1    Covered              
+        bin auto[A0]                                        0          1    ZERO                 
+        bin auto[A1]                                        1          1    Covered              
+        bin auto[A2]                                        1          1    Covered              
+        bin auto[A3]                                        1          1    Covered              
+        bin auto[A4]                                        1          1    Covered              
+        bin auto[A5]                                        1          1    Covered              
+        bin auto[A6]                                        1          1    Covered              
+        bin auto[A7]                                        1          1    Covered              
+        bin auto[S2]                                        1          1    Covered              
+        bin auto[S3]                                        1          1    Covered              
+        bin auto[S4]                                        1          1    Covered              
+        bin auto[S5]                                        2          1    Covered              
+        bin auto[S6]                                        1          1    Covered              
+        bin auto[S7]                                        1          1    Covered              
+        bin auto[S8]                                        1          1    Covered              
+        bin auto[S9]                                        1          1    Covered              
+        bin auto[S10]                                       1          1    Covered              
+        bin auto[S11]                                       1          1    Covered              
+        bin auto[T3]                                        1          1    Covered              
+        bin auto[T4]                                        1          1    Covered              
+        bin auto[T5]                                        1          1    Covered              
+        bin auto[T6]                                        0          1    ZERO                 
+    Coverpoint remu_cg::cp_rs1_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint remu_cg::cp_rs2_sign                   100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 15          1    Covered              
+        bin auto[NEGATIVE]                                 10          1    Covered              
+    Coverpoint remu_cg::cp_rd_sign                    100.00%        100    Covered              
+        covered/total bins:                                 2          2                      
+        missing/total bins:                                 0          2                      
+        % Hit:                                        100.00%        100                      
+        bin auto[POSITIVE]                                 22          1    Covered              
+        bin auto[NEGATIVE]                                  3          1    Covered              
+    Coverpoint remu_cg::cp_div_result                 100.00%        100    Covered              
+        covered/total bins:                                 3          3                      
+        missing/total bins:                                 0          3                      
+        % Hit:                                        100.00%        100                      
+        bin auto[DIV_NORMAL]                               19          1    Covered              
+        bin auto[DIV_BY_ZERO]                               5          1    Covered              
+        bin auto[DIV_OVERFLOW]                              1          1    Covered              
+    Cross remu_cg::cp_sign_cross                      100.00%        100    Covered              
+        covered/total bins:                                 4          4                      
+        missing/total bins:                                 0          4                      
+        % Hit:                                        100.00%        100                      
+        bin <auto[POSITIVE],auto[POSITIVE]>                 9          1    Covered              
+        bin <auto[NEGATIVE],auto[POSITIVE]>                 6          1    Covered              
+        bin <auto[POSITIVE],auto[NEGATIVE]>                 6          1    Covered              
+        bin <auto[NEGATIVE],auto[NEGATIVE]>                 4          1    Covered              
+
+TOTAL COVERGROUP COVERAGE: 89.95%  COVERGROUP TYPES: 8
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/summary.txt b/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/summary.txt
new file mode 100644
index 0000000..1066a7a
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/coverage/summary.txt
@@ -0,0 +1,54 @@
+This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv
+
+    Coverpoint mul_cg::cp_rs1                          75.00%        100    Uncovered            
+    Coverpoint mul_cg::cp_rs2                          75.00%        100    Uncovered            
+    Coverpoint mul_cg::cp_rd                           75.00%        100    Uncovered            
+    Coverpoint mul_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint mul_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint mul_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint mulh_cg::cp_rs1                         75.00%        100    Uncovered            
+    Coverpoint mulh_cg::cp_rs2                         75.00%        100    Uncovered            
+    Coverpoint mulh_cg::cp_rd                          75.00%        100    Uncovered            
+    Coverpoint mulh_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint mulh_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint mulh_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint mulhsu_cg::cp_rs1                       75.00%        100    Uncovered            
+    Coverpoint mulhsu_cg::cp_rs2                       75.00%        100    Uncovered            
+    Coverpoint mulhsu_cg::cp_rd                        75.00%        100    Uncovered            
+    Coverpoint mulhsu_cg::cp_rs1_sign                 100.00%        100    Covered              
+    Coverpoint mulhsu_cg::cp_rs2_sign                 100.00%        100    Covered              
+    Coverpoint mulhsu_cg::cp_rd_sign                  100.00%        100    Covered              
+    Coverpoint mulhu_cg::cp_rs1                        75.00%        100    Uncovered            
+    Coverpoint mulhu_cg::cp_rs2                        75.00%        100    Uncovered            
+    Coverpoint mulhu_cg::cp_rd                         75.00%        100    Uncovered            
+    Coverpoint mulhu_cg::cp_rs1_sign                  100.00%        100    Covered              
+    Coverpoint mulhu_cg::cp_rs2_sign                  100.00%        100    Covered              
+    Coverpoint mulhu_cg::cp_rd_sign                   100.00%        100    Covered              
+    Coverpoint div_cg::cp_rs1                          75.00%        100    Uncovered            
+    Coverpoint div_cg::cp_rs2                          75.00%        100    Uncovered            
+    Coverpoint div_cg::cp_rd                           75.00%        100    Uncovered            
+    Coverpoint div_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint div_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint div_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint div_cg::cp_div_result                  100.00%        100    Covered              
+    Coverpoint divu_cg::cp_rs1                         75.00%        100    Uncovered            
+    Coverpoint divu_cg::cp_rs2                         75.00%        100    Uncovered            
+    Coverpoint divu_cg::cp_rd                          75.00%        100    Uncovered            
+    Coverpoint divu_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint divu_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint divu_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint divu_cg::cp_div_result                 100.00%        100    Covered              
+    Coverpoint rem_cg::cp_rs1                          75.00%        100    Uncovered            
+    Coverpoint rem_cg::cp_rs2                          75.00%        100    Uncovered            
+    Coverpoint rem_cg::cp_rd                           75.00%        100    Uncovered            
+    Coverpoint rem_cg::cp_rs1_sign                    100.00%        100    Covered              
+    Coverpoint rem_cg::cp_rs2_sign                    100.00%        100    Covered              
+    Coverpoint rem_cg::cp_rd_sign                     100.00%        100    Covered              
+    Coverpoint rem_cg::cp_div_result                  100.00%        100    Covered              
+    Coverpoint remu_cg::cp_rs1                         75.00%        100    Uncovered            
+    Coverpoint remu_cg::cp_rs2                         75.00%        100    Uncovered            
+    Coverpoint remu_cg::cp_rd                          75.00%        100    Uncovered            
+    Coverpoint remu_cg::cp_rs1_sign                   100.00%        100    Covered              
+    Coverpoint remu_cg::cp_rs2_sign                   100.00%        100    Covered              
+    Coverpoint remu_cg::cp_rd_sign                    100.00%        100    Covered              
+    Coverpoint remu_cg::cp_div_result                 100.00%        100    Covered              
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIV.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIV.reference_output
new file mode 100644
index 0000000..9735211
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIV.reference_output
@@ -0,0 +1,52 @@
+ffffffff
+00000000
+00000000
+00000000
+00000000
+ffffffff
+00000001
+ffffffff
+00000000
+00000000
+ffffffff
+ffffffff
+00000001
+00000000
+00000000
+ffffffff
+7fffffff
+80000001
+00000001
+00000000
+ffffffff
+80000000
+80000000
+ffffffff
+00000001
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIVU.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIVU.reference_output
new file mode 100644
index 0000000..84ff2cc
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/DIVU.reference_output
@@ -0,0 +1,52 @@
+ffffffff
+00000000
+00000000
+00000000
+00000000
+ffffffff
+00000001
+00000000
+00000000
+00000000
+ffffffff
+ffffffff
+00000001
+00000002
+00000001
+ffffffff
+7fffffff
+00000000
+00000001
+00000000
+ffffffff
+80000000
+00000000
+00000001
+00000001
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/MUL.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MUL.reference_output
new file mode 100644
index 0000000..64c1bec
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MUL.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+ffffffff
+7fffffff
+80000000
+00000000
+ffffffff
+00000001
+80000001
+80000000
+00000000
+7fffffff
+80000001
+00000001
+80000000
+00000000
+80000000
+80000000
+80000000
+00000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULH.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULH.reference_output
new file mode 100644
index 0000000..79034fa
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULH.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+ffffffff
+00000000
+ffffffff
+00000000
+ffffffff
+00000000
+ffffffff
+00000000
+00000000
+00000000
+ffffffff
+3fffffff
+c0000000
+00000000
+ffffffff
+00000000
+c0000000
+40000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHSU.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHSU.reference_output
new file mode 100644
index 0000000..43d614b
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHSU.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
+7ffffffe
+3fffffff
+3fffffff
+00000000
+ffffffff
+80000000
+c0000000
+c0000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHU.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHU.reference_output
new file mode 100644
index 0000000..a4bcd18
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/MULHU.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+fffffffe
+7ffffffe
+7fffffff
+00000000
+00000000
+7ffffffe
+3fffffff
+3fffffff
+00000000
+00000000
+7fffffff
+3fffffff
+40000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/REM.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/REM.reference_output
new file mode 100644
index 0000000..8c77876
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/REM.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+00000000
+00000000
+00000001
+00000001
+ffffffff
+00000000
+00000000
+ffffffff
+ffffffff
+7fffffff
+00000000
+00000000
+00000000
+7fffffff
+80000000
+00000000
+00000000
+ffffffff
+00000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/references/REMU.reference_output b/tests/riscv-compliance/riscv-test-suite/rv32im/references/REMU.reference_output
new file mode 100644
index 0000000..59f0e2d
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/references/REMU.reference_output
@@ -0,0 +1,52 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+00000000
+00000001
+00000001
+00000001
+ffffffff
+00000000
+00000000
+00000001
+7fffffff
+7fffffff
+00000000
+7fffffff
+00000000
+7fffffff
+80000000
+00000000
+80000000
+00000001
+00000000
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+00000000
+00000000
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S
new file mode 100644
index 0000000..e02339e
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-DIV-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction DIV.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(div, x17, x18, 0xffffffff, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(div, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(div, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(div, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(div, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(div, x27, x28, 0xffffffff, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(div, x29, x30, 0x1, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(div, x21, x3, 0xffffffff, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(div, x4, x8, 0, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(div, x9, x11, 0, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(div, x12, x13, 0xffffffff, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(div, x14, x15, 0xffffffff, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(div, x16, x17, 0x1, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(div, x18, x19, 0, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(div, x20, x21, 0, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(div, x22, x23, 0xffffffff, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(div, x24, x25, 0x7fffffff, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(div, x26, x27, 0x80000001, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(div, x28, x29, 0x1, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(div, x30, x21, 0, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(div, x3, x4, 0xffffffff, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(div, x8, x9, 0x80000000, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(div, x11, x12, 0x80000000, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(div, x13, x14, 0xffffffff, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(div, x15, x16, 0x1, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S
new file mode 100644
index 0000000..3491231
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-DIVU-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction DIVU.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(divu, x17, x18, 0xffffffff, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(divu, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(divu, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(divu, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(divu, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(divu, x27, x28, 0xffffffff, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(divu, x29, x30, 0x1, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(divu, x21, x3, 0, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(divu, x4, x8, 0, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(divu, x9, x11, 0, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(divu, x12, x13, 0xffffffff, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(divu, x14, x15, 0xffffffff, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(divu, x16, x17, 0x1, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(divu, x18, x19, 0x2, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(divu, x20, x21, 0x1, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(divu, x22, x23, 0xffffffff, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(divu, x24, x25, 0x7fffffff, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(divu, x26, x27, 0, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(divu, x28, x29, 0x1, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(divu, x30, x21, 0, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(divu, x3, x4, 0xffffffff, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(divu, x8, x9, 0x80000000, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(divu, x11, x12, 0, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(divu, x13, x14, 0x1, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(divu, x15, x16, 0x1, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S
new file mode 100644
index 0000000..773b350
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-MUL-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction MUL.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(mul, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(mul, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(mul, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(mul, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mul, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(mul, x27, x28, 0, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mul, x29, x30, 0x1, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mul, x21, x3, 0xffffffff, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mul, x4, x8, 0x7fffffff, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mul, x9, x11, 0x80000000, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(mul, x12, x13, 0, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mul, x14, x15, 0xffffffff, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mul, x16, x17, 0x1, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mul, x18, x19, 0x80000001, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mul, x20, x21, 0x80000000, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(mul, x22, x23, 0, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(mul, x24, x25, 0x7fffffff, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(mul, x26, x27, 0x80000001, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(mul, x28, x29, 0x1, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mul, x30, x21, 0x80000000, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(mul, x3, x4, 0, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(mul, x8, x9, 0x80000000, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(mul, x11, x12, 0x80000000, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(mul, x13, x14, 0x80000000, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mul, x15, x16, 0, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S
new file mode 100644
index 0000000..a950da3
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-MULH-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction MULH.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(mulh, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(mulh, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(mulh, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(mulh, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulh, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(mulh, x27, x28, 0, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulh, x29, x30, 0, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulh, x21, x3, 0xffffffff, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulh, x4, x8, 0, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulh, x9, x11, 0xffffffff, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(mulh, x12, x13, 0, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulh, x14, x15, 0xffffffff, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulh, x16, x17, 0, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulh, x18, x19, 0xffffffff, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulh, x20, x21, 0, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(mulh, x22, x23, 0, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(mulh, x24, x25, 0, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(mulh, x26, x27, 0xffffffff, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(mulh, x28, x29, 0x3fffffff, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulh, x30, x21, 0xc0000000, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(mulh, x3, x4, 0, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(mulh, x8, x9, 0xffffffff, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(mulh, x11, x12, 0, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(mulh, x13, x14, 0xc0000000, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulh, x15, x16, 0x40000000, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S
new file mode 100644
index 0000000..0620cd4
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-MULHSU-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction MULHSU.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(mulhsu, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhsu, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhsu, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhsu, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhsu, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(mulhsu, x27, x28, 0, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhsu, x29, x30, 0, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhsu, x21, x3, 0, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhsu, x4, x8, 0, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhsu, x9, x11, 0, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(mulhsu, x12, x13, 0, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhsu, x14, x15, 0xffffffff, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhsu, x16, x17, 0xffffffff, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhsu, x18, x19, 0xffffffff, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhsu, x20, x21, 0xffffffff, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(mulhsu, x22, x23, 0, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhsu, x24, x25, 0, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhsu, x26, x27, 0x7ffffffe, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhsu, x28, x29, 0x3fffffff, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhsu, x30, x21, 0x3fffffff, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(mulhsu, x3, x4, 0, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhsu, x8, x9, 0xffffffff, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhsu, x11, x12, 0x80000000, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhsu, x13, x14, 0xc0000000, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhsu, x15, x16, 0xc0000000, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S
new file mode 100644
index 0000000..88bddfd
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-MULHU-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction MULHU.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(mulhu, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhu, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhu, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhu, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhu, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(mulhu, x27, x28, 0, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhu, x29, x30, 0, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhu, x21, x3, 0, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhu, x4, x8, 0, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhu, x9, x11, 0, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(mulhu, x12, x13, 0, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhu, x14, x15, 0, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhu, x16, x17, 0xfffffffe, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhu, x18, x19, 0x7ffffffe, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhu, x20, x21, 0x7fffffff, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(mulhu, x22, x23, 0, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhu, x24, x25, 0, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhu, x26, x27, 0x7ffffffe, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhu, x28, x29, 0x3fffffff, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhu, x30, x21, 0x3fffffff, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(mulhu, x3, x4, 0, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(mulhu, x8, x9, 0, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(mulhu, x11, x12, 0x7fffffff, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(mulhu, x13, x14, 0x3fffffff, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(mulhu, x15, x16, 0x40000000, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/REM.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/REM.S
new file mode 100644
index 0000000..1aee9df
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/REM.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-REM-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction REM.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(rem, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(rem, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(rem, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(rem, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(rem, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(rem, x27, x28, 0x1, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(rem, x29, x30, 0, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(rem, x21, x3, 0, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(rem, x4, x8, 0x1, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(rem, x9, x11, 0x1, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(rem, x12, x13, 0xffffffff, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(rem, x14, x15, 0, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(rem, x16, x17, 0, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(rem, x18, x19, 0xffffffff, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(rem, x20, x21, 0xffffffff, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(rem, x22, x23, 0x7fffffff, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(rem, x24, x25, 0, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(rem, x26, x27, 0, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(rem, x28, x29, 0, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(rem, x30, x21, 0x7fffffff, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(rem, x3, x4, 0x80000000, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(rem, x8, x9, 0, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(rem, x11, x12, 0, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(rem, x13, x14, 0xffffffff, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(rem, x15, x16, 0, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S b/tests/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S
new file mode 100644
index 0000000..84e7817
--- /dev/null
+++ b/tests/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S
@@ -0,0 +1,142 @@
+# RISC-V Compliance Test RV32IM-REMU-01
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Specification: RV32IM Base Integer Instruction Set, Version 2.0
+# Description: Testing instruction REMU.
+
+#include "test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV32M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n")
+
+	# address for test results
+	la	x2, test_1_res
+
+	TEST_RR_SRC2(remu, x17, x18, 0, 0x0, 0x0, x2, 0)
+	TEST_RR_SRC2(remu, x19, x20, 0, 0x0, 0x1, x2, 4)
+	TEST_RR_SRC2(remu, x21, x22, 0, 0x0, -0x1, x2, 8)
+	TEST_RR_SRC2(remu, x23, x24, 0, 0x0, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(remu, x25, x26, 0, 0x0, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n")
+
+	# address for test results
+	la	x2, test_2_res
+
+	TEST_RR_SRC2(remu, x27, x28, 0x1, 0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(remu, x29, x30, 0, 0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(remu, x21, x3, 0x1, 0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(remu, x4, x8, 0x1, 0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(remu, x9, x11, 0x1, 0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n")
+
+	# address for test results
+	la	x2, test_3_res
+
+	TEST_RR_SRC2(remu, x12, x13, 0xffffffff, -0x1, 0x0, x2, 0)
+	TEST_RR_SRC2(remu, x14, x15, 0, -0x1, 0x1, x2, 4)
+	TEST_RR_SRC2(remu, x16, x17, 0, -0x1, -0x1, x2, 8)
+	TEST_RR_SRC2(remu, x18, x19, 0x1, -0x1, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(remu, x20, x21, 0x7fffffff, -0x1, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n")
+
+	# address for test results
+	la	x2, test_4_res
+
+	TEST_RR_SRC2(remu, x22, x23, 0x7fffffff, 0x7fffffff, 0x0, x2, 0)
+	TEST_RR_SRC2(remu, x24, x25, 0, 0x7fffffff, 0x1, x2, 4)
+	TEST_RR_SRC2(remu, x26, x27, 0x7fffffff, 0x7fffffff, -0x1, x2, 8)
+	TEST_RR_SRC2(remu, x28, x29, 0, 0x7fffffff, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(remu, x30, x21, 0x7fffffff, 0x7fffffff, 0x80000000, x2, 16)
+
+	# ---------------------------------------------------------------------------------------------
+
+	RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n")
+
+	# address for test results
+	la	x2, test_5_res
+
+	TEST_RR_SRC2(remu, x3, x4, 0x80000000, 0x80000000, 0x0, x2, 0)
+	TEST_RR_SRC2(remu, x8, x9, 0, 0x80000000, 0x1, x2, 4)
+	TEST_RR_SRC2(remu, x11, x12, 0x80000000, 0x80000000, -0x1, x2, 8)
+	TEST_RR_SRC2(remu, x13, x14, 0x1, 0x80000000, 0x7fffffff, x2, 12)
+	TEST_RR_SRC2(remu, x15, x16, 0, 0x80000000, 0x80000000, x2, 16)
+
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+test_1_res:
+	.fill 5, 4, -1
+test_2_res:
+	.fill 5, 4, -1
+test_3_res:
+	.fill 5, 4, -1
+test_4_res:
+	.fill 5, 4, -1
+test_5_res:
+	.fill 5, 4, -1
+test_6_res:
+	.fill 5, 4, -1
+test_7_res:
+	.fill 5, 4, -1
+test_8_res:
+	.fill 5, 4, -1
+test_9_res:
+	.fill 5, 4, -1
+test_10_res:
+	.fill 5, 4, -1
+
+RV_COMPLIANCE_DATA_END
diff --git a/tests/riscv-compliance/spec/TestFormatSpec.adoc b/tests/riscv-compliance/spec/TestFormatSpec.adoc
new file mode 100644
index 0000000..84dc16b
--- /dev/null
+++ b/tests/riscv-compliance/spec/TestFormatSpec.adoc
@@ -0,0 +1,758 @@
+= RISC-V Compliance Test Format Specification =
+RISC-V Foundation Compliance Task Group
+Issue 1.0 Draft
+:toc:
+:icons: font
+:numbered:
+:source-highlighter: rouge
+
+////
+SPDX-License-Identifier: CC-BY-4.0
+
+Document conventions:
+- one line per paragraph (don't fill lines - this makes changes clearer)
+- Wikipedia heading conventions (First word only capitalized)
+- US spelling throughout.
+- Run "make spell" before committing changes.
+- Build the HTML and commit it with any changed source.
+- Do not commit the PDF!
+////
+
+== Introduction
+=== About
+
+This document contains the RISC-V <<The RISC-V compliance test pool,_compliance test pool_>> structure and <<The compliance test,_compliance test_>> format specification which shall be used as a reference document for those who write or are going to write tests for the RISC-V compliance test pool and for those who are going to use the <<The RISC-V compliance test pool,_compliance test pool_>> in their own compliance test framework.
+
+* It includes, as example, source code listing and detailed description of one <<The compliance test,_compliance test_>>
+
+Framework specification which includes description of how the <<The RISC-V compliance test suite,_compliance test suites_>> are built and used for the appropriate RISC-V configurations is given in the complementary Framework Specification document. This document is made freely available under a <<app_cc_by_4.0>>.
+
+
+=== Intended audience
+
+This document is intended for design and verification engineers who wish to develop new compliance tests and also for those who wish to write or adapt their own test framework. 
+
+=== Future work
+
+This is a draft document; it partially documents what exists, and partially documents the longer-term goal.
+As such, this document still under review and its content will change.
+Its primary aim is to get a long-term stable version of the spec and to give test authors sufficient lead time to prepare test authoring tools and strategies.
+
+=== Feedback and how to contribute
+
+Comments on this document should be made through the RISC-V Compliance Task Group mailing list. Proposed changes may be submitted as git pull requests.
+
+You are encouraged to contribute to this repository by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory.
+
+NOTE: Don't forget to add your own name to the list of contributors in the document.
+
+==== AsciiDoc
+
+This is a structured text format used by this document.  Simple usage should be fairly self evident.
+
+* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website].
+
+* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website].
+
+* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful.
+
+==== Installing tools
+
+To generate the documentation as HTML you need _asciidoctor_ and to generate as
+PDF you need _asciidoctor-pdf_.
+
+* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor].
+
+* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf].
+
+To spell check you need _aspell_ installed.
+
+==== Building the documentation
+
+To build HTML:
+[source,make]
+----
+make html
+----
+
+To build PDF:
+[source,make]
+----
+make pdf
+----
+
+To build both:
+[source,make]
+----
+make
+----
+
+To check the spelling (excludes any listing or code phrases):
+[source,make]
+----
+make spell
+----
+
+Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`].
+
+=== Contributors
+
+This document has been created by the following people (in alphabetical order of surname).
+
+[quote]
+Allen Baum, Jeremy Bennett, Radek Hajek, Premysl Vaclavik
+
+=== Document history
+[cols="<1,<2,<3,<4",options="header,pagewidth",]
+|================================================================================
+| _Revision_ | _Date_            | _Author_ | _Modification_
+
+
+| 1.2.5 Draft  | 22 Jan 2020      |
+
+Allen Baum |
+
+        * removed references to test pool reference doc, mentioned that the framework will generate it
+	* clarified that macros defined in a test may be used in a test
+	* minor clarifications, consistency changes, added page breaks
+
+| 1.2.4 Draft  | 08 Jan 2020      |
+
+Allen Baum |
+
+        * typos fixed
+	* added RVTEST_BASEUPD macro
+	* added explanations for each macro
+	* clarified restrictions on #ifdefs
+	* added comment that test cases with identical conditions should be combined into a single case
+	* documented that test case first parameter should match the #ifdef parameter that precedes it
+
+| 1.2.3 Draft  | 02 Dec 2019      |
+
+Allen Baum |
+
+        * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined
+	* add more complete list of macros, their uses, parameters, and whether they are required or optional
+	* minor structural changes (moving sentences, renumbering) and typo fixes
+	* clarified impact of debug macros
+	* clarified how SIGUPD and BASEUPD must be used, fixed parameter description
+
+| 1.2.2 Draft  | 21 Nov 2019      |
+
+Allen Baum |
+
+        * remove section about test taxonomy, binary tests, emulated ops
+        * clarify/fix  boundary between test target and framework responsibilities
+          (split test target into test target and test shell)
+        * remove To Be discussed items that have been discussed
+	* remove default case condition; if conditions are unchaged, part of same case
+        *  minor grammatical changes related to the above
+
+| 1.2.1 Draft  | 19 Nov 2019      |
+
+Allen Baum |
+
+        * spec/TestFormatSpec.adoc: changed the format of the signature to fixed 32b data size only extracted from COMPLIANCE_DATA_BEGIN/END range.
+        * made test suite subdirectories upper case, with sub-extensions camel case
+	* updated example to match most recent riscof implement macros
+	* fix format so Appendix is now in TOC
+	* moved note about multiple test cases in a test closer to definition
+	* fixed cut/paste error in example of test pool
+        * more gramatical fixes, clarifications added
+        * added To Be Discussed items regarding emulated instruction and binary tests
+	* added graphic of test suite/test_pool/test/test_case hierarchy
+
+
+| 1.2.1 Draft  | 12 Oct 2019      |
+
+Allen Baum |
+
+minor grammar, wording, syntax corrections, added detail and clarification from suggestions by Paul Donahue
+
+| 1.2 Draft  | 12 Sep 2019      |
+
+Allen Baum |
+
+minor grammar, wording, syntax corrections, added detail and clarification
+Added detail regarding the 2 approaches for test selection: central database, or embedded conditions embedded in macros
+Added detail of proposed standard macros RVTEST_SIGBASE, RVTEST_SIGUPD, RVTEST_CASE
+More explanation of spec status in initial _future work_ paragraph (i.e. goal, not yet accomplished)
+Removed many "to Be Discussed items and made them official
+Removed options, made POR for test selection and standard macros RVTEST_SIGBASE, RVTEST_SIGUPD, RVTEST_CASE
+Removed prohibition on absolute addresses
+Clarified which test suites a test should be in where they are dependent on multiple extensions
+Clarified use of includes and macros (and documented exsiting deviations)
+Clarified use of YAML files
+Added detail to description and uses of common compliance test pool reference document
+
+| 1.1 Draft  | 15 Feb 2019      |
+
+Radek Hajek |
+
+Appendix A: example assertions update
+
+| 1.0 Draft  | 10 Dec 2018      |
+
+Radek Hajek, Premysl Vaclavik |
+
+First version of the document under this file name. Document may contain some segments of the README.adoc from the compatibility reasons.
+
+|================================================================================
+<<<
+== Foreword
+The compliance test pool shall become a complete set of compliance tests which will allow developers to build a compliance test suite for any legal RISC-V configuration. The compliance tests will be very likely written by various authors and therefore it is very important to define the compliance test pool structure and compliance test form, which will be obligatory for all tests. Unification of tests will guarantee optimal compliance test pool management and also better quality and readability of the tests. Last but not least, it will simplify the process of adding new tests into the existing compliance test pool and the formal revision process.
+
+== Vocabulary
+=== The compliance test
+The compliance test is a nonfunctional testing technique which is done to validate whether the system developed meets the prescribed standard or not. In this particular case the golden reference is the RISC-V ISA standard. 
+
+For purpose of this document we understand that the compliance test is a single test which represents the minimum test code that can be compiled and run. It is written in assembler code and its product is a <<The test signature,_test signature_>>. A compliance test may consist of several <<The test case,_test cases_>>.
+
+=== The RISC-V compliance test pool
+The RISC-V compliance test pool consists of all approved <<The compliance test,_compliance tests_>> that can be assembled by the test framework, forming the <<The RISC-V compliance test suite,_compliance test suite_>>. The RISC-V compliance test pool must be test target independent (so, should correctly run on any compliant target). Note that this nonfunctional testing is not a substitute for verification or device test.
+
+=== The RISC-V compliance test suite
+The RISC-V compliance test suite is a group of tests selected from the <<The RISC-V compliance test pool,_compliance test pool_>> to test compliance for the specific RISC-V configuration. Test results are obtained in the form of a <<The test suite signature,_test suite signature_>>. Selection of tests is performed based on the target's asserted configuration, and the spec,  Execution Environment or platform requirements. Compliant processor or processor models shall exhibit the same test suite signature as the golden reference test suite signature for the specific configuration being tested.
+
+=== The test case
+A _test case_ is part of the compliance test that tests just one feature of the specification.
+
+----
+Note: a single test can contain multiple test cases, each of which can have its own test inclusion condition (as defined by the cond_str parameter of the RVTEST_CASE macro.
+----
+
+[#img-testStruct]
+.Test Suite, Test_Pool, Test, Test_Case relationship
+image::./testpool.jpg[testStruct]
+
+=== The test case signature
+The _test case signature_ is represented by single or multiple values. Values are written to memory at the address starting at the address specified by the RVMODEL_DATA_BEGIN and ending at RVMODEL_DATA_END. Signatures can be generated most easily using the RVTEST_SIGUPD macro.
+
+=== The test signature
+The <<The test signature,_test signature_>> is a characteristic value which is generated by the compliance test run. The <<The test signature,_test signature_>> may consist of several <<The test case signature,_test case signatures_>>, prefixed with a separate line containing the name of the test and a unique value indicating its version (e.g. git checkin hash). The test target is responsible for extracting values from memory and properly formatting them, using metadata provided to it by the framework using the RVMODEL_DATA_BEGIN and RVMODEL_DATA_END macros. Test case signature values are written one per line, starting with the most-significant byte on the left-hand side with the format <hex_value> where the length of value will be 32 bits (so 8 characters), regardless of the actual value length computed by the test.
+ 
+=== The test suite signature
+The _test suite signature_ is defined as a set of <<The test signature,_test signatures_>> valid for given <<The RISC-V compliance test suite,_compliance test suite_>>. It represents the test signature of the particular RISC-V configuration selected for the compliance test. 
+
+=== The target shell
+The <<The target shell, _target shell_>> is the software and hardware environment around the <<The test target,_test target_>> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <<The target shell, _target shell_>> is a .S <<The compliance test,_compliance test_>> file, and the output is a <<The test signature,_test signature_>>.
+
+=== The test target
+The <<The test target,_test target_>> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the  <<The target shell, _target shell_>> to handle different targets while using the same <<The RISC-V compliance test pool,_compliance test pool_>> as a test source.
+
+=== The RISC-V processor (device) configuration
+The RISC-V ISA specification allows many optional instructions, registers, and other features. Production directed targets typically have a fixed subset of available options. A simulator, on the other hand, may implement all known options which may be constrained to mimic the behavior of the RISC-V processor with the particular configuration.  It is a role of the Compliance Test Framework to build and use the <<The RISC-V compliance test suite,_compliance test suite_>> suitable for the selected RISC-V configuration. 
+
+
+=== The compliance test framework
+The <<The compliance test framework,_compliance test framework_>> selects and configures the <<The RISC-V compliance test suite,_compliance test suite_>> from the <<The RISC-V compliance test pool,_compliance test pool_>> for the selected <<The test target,_test target_>> based on both the specific architectural choices made by an implementation and those required by the Execution Environment It causes the <<The target shell, _target shell_>> to build, execute, and report a signature. The <<The compliance test framework,_compliance test framework_>> then compares reported signatures, inserts test part names and version numbers and summarizes differences (or lack of them) into a RISC-V compliance report. The primary role of the well-defined <<The RISC-V compliance test pool,_compliance test pool_>> structure is to provide the tests in a form suitable for the Compliance Test Framework selection engine. 
+
+<<<
+== Compliance test pool 
+=== Test pool structure
+
+The structure of <<The compliance test,_compliance tests_>> in the <<The RISC-V compliance test pool,_compliance test pool_>> shall be based on defined RISC-V extensions and privileged mode selection. This will provide a good overview of which parts of the ISA specification are already covered in the <<The RISC-V compliance test suite,_compliance test suite_>>, and which tests are suitable for certain configurations. The compliance test pool has this structure:
+
+----
+compliance-tests-suite (root)
+|-- <architecture>_<mode>/<feature(s)>, where
+<architecture> is [ RV32I | RV64I | RV32E ]
+<mode> is [ M | MU | MS | MSU ], where
+   M   Machine      mode tests - tests execute in M-mode only 
+   MU  Machine/User mode tests - tests execute in both M- & U-modes (S-mode may exist)
+   MS  Machine/Supv mode tests - tests execute in both M- & S-modes (not U-mode)
+   MSU All          mode tests - tests execute in all of M-, S-, & U-Modes
+<feature(s)> are the lettered extension [A | B | C | M ...] or subextension [Zifencei | Zam | ...] when the tests involve extensions, or more general names when tests cut across extension definitionss (e.g. Priv, Interrupt, Vm). The feature string consists of an initial capital letter, followed by any further letters in lower case.
+
+----
+
+Note that this structure is for organizational purposes, not functional purposes, although full test names will take advantage of it.
+
+Tests that will be executed in different modes, even if the results are identical, should be replicated in each mode directory, e.g. RV32I_M/, RV32I_MS/, and RV32I_MU/. These tests  are typically those involving trapping behavior, e.g load, store, and privilged ops.
+
+=== Test naming
+
+The naming convention of a single test:
+
+<__test objective__>-<__test number__>.S
+
+* __test objective__ – an aspect that the test is focused on. A test objective may be an instruction for ISA tests (ADD, SUB, ...), or a characteristic covering multiple instructions, e.g. exception event (misaligned fetch, misalign load/store) and others.
+
+* __test number__ – number of the test. It is expected that multiple tests may be specified for one test objective. We recommend to break down complex tests into a set of small tests. A simple rule of thumb is one simple test objective = one simple test. The code becomes more readable and the test of the objective can be improved just by adding <<The test case,_test cases_>>. The typical example are instruction tests for the F extension. 
+
+*  A test name shall not include an ISA category as part of its name (i.e. the directory, subdirectory names). + 
+Experience has shown that including ISA category in the test name leads to very long test names. Instead, we have introduced the <<Test pool structure,test pool structure>> where the full name is composed of the test path in the <<Test pool structure,test pool structure>> and the simple test name. +
+Since full names can be reconstructed easily it is not necessary to include the path in test names.
+
+=== The test structure of a compliance test
+
+All tests shall use a signature approach. Each test shall be written in the same style, with defined mandatory items. There are both pre-defined and model-specific macros which shall be used in every test to guarantee their portability. In addition, there are both pre-defined and model specific macros that are not required, but may be used in tests.
+
+*Required, Pre-defined Macros* +
+  RVTEST_ISA(isa_str)          // defines the Test Virtual Machine (TVM, the ISA being tested) +
+  -  Empty macro to specify the isa required for compilation of the test. +
+  -  This is mandated to be present at the start of the test. +
+  RVTEST_CODE_BEGIN            // start of code (test) section +
+  - Macro to indicate test code start add and where test startup routine is inserted. +
+  - No part of the code section should precede this macro +
+  RVTEST_CODE_END              // end of code (test) section +
+  = Macro to indicate test code end. +
+  - No part of the code section should follow after this macro. +
+  RVTEST_CASE(CaseName, CondStr)  // execute this case only if condition in cond_str are met +
+- CaseName is arbitrary string  +
+- CondStr is evaluated to determine if the test-case is enabled and sets name variable +
+- CondStr can also define compile time macros required for the test-case to be enabled. +
+- the test-case must be delimited with an #ifdef CaseName/#endif pair +
+- the format of CondStr can be found in https://riscof.readthedocs.io/en/latest/cond_spec.html#cond-spec
+
+*Required, Model-defined Macros* +
+  RVMODEL_DATA_BEGIN            // start of output data (signature) section +
+  RVMODEL_DATA_END              // end of output data (signature) section +
+  RVMODEL_DATA_SECTION          // model defined data area +
+ - contains static input data and intermediate scratch area for the test (e.g. stack) +
+  RVMODEL_HALT                  // defines model halt mechanism, which starts signature saving
+
+*Optional, Pre-defined Macros* +
+  RVTEST_SIGBASE(BaseReg,Val)   // defines the base register used to update signature values +
+ - Register BaseReg is loaded with value Val +
+ - hidden_offset is initialized to zero +
+  RVTEST_SIGUPD(BaseReg, SigReg [,Value]) // stores sig value, with optional value assertion +
+ - Register Val is stored in mem(reg_Base+hidden_offset) +
+ - hidden_offset is post incremented  so repeated uses store signature values sequentially +
+  RVTEST_BASEUPD(BaseReg[oldBase[,newOff]]) // [moves &] updates BaseReg past stored signature +
+ - Register BaseReg is loaded with the oldReg+newOff+hidden_offset +
+ - BaseReg is used if oldBase isn't specified; 0 is used if newOff isn't specified +
+ - hidden_offset is re-initialized to 0 afterwards
+
+*Optional, Model-defined Macros* +
+  RVMODEL_BOOT                       // contains boot code for model; may include emulation code or trap stub +
+  RVMODEL_IO_INIT                    // initializes IO for debug output +
+ - this must be invoked if any of the other RV_MODEL_IO_* macros are used +
+  RVMODEL_IO_CHECK                   // checks IO for debug output +
+ - <needs description of how this is used > +
+  RVMODEL_IO_ASSERT_GPR_EQ(ScrReg, Reg, Value) // debug assertion that GPR should have value +
+ - outputs a debug message if Reg!=Value +
+ - ScrReg is a scratch register used by the output routine; its final value cannot be guaranteed +
+  RVMODEL_IO_WRITE_STR(ScrReg, String) // output debug string, using a scratch register +
+ - outputs the message String
+ - ScrReg is a scratch register used by the output routine; its final value cannot be guaranteed +
+
+The test structure of a compliance test shall have the following sections in the order as follows:
+
+.  Header + license (including a specification link, a brief test description and RVTEST_ISA macro))
+.  Includes of header files (see Common Header Files section)
+.  Test Virtual Machine (TVM) specification
+.  Test code between “RVTEST_CODE_BEGIN” and “RVTEST_CODE_END”
+.  Input data section, marked with "RVMODEL_DATA_SECTION"
+.  Output data section between “RVMODEL_DATA_BEGIN” and “RVMODEL_DATA_END”.
+
+
+ Note that there is no a requirement that the code or scratch data sections must be contiguous in memory, or that they be located before or after data or code sections (configured by embedded directives recognized by the linker)
+
+==== Common test format rules
+
+There are the following common rules that shall be applied to each <<The compliance test,_compliance test_>>:
+
+. Always use “//” as commentary. “#” should be used only for includes and defines.
+. A test shall be divided into logical blocks (<<The test case,_test cases_>>) according to the test goals. Test cases are enclosed in an `#ifdef <__CaseName__>, #endif` pair and begin with the RVTEST_CASE(CaseName,CondStr) macro that specifies the test case name, and a string that defines the conditions under which that <<The test case,_Test case_>> can be selected for assembly and execution. Those conditions will be collected and used to generate the database which in turn is used to select tests for inclusion in the test suite for this target.
+. Tests should use the RVTEST_SIGBASE(BaseReg,Val) macro to define the GPR used as a pointer to the output signature area, and its initial value. It can be used multiple times within a test to reassign the output area or change the base register. This value will be used by the invocations of the RVTEST_SIGUPD macro.
+. Tests should use the RVTEST_SIGUPD(BaseReg, SigReg, ScratchReg, Value) macro to store signature values using (only) the base register defined in the most recently encountered RVTEST_SIGBASE(BaseReg,Val) macro. Repeated uses will automatically have an increasing offset that is managed by the macro. 
+.. Uses of RVTEST_SIGUPD shall always be preceded sometime in the test case by RVTEST_SIGBASE. +
+.. The SIGUPD macro may optionally invoke a test assertion macro (e.g. RVMODEL_IO_ASSERT_GPR_EQ) with an assertion value for debugging, determined by the presence of ScratchReg and Value parameters. +
+.. Tests that use SIGUPD inside a loop or in any section of code that will be repeated (e.g. traps) must use the BASEUPD macro between each loop iteration or repeated code to ensure static values of the base and offset don't overwrite older values. 
+. When macros are needed for debug purposes, only macros from compliance_model.h shall be used. 
+   Note that using this feature shall not affect the signature results of the test run.
+. Test shall not include other tests (e.g. #include “../add.S”) to prevent non-complete tests, compilation issues, and problems with code maintenance. 
+. Tests and test cases shall be skipped if not required for a specific model test configuration based on test conditions defined in the RVTEST_CASE macro. Tests that are selected may be further configured using variables (e.g. XLEN) which are passed into the tests and used to compile them. In either case, those conditions and variables are derived from the YAML specification of the device and execution environment that are passed into the framework. The flow is to run a compliance test suite built by the <<The compliance test framework,_Compliance Test Framework_>> from the <<The RISC-V compliance test pool,_compliance test pool_>> to determine which tests and test cases to run. 
+. Tests shall not depend on tool specific features. For example, tests shall avoid usage of internal GCC macros (e..g. ____risc_xlen__), specific syntax (char 'a' instead of 'a) or simulator features (e.g. tohost) etc.
+. Each test shall be ended by the (target specific) “RVMODEL_HALT“ macro. Depending on branches in the test, there may be more than one instance of this in a test.
+. Macros defined outside of a test shall only be defined in specific predefined header files (see <<Common Header Files,_Common Header Files_>> below), and once they are in use, they may be modified only if the function of all affected tests remains unchanged.
+It is acceptable that macros use may lead to operand repetition (register X is used every time).
+- The aim of this restriction is to have test code more readable and to avoid side effects which may occur when different contributors will include new <<The compliance test,_compliance tests_>> or updates of existing ones in the <<The RISC-V compliance test pool,_compliance test pool_>>.
+This measure results from the negative experience, where the <<The RISC-V compliance test suite,_compliance test suite_>> could be used just for one target while the compliance test code changes were necessary to have it also running for other targets.
+
+==== Common Header Files
+
+Each test shall include only the following header files:
+
+. _compliance_model.h_ – defines target-specific macros, both required and optional:  (e.g. RVMODEL_xxx)
+. _compliance_test.h_ –  defines pre-defined test macros both required and optional:  (e.g. RVTEST_xxx)
+
+Adding new header files is forbidden. It may lead to macro redefinition and compilation issues.
+Macros maybe defined and used inside a test, as they will not be defined outside that specific test.
+Assertions will generate code that reports assertion failures (and optionally successes?) only if enabled by the framework.
+In addition, the framework may collect the assertion values and save them as a signature output file if enabled by the framework.
+
+----
+Note that there are other legacy header files (aw_test_macros.h, riscv_test.h, encoding.h, ..) already included and used in existing tests that. 
+These header files shall not be modified for testing purposes. New tests should must either move them into compliance_test.h or not use them.
+----
+
+==== Framework Requirements
+
+The framework will import files that describe 
+
+- the implemented, target-specific configuration parameters in YAML format
+
+- the required, platform-specific  configuration parameters in YAML format
+
+The framework will generate intermediate files, including a Test Database YAML file that selects tests from the test pool to generate a test suite for the target.
+
+The framework will also invoke the <<The target shell, _target shell_>> as appropriate to cause tests to be built, loaded, executed, and results reported.
+
+The YAML files define both the values of those conditions and values that can be used by the framework to configure tests (e.g. format of WARL CSR fields). 
+Tests should not have #if, #ifdef, etc. for conditional assembly except those that surround RVMODEL_CASE macros
+Instead, each of those should be a separate <<The test case,_test case_>> whose conditions are defined in
+ the common reference document entry for that test and test case number.
+
+<<<
+[appendix]
+
+== Example - ISA test _ADD-01.S_
+
+.a) Header and license
+
+----
+// RISC-V Compliance Test ADD-01
+//
+// Copyright (c) 2017, Codasip Ltd.
+// Copyright (c) 2018, Imperas Software Ltd. Additions
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//    * Redistributions of source code must retain the above copyright
+//      notice, this list of conditions and the following disclaimer.
+//    * Redistributions in binary form must reproduce the above copyright
+//      notice, this list of conditions and the following disclaimer in the
+//      documentation and/or other materials provided with the distribution.
+//    * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
+//      names of its contributors may be used to endorse or promote products
+//      derived from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+// IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. BE LIABLE FOR ANY DIRECT,
+// INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Specification: RV32I Base Integer Instruction Set, Version 2.0
+// Description: Testing instruction ADD.
+----
+
+.b) Includes of header files
+
+----
+#include "compliance_test.h"
+#include "compliance_model.h"
+
+----
+
+.c) TVM selection
+
+----
+// Test Virtual Machine (TVM) used by program.
+RVTEST_ISA("RV32M")   //This is a standard macro
+----
+
+.d) Test code
+
+ISA test is divided into several test cases marked as “A“,“B“,“C“, etc. These test cases distinguish various logical tests. The test uses macros from compliance_io.h for debug purposes.
+
+----
+// Test code region.
+RVTEST_CODE_BEGIN
+
+   RVMODEL_IO_INIT
+   RVMODEL_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+   RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
+----
+
+.d.A) Test code - test case A
+
+Test case “A“ focuses on checking corner case values of the ADD instruction. In particular, 0, 1, -1, 0x7FFFFFFF, 0x80000000 with 0, 1, -1, MIN, MAX values.
+
+----
+// -------------------------------------------------------------------------------------
+#ifdef TEST_CASE_A
+//  update case variable, describes test, defines framework test requirements
+RVTEST_CASE(TEST_CASE_A ,"check ISA:=regex(.*I.*); def TEST_CASE_A=True")
+RVMODEL_IO_WRITE_STR(x31, "// Test case A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");
+
+// Addresses for test data and results
+la x1, test_A1_data
+RVTEST_SIGBASE(x2, test_A1_res)      //this sets x2 as sig_base and initializes it and sig_offset
+
+// Load testdata
+lw x3, 0(x1)
+
+// Register initialization
+li x4, 0
+li x5, 1
+li x6, -1
+li x7, 0x7FFFFFFF
+li x8, 0x80000000
+
+// Test
+add x4, x3, x4
+add x5, x3, x5
+add x6, x3, x6
+add x7, x3, x7
+add x8, x3, x8
+
+// Store results, and assert expected values
+RVTEST_SIGUPD(x2, x3, 0x00000000) -- stores x3 at sig_base+sig_offset, updates sig_offset
+RVTEST_SIGUPD(x2, x4, 00000000) -- stores x4 at sig_base+sig_offset, updates sig_offset
+RVTEST_SIGUPD(x2, x5, 0x00000000)
+RVTEST_SIGUPD(x2, x6, 0xFFFFFFFF)
+RVTEST_SIGUPD(x2, x7, 0xFFFFFFFF)
+RVTEST_SIGUPD(x2, x8, 0x80000000)
+
+
+RVMODEL_IO_WRITE_STR(x31, "// Test case A1 - Complete\n");
+
+// ---------------------------------------------------------------------------
+RVMODEL_IO_WRITE_STR(x31, "// Test case A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");
+
+<similar code to A1>
+
+// ---------------------------------------------------------------------------
+RVMODEL_IO_WRITE_STR(x31, "// Test case A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");
+
+<similar code to A1>
+
+// ---------------------------------------------------------------------------
+RVMODEL_IO_WRITE_STR(x31, "// Test case A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");
+
+<similar code to A1>
+
+// ---------------------------------------------------------------------------
+RVMODEL_IO_WRITE_STR(x31, "// Test case A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");
+
+<similar code to A1>
+
+#endif
+----
+<<<
+.d.B) Test code - test case B
+
+Test case “B“ focuses on forwarding between instruction. It means that a result of an instruction is immediately passed to another instruction.
+
+----
+// ---------------------------------------------------------------------------
+#ifdef TEST_CASE_B
+//  update case variable, describes test, defines framework test requirements
+RVTEST_CASE(TEST_CASE_B ,"check ISA:=regex(.*I.*); def TEST_CASE_B=True")
+RVMODEL_IO_WRITE_STR(x31, "// Test case B - testing forwarding between instructions\n");
+
+// Addresses for test data and results
+la x25, test_B_data
+RVTEST_SIGBASE(x26, test_B_res)      //this sets x26 as sig_base and initializes it and sig_offset
+
+// Load testdata
+lw x28, 0(x25)
+
+// Register initialization
+li x27, 0x1
+
+// Test
+add x29, x28, x27
+add x30, x29, x27
+add x31, x30, x27
+add x1,  x31, x27
+add x2,  x1,  x27
+add x3,  x2,  x27
+
+// store results, and assert expected values
+RVTEST_SIGUPD(x26, x27, 0x00000001) //store x27 at sig_base+sig_offset, update sig_offset, assert expected value
+RVTEST_SIGUPD(x26, x29, 0x0000ABCE)
+RVTEST_SIGUPD(x26, x30, 0x0000ABCF)
+RVTEST_SIGUPD(x26, x31, 0x0000ABD0)
+RVTEST_SIGUPD(x26, x1,  0x0000ABD1)
+RVTEST_SIGUPD(x26, x2,  0x0000ABD2)
+RVTEST_SIGUPD(x26, x3,  0x0000ABD3)
+
+RVMODEL_IO_WRITE_STR(x31, "// Test case B - Complete\n");
+
+#endif
+----
+<<<
+.d.C) Test code - test case C
+
+Test case “C“ focuses on writing to x0. This register is hardwired to the 0 value, so in any RISC-V implementation, it must not be overwritten.
+
+----
+// -------------------------------------------------------------------
+#ifdef TEST_CASE_C
+//  update case variable, describes test, defines framework test requirements
+RVTEST_CASE(TEST_CASE_B ,"check ISA:=regex(.*I.*); def TEST_CASE_C=True")
+RVMODEL_IO_WRITE_STR(x31, "// Test case C - testing writing to x0\n");
+
+// Addresses for test data and results
+la x1, test_C_data
+RVTEST_SIGBASE(x2, test_C_res)      //this sets x2 as sig_base and initializes it and sig_offset
+
+// Load testdata
+lw x28, 0(x1)
+
+// Register initialization
+li x27, 0xF7FF8818
+
+// Test
+add x0, x28, x27
+
+// store results using x2 as a base
+RVTEST_SIGUPD(x2, x0, 0x00000000)
+
+RVMODEL_IO_WRITE_STR(x31, "// Test case C - Complete\n");
+#endif
+
+----
+
+<<<
+.d.D) Test code - test case D
+
+Test case “D“ focuses on forwarding through x0. This register is hardwired to the 0 value, so a temporary non-zero result must not be passed to another instruction.
+
+----
+// ---------------------------------------------------------------------------
+#ifdef TEST_CASE_D
+//  update case variable, describes test, defines framework test requirements
+RVTEST_CASE(TEST_CASE_D ,"check ISA:=regex(.*I.*); def TEST_CASE_D=True")
+RVMODEL_IO_WRITE_STR(x31, "// Test case D - testing forwarding throught x0\n");
+
+// Addresses for test data and results
+la x1, test_D_data
+RVTEST_SIGBASE(x2, test_D_res)      //this sets x2 as sig_base and initializes it and sig_offset
+
+// Load testdata
+lw x28, 0(x1)
+
+// Register initialization
+li x27, 0xF7FF8818
+
+// Test
+add x0, x28, x27
+add x5,  x0,  x0
+
+// store results
+RVTEST_SIGUPD(x2, x0, 0x00000000)
+RVTEST_SIGUPD(x2, x5, 0x00000000)
+
+RVMODEL_IO_WRITE_STR(x31, "// Test case D - Complete\n");
+----
+
+<<<
+.d.E) Test code - test case E
+
+Test case “E“ focuses on ADD with x0. The ADD instruction performs the MOVE operation in that case.
+
+----
+// ---------------------------------------------------------------------------
+#ifdef TEST_CASE_E
+//  update case variable, describes test, defines framework test requirements
+RVTEST_CASE(TEST_CASE_E ,"check ISA:=regex(.*I.*); def TEST_CASE_E=True")
+RVMODEL_IO_WRITE_STR(x31, "// Test case E - testing moving (add with x0)\n");
+
+// Addresses for test data and results
+la x1, test_E_data
+RVTEST_SIGBASE(x2, test_E_res)      //this sets x2 as sig_base and initializes it and sig_offset
+
+// Load testdata
+lw x3, 0(x1)
+
+// Test
+add x4,   x3,  x0
+add x5,   x4,  x0
+add x6,   x0,  x5
+add x14,  x6,  x0
+add x15, x14,  x0
+add x16, x15,  x0
+add x25,  x0, x16
+add x26,  x0, x25
+add x27, x26,  x0
+
+// Store results, assert expected value
+RVTEST_SIGUPD(x2, x4,  0x36925814)
+RVTEST_SIGUPD(x2, x26, 0x36925814)
+RVTEST_SIGUPD(x2, x27, 0x36925814)
+
+RVMODEL_IO_WRITE_STR(x31, "// Test case E - Complete\n");
+
+#endif
+----
+
+Note that because all the test conditions in the above example are identical, they should have been combined into a single test case.
+
+<<<
+.d.F) Test code - section Test End
+
+Every test environment should implement at least one instance of the HALT macro. IMore than one would be implemented in cases where the test has branches or traps that cause it to end in different locations. When the macro is called, operation of DUT is stopped and a comparison to the reference results can be performed.
+
+----
+RVMODEL_IO_WRITE_STR(x31, "// Test End\n")
+// ---------------------------------------------------------------------------
+// HALT
+RVMODEL_HALT
+RVTEST_CODE_END
+----
+
+.e) Test code - section Input Data
+
+Addresses used for storing input data.
+
+----
+// Input data section.
+.data
+test_A1_data:
+.word 0
+test_A2_data:
+.word 1
+test_A3_data:
+.word -1
+test_A4_data:
+.word 0x7FFFFFFF
+test_A5_data:
+.word 0x80000000
+test_B_data:
+.word 0x0000ABCD
+test_C_data:
+.word 0x12345678
+test_D_data:
+.word 0xFEDCBA98
+test_E_data:
+.word 0x36925814
+----
+<<<
+.f) Test code - section Output Data
+
+Addresses used for storing results.
+
+----
+// Output data section.
+RVMODEL_DATA_BEGIN
+test_A1_res:
+.fill 6, 4, -1
+test_A2_res:
+.fill 6, 4, -1
+test_A3_res:
+.fill 6, 4, -1
+test_A4_res:
+.fill 6, 4, -1
+test_A5_res:
+.fill 6, 4, -1
+test_B_res:
+.fill 8, 4, -1
+test_C_res:
+.fill 1, 4, -1
+test_D_res:
+.fill 2, 4, -1
+test_E_res:
+.fill 3, 4, -1
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+----
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