rtl:utils: add async_fifo module
Signed-off-by: liangkangnan <liangkangnan@163.com>verilator
liangkangnan
parent
8bfee71fd0
commit
7993b97612
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@ -94,3 +94,4 @@
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../rtl/utils/prim_subreg_ext.sv
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../rtl/utils/prim_filter.sv
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../rtl/utils/up_counter.sv
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../rtl/utils/async_fifo.sv
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@ -0,0 +1,230 @@
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Generic asynchronous fifo for use in a variety of devices.
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module async_fifo #(
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parameter int unsigned Width = 16,
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parameter int unsigned Depth = 3,
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localparam int unsigned DepthW = $clog2(Depth+1) // derived parameter representing [0..Depth]
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) (
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// write port
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input clk_wr_i,
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input rst_wr_ni,
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input wvalid_i,
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output wready_o,
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input [Width-1:0] wdata_i,
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output [DepthW-1:0] wdepth_o,
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// read port
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input clk_rd_i,
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input rst_rd_ni,
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output rvalid_o,
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input rready_i,
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output [Width-1:0] rdata_o,
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output [DepthW-1:0] rdepth_o
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);
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localparam int unsigned PTRV_W = $clog2(Depth);
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localparam logic [PTRV_W-1:0] DepthMinus1 = PTRV_W'(Depth - 1);
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localparam int unsigned PTR_WIDTH = PTRV_W+1;
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logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
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logic [PTR_WIDTH-1:0] fifo_wptr_sync_combi, fifo_rptr_sync;
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logic [PTR_WIDTH-1:0] fifo_wptr_gray_sync, fifo_rptr_gray_sync;
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logic [PTR_WIDTH-1:0] fifo_wptr_gray, fifo_rptr_gray;
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logic fifo_incr_wptr, fifo_incr_rptr, empty;
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logic full_wclk, full_rclk;
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assign wready_o = !full_wclk;
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assign rvalid_o = !empty;
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// create the write and read pointers
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assign fifo_incr_wptr = wvalid_i & wready_o;
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assign fifo_incr_rptr = rvalid_o & rready_i;
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///////////////////
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// write pointer //
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///////////////////
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always_ff @(posedge clk_wr_i or negedge rst_wr_ni)
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if (!rst_wr_ni) begin
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fifo_wptr <= {(PTR_WIDTH){1'b0}};
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end else if (fifo_incr_wptr) begin
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if (fifo_wptr[PTR_WIDTH-2:0] == DepthMinus1) begin
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fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
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end else begin
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fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
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end
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end
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// gray-coded version
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always_ff @(posedge clk_wr_i or negedge rst_wr_ni)
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if (!rst_wr_ni) begin
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fifo_wptr_gray <= {(PTR_WIDTH){1'b0}};
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end else if (fifo_incr_wptr) begin
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if (fifo_wptr[PTR_WIDTH-2:0] == DepthMinus1) begin
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fifo_wptr_gray <= dec2gray({~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}});
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end else begin
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fifo_wptr_gray <= dec2gray(fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1});
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end
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end
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/*
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prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
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.clk_i (clk_rd_i),
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.rst_ni (rst_rd_ni),
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.d_i (fifo_wptr_gray),
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.q_o (fifo_wptr_gray_sync));
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*/
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logic [PTR_WIDTH-1:0] fifo_wptr_gray_q1, fifo_wptr_gray_q2;
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always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
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if (!rst_rd_ni) begin
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fifo_wptr_gray_q1 <= {(PTR_WIDTH){1'b0}};
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fifo_wptr_gray_q2 <= {(PTR_WIDTH){1'b0}};
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end else begin
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fifo_wptr_gray_q1 <= fifo_wptr_gray;
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fifo_wptr_gray_q2 <= fifo_wptr_gray_q1;
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end
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end
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assign fifo_wptr_gray_sync = fifo_wptr_gray_q2;
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assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
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//////////////////
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// read pointer //
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//////////////////
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always_ff @(posedge clk_rd_i or negedge rst_rd_ni)
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if (!rst_rd_ni) begin
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fifo_rptr <= {(PTR_WIDTH){1'b0}};
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end else if (fifo_incr_rptr) begin
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if (fifo_rptr[PTR_WIDTH-2:0] == DepthMinus1) begin
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fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
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end else begin
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fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
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end
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end
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// gray-coded version
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always_ff @(posedge clk_rd_i or negedge rst_rd_ni)
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if (!rst_rd_ni) begin
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fifo_rptr_gray <= {(PTR_WIDTH){1'b0}};
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end else if (fifo_incr_rptr) begin
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if (fifo_rptr[PTR_WIDTH-2:0] == DepthMinus1) begin
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fifo_rptr_gray <= dec2gray({~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}});
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end else begin
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fifo_rptr_gray <= dec2gray(fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1});
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end
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end
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/*
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prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
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.clk_i (clk_wr_i),
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.rst_ni (rst_wr_ni),
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.d_i (fifo_rptr_gray),
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.q_o (fifo_rptr_gray_sync));
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*/
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logic [PTR_WIDTH-1:0] fifo_rptr_gray_q1, fifo_rptr_gray_q2;
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always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
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if (!rst_wr_ni) begin
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fifo_rptr_gray_q1 <= {(PTR_WIDTH){1'b0}};
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fifo_rptr_gray_q2 <= {(PTR_WIDTH){1'b0}};
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end else begin
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fifo_rptr_gray_q1 <= fifo_rptr_gray;
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fifo_rptr_gray_q2 <= fifo_rptr_gray_q1;
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end
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end
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assign fifo_rptr_gray_sync = fifo_rptr_gray_q2;
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always_ff @(posedge clk_wr_i or negedge rst_wr_ni)
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if (!rst_wr_ni) begin
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fifo_rptr_sync <= {PTR_WIDTH{1'b0}};
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end else begin
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fifo_rptr_sync <= gray2dec(fifo_rptr_gray_sync);
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end
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//////////////////
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// empty / full //
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//////////////////
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assign full_wclk = (fifo_wptr == (fifo_rptr_sync ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
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assign full_rclk = (fifo_wptr_sync_combi == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
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// Current depth in the write clock side
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logic wptr_msb;
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logic rptr_sync_msb;
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logic [PTRV_W-1:0] wptr_value;
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logic [PTRV_W-1:0] rptr_sync_value;
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assign wptr_msb = fifo_wptr[PTR_WIDTH-1];
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assign rptr_sync_msb = fifo_rptr_sync[PTR_WIDTH-1];
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assign wptr_value = fifo_wptr[0+:PTRV_W];
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assign rptr_sync_value = fifo_rptr_sync[0+:PTRV_W];
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assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
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(wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
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(DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
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// Same again in the read clock side
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assign empty = (fifo_wptr_sync_combi == fifo_rptr);
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logic rptr_msb;
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logic wptr_sync_msb;
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logic [PTRV_W-1:0] rptr_value;
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logic [PTRV_W-1:0] wptr_sync_value;
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assign wptr_sync_msb = fifo_wptr_sync_combi[PTR_WIDTH-1];
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assign rptr_msb = fifo_rptr[PTR_WIDTH-1];
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assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
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assign rptr_value = fifo_rptr[0+:PTRV_W];
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assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
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(wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
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(DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
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/////////////
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// storage //
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/////////////
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logic [Width-1:0] storage [Depth];
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always_ff @(posedge clk_wr_i)
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if (fifo_incr_wptr) begin
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storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata_i;
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end
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assign rdata_o = storage[fifo_rptr[PTR_WIDTH-2:0]];
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// gray code conversion functions. algorithm walks up from 0..N-1
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// then flips the upper bit and walks down from N-1 to 0.
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function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
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logic [PTR_WIDTH-1:0] decval_sub;
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logic [PTR_WIDTH-2:0] decval_in;
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logic unused_decval_msb;
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decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
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{unused_decval_msb, decval_in} = decval[PTR_WIDTH-1] ? decval_sub : decval;
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// Was done in two assigns for low bits and top bit
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// but that generates a (bogus) verilator warning, so do in one assign
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dec2gray = {decval[PTR_WIDTH-1],
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{1'b0,decval_in[PTR_WIDTH-2:1]} ^ decval_in[PTR_WIDTH-2:0]};
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endfunction
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function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
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logic [PTR_WIDTH-2:0] dec_tmp, dec_tmp_sub;
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logic unused_decsub_msb;
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dec_tmp[PTR_WIDTH-2] = grayval[PTR_WIDTH-2];
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for (int i = PTR_WIDTH-3; i >= 0; i--)
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dec_tmp[i] = dec_tmp[i+1]^grayval[i];
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{unused_decsub_msb, dec_tmp_sub} = (PTR_WIDTH-1)'(Depth) - {1'b0, dec_tmp} - 1'b1;
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if (grayval[PTR_WIDTH-1])
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gray2dec = {1'b1,dec_tmp_sub};
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else
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gray2dec = {1'b0,dec_tmp};
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endfunction
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// TODO: assertions on full, empty, gray transitions
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endmodule
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