temp commit

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-04-30 18:27:30 +08:00
parent 53865371ce
commit 738fba1d6f
3 changed files with 9 additions and 6 deletions

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@ -29,7 +29,7 @@ module divider(
input wire start_i, // 开始信号,运算期间这个信号需要一直保持有效 input wire start_i, // 开始信号,运算期间这个信号需要一直保持有效
input wire[3:0] op_i, // 具体是哪一条指令 input wire[3:0] op_i, // 具体是哪一条指令
output reg[31:0] result_o, // 除法结果高32位是余数低32位是商 output reg[31:0] result_o, // 除法结果
output reg ready_o // 运算结束信号 output reg ready_o // 运算结束信号
); );

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@ -332,6 +332,7 @@ module exu(
.muldiv_op_divu_i(muldiv_op_divu_o), .muldiv_op_divu_i(muldiv_op_divu_o),
.muldiv_op_rem_i(muldiv_op_rem_o), .muldiv_op_rem_i(muldiv_op_rem_o),
.muldiv_op_remu_i(muldiv_op_remu_o), .muldiv_op_remu_i(muldiv_op_remu_o),
.int_stall_i(int_stall_i),
.muldiv_reg_wdata_o(muldiv_reg_wdata_o), .muldiv_reg_wdata_o(muldiv_reg_wdata_o),
.muldiv_reg_we_o(muldiv_reg_we_o), .muldiv_reg_we_o(muldiv_reg_we_o),
.muldiv_stall_o(muldiv_stall_o) .muldiv_stall_o(muldiv_stall_o)
@ -366,9 +367,9 @@ module exu(
.reg_wdata_o(reg_wdata_o) .reg_wdata_o(reg_wdata_o)
); );
assign reg_we_o = commit_reg_we_o; assign reg_we_o = commit_reg_we_o & (~int_stall_i);
assign jump_flag_o = bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o | int_assert_i; assign jump_flag_o = ((bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o) & (~int_stall_i)) | int_assert_i;
assign jump_addr_o = int_assert_i? int_addr_i: assign jump_addr_o = int_assert_i? int_addr_i:
sys_op_fence_o? next_pc_i: sys_op_fence_o? next_pc_i:
bjp_res_o; bjp_res_o;
@ -376,10 +377,10 @@ module exu(
assign csr_raddr_o = csr_addr_o; assign csr_raddr_o = csr_addr_o;
assign csr_waddr_o = csr_addr_o; assign csr_waddr_o = csr_addr_o;
assign csr_we_o = req_csr_o; assign csr_we_o = req_csr_o & (~int_stall_i);
assign csr_wdata_o = alu_res_o; assign csr_wdata_o = alu_res_o;
assign mem_we_o = mem_mem_we_o; assign mem_we_o = mem_mem_we_o & (~int_stall_i);
assign mem_wdata_o = mem_wdata; assign mem_wdata_o = mem_wdata;
assign inst_valid_o = hold_flag_o? 1'b0: inst_valid_i; assign inst_valid_o = hold_flag_o? 1'b0: inst_valid_i;

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@ -33,6 +33,8 @@ module exu_muldiv(
input wire muldiv_op_rem_i, input wire muldiv_op_rem_i,
input wire muldiv_op_remu_i, input wire muldiv_op_remu_i,
input wire int_stall_i,
output wire[31:0] muldiv_reg_wdata_o, output wire[31:0] muldiv_reg_wdata_o,
output wire muldiv_reg_we_o, output wire muldiv_reg_we_o,
output wire muldiv_stall_o output wire muldiv_stall_o
@ -41,7 +43,7 @@ module exu_muldiv(
// 除法操作 // 除法操作
wire op_div = muldiv_op_div_i | muldiv_op_divu_i | muldiv_op_rem_i | muldiv_op_remu_i; wire op_div = muldiv_op_div_i | muldiv_op_divu_i | muldiv_op_rem_i | muldiv_op_remu_i;
wire div_start = op_div & (!div_ready); wire div_start = op_div & (!div_ready) & (~int_stall_i);
wire[3:0] div_op = {muldiv_op_div_i, muldiv_op_divu_i, muldiv_op_rem_i, muldiv_op_remu_i}; wire[3:0] div_op = {muldiv_op_div_i, muldiv_op_divu_i, muldiv_op_rem_i, muldiv_op_remu_i};
wire[31:0] div_result; wire[31:0] div_result;
wire div_ready; wire div_ready;