diff --git a/rtl/core/divider.sv b/rtl/core/divider.sv
index 760cd32..6152d05 100644
--- a/rtl/core/divider.sv
+++ b/rtl/core/divider.sv
@@ -29,7 +29,7 @@ module divider(
     input wire start_i,                 // 开始信号，运算期间这个信号需要一直保持有效
     input wire[3:0] op_i,               // 具体是哪一条指令
 
-    output reg[31:0] result_o,          // 除法结果，高32位是余数，低32位是商
+    output reg[31:0] result_o,          // 除法结果
     output reg ready_o                  // 运算结束信号
 
     );
diff --git a/rtl/core/exu.sv b/rtl/core/exu.sv
index 6bb6860..7fa9c8b 100644
--- a/rtl/core/exu.sv
+++ b/rtl/core/exu.sv
@@ -332,6 +332,7 @@ module exu(
         .muldiv_op_divu_i(muldiv_op_divu_o),
         .muldiv_op_rem_i(muldiv_op_rem_o),
         .muldiv_op_remu_i(muldiv_op_remu_o),
+        .int_stall_i(int_stall_i),
         .muldiv_reg_wdata_o(muldiv_reg_wdata_o),
         .muldiv_reg_we_o(muldiv_reg_we_o),
         .muldiv_stall_o(muldiv_stall_o)
@@ -366,9 +367,9 @@ module exu(
         .reg_wdata_o(reg_wdata_o)
     );
 
-    assign reg_we_o = commit_reg_we_o;
+    assign reg_we_o = commit_reg_we_o & (~int_stall_i);
 
-    assign jump_flag_o = bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o | int_assert_i;
+    assign jump_flag_o = ((bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o) & (~int_stall_i)) | int_assert_i;
     assign jump_addr_o = int_assert_i? int_addr_i:
                          sys_op_fence_o? next_pc_i:
                          bjp_res_o;
@@ -376,10 +377,10 @@ module exu(
 
     assign csr_raddr_o = csr_addr_o;
     assign csr_waddr_o = csr_addr_o;
-    assign csr_we_o = req_csr_o;
+    assign csr_we_o = req_csr_o & (~int_stall_i);
     assign csr_wdata_o = alu_res_o;
 
-    assign mem_we_o = mem_mem_we_o;
+    assign mem_we_o = mem_mem_we_o & (~int_stall_i);
     assign mem_wdata_o = mem_wdata;
 
     assign inst_valid_o = hold_flag_o? 1'b0: inst_valid_i;
diff --git a/rtl/core/exu_muldiv.sv b/rtl/core/exu_muldiv.sv
index cda79a3..1dd06f5 100644
--- a/rtl/core/exu_muldiv.sv
+++ b/rtl/core/exu_muldiv.sv
@@ -33,6 +33,8 @@ module exu_muldiv(
     input wire muldiv_op_rem_i,
     input wire muldiv_op_remu_i,
 
+    input wire int_stall_i,
+
     output wire[31:0] muldiv_reg_wdata_o,
     output wire muldiv_reg_we_o,
     output wire muldiv_stall_o
@@ -41,7 +43,7 @@ module exu_muldiv(
 
     // 除法操作
     wire op_div = muldiv_op_div_i | muldiv_op_divu_i | muldiv_op_rem_i | muldiv_op_remu_i;
-    wire div_start = op_div & (!div_ready);
+    wire div_start = op_div & (!div_ready) & (~int_stall_i);
     wire[3:0] div_op = {muldiv_op_div_i, muldiv_op_divu_i, muldiv_op_rem_i, muldiv_op_remu_i};
     wire[31:0] div_result;
     wire div_ready;