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rtl: add generate block name 

Signed-off-by: liangkangnan <liangkangnan@163.com>
bram
Blue Liang 2020-10-26 17:01:04 +08:00
parent eb5647915a
commit 60a4f7d6df
3 changed files with 41 additions and 41 deletions
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62
rtl/sys_bus/rib.v
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@ -136,42 +136,42 @@ module rib #(
genvar i;
generate
if (MASTER_NUM == 2) begin
if (MASTER_NUM == 2) begin: if_m_num_2
assign master_req = {m0_req_vld_i, m1_req_vld_i};
assign master_rsp_rdy = {m0_rsp_rdy_i, m1_rsp_rdy_i};
assign master_we = {m0_we_i, m1_we_i};
wire[32*MASTER_NUM-1:0] m_addr = {m0_addr_i, m1_addr_i};
wire[32*MASTER_NUM-1:0] m_data = {m0_data_i, m1_data_i};
wire[4*MASTER_NUM-1:0] m_sel = {m0_sel_i, m1_sel_i};
for (i = 0; i < MASTER_NUM; i = i + 1) begin
for (i = 0; i < MASTER_NUM; i = i + 1) begin: for_m_num_2
assign master_addr[i] = m_addr[(i+1)*32-1:32*i];
assign master_data[i] = m_data[(i+1)*32-1:32*i];
assign master_sel[i] = m_sel[(i+1)*4-1:4*i];
end
end
if (MASTER_NUM == 3) begin
if (MASTER_NUM == 3) begin: if_m_num_3
assign master_req = {m0_req_vld_i, m1_req_vld_i, m2_req_vld_i};
assign master_rsp_rdy = {m0_rsp_rdy_i, m1_rsp_rdy_i, m2_rsp_rdy_i};
assign master_we = {m0_we_i, m1_we_i, m2_we_i};
wire[32*MASTER_NUM-1:0] m_addr = {m0_addr_i, m1_addr_i, m2_addr_i};
wire[32*MASTER_NUM-1:0] m_data = {m0_data_i, m1_data_i, m2_data_i};
wire[4*MASTER_NUM-1:0] m_sel = {m0_sel_i, m1_sel_i, m2_sel_i};
for (i = 0; i < MASTER_NUM; i = i + 1) begin
for (i = 0; i < MASTER_NUM; i = i + 1) begin: for_m_num_3
assign master_addr[i] = m_addr[(i+1)*32-1:32*i];
assign master_data[i] = m_data[(i+1)*32-1:32*i];
assign master_sel[i] = m_sel[(i+1)*4-1:4*i];
end
end
if (MASTER_NUM == 4) begin
if (MASTER_NUM == 4) begin: if_m_num_4
assign master_req = {m0_req_vld_i, m1_req_vld_i, m2_req_vld_i, m3_req_vld_i};
assign master_rsp_rdy = {m0_rsp_rdy_i, m1_rsp_rdy_i, m2_rsp_rdy_i, m3_rsp_rdy_i};
assign master_we = {m0_we_i, m1_we_i, m2_we_i, m3_we_i};
wire[32*MASTER_NUM-1:0] m_addr = {m0_addr_i, m1_addr_i, m2_addr_i, m3_addr_i};
wire[32*MASTER_NUM-1:0] m_data = {m0_data_i, m1_data_i, m2_data_i, m3_data_i};
wire[4*MASTER_NUM-1:0] m_sel = {m0_sel_i, m1_sel_i, m2_sel_i, m3_sel_i};
for (i = 0; i < MASTER_NUM; i = i + 1) begin
for (i = 0; i < MASTER_NUM; i = i + 1) begin: for_m_num_4
assign master_addr[i] = m_addr[(i+1)*32-1:32*i];
assign master_data[i] = m_data[(i+1)*32-1:32*i];
assign master_sel[i] = m_sel[(i+1)*4-1:4*i];
@ -182,10 +182,10 @@ module rib #(
wire[MASTER_NUM-1:0] master_sel_vec;
// 优先级仲裁机制，LSB优先级最高，MSB优先级最低
for (i = 0; i < MASTER_NUM; i = i + 1) begin
if (i == 0) begin
for (i = 0; i < MASTER_NUM; i = i + 1) begin: m_arb
if (i == 0) begin: m_is_0
assign master_req_vec[i] = 1'b1;
end else begin
end else begin: m_is_not_0
assign master_req_vec[i] = ~(|master_req[i-1:0]);
end
assign master_sel_vec[i] = master_req_vec[i] & master_req[i];
@ -200,14 +200,14 @@ module rib #(
integer j;
always @ (*) begin
always @ (*) begin: m_out
mux_m_addr = 32'h0;
mux_m_data = 32'h0;
mux_m_sel = 4'h0;
mux_m_req_vld = 1'b0;
mux_m_rsp_rdy = 1'b0;
mux_m_we = 1'b0;
for (j = 0; j < MASTER_NUM; j = j + 1) begin
for (j = 0; j < MASTER_NUM; j = j + 1) begin: m_sig_out
mux_m_addr = mux_m_addr | ({32{master_sel_vec[j]}} & master_addr[j]);
mux_m_data = mux_m_data | ({32{master_sel_vec[j]}} & master_data[j]);
mux_m_sel = mux_m_sel | ({4 {master_sel_vec[j]}} & master_sel[j]);
@ -223,7 +223,7 @@ module rib #(
// 访问地址的最高4位决定要访问的是哪一个从设备
// 因此最多支持16个从设备
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: s_sel
assign slave_sel[i] = (mux_m_addr[31:28] == i);
end
@ -231,38 +231,38 @@ module rib #(
wire[SLAVE_NUM-1:0] slave_rsp_vld;
wire[31:0] slave_data[SLAVE_NUM-1:0];
if (SLAVE_NUM == 2) begin
if (SLAVE_NUM == 2) begin: if_s_num_2
assign slave_req_rdy = {s1_req_rdy_i, s0_req_rdy_i};
assign slave_rsp_vld = {s1_rsp_vld_i, s0_rsp_vld_i};
wire[32*SLAVE_NUM-1:0] s_data = {s1_data_i, s0_data_i};
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: for_s_num_2
assign slave_data[i] = s_data[(i+1)*32-1:32*i];
end
end
if (SLAVE_NUM == 3) begin
if (SLAVE_NUM == 3) begin: if_s_num_3
assign slave_req_rdy = {s2_req_rdy_i, s1_req_rdy_i, s0_req_rdy_i};
assign slave_rsp_vld = {s2_rsp_vld_i, s1_rsp_vld_i, s0_rsp_vld_i};
wire[32*SLAVE_NUM-1:0] s_data = {s2_data_i, s1_data_i, s0_data_i};
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: for_s_num_3
assign slave_data[i] = s_data[(i+1)*32-1:32*i];
end
end
if (SLAVE_NUM == 4) begin
if (SLAVE_NUM == 4) begin: if_s_num_4
assign slave_req_rdy = {s3_req_rdy_i, s2_req_rdy_i, s1_req_rdy_i, s0_req_rdy_i};
assign slave_rsp_vld = {s3_rsp_vld_i, s2_rsp_vld_i, s1_rsp_vld_i, s0_rsp_vld_i};
wire[32*SLAVE_NUM-1:0] s_data = {s3_data_i, s2_data_i, s1_data_i, s0_data_i};
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: for_s_num_4
assign slave_data[i] = s_data[(i+1)*32-1:32*i];
end
end
if (SLAVE_NUM == 5) begin
if (SLAVE_NUM == 5) begin: if_s_num_5
assign slave_req_rdy = {s4_req_rdy_i, s3_req_rdy_i, s2_req_rdy_i, s1_req_rdy_i, s0_req_rdy_i};
assign slave_rsp_vld = {s4_rsp_vld_i, s3_rsp_vld_i, s2_rsp_vld_i, s1_rsp_vld_i, s0_rsp_vld_i};
wire[32*SLAVE_NUM-1:0] s_data = {s4_data_i, s3_data_i, s2_data_i, s1_data_i, s0_data_i};
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: for_s_num_5
assign slave_data[i] = s_data[(i+1)*32-1:32*i];
end
end
@ -271,11 +271,11 @@ module rib #(
reg mux_s_req_rdy;
reg mux_s_rsp_vld;
always @ (*) begin
always @ (*) begin: s_out
mux_s_data = 32'h0;
mux_s_req_rdy = 1'b0;
mux_s_rsp_vld = 1'b0;
for (j = 0; j < SLAVE_NUM; j = j + 1) begin
for (j = 0; j < SLAVE_NUM; j = j + 1) begin: s_sig_out
mux_s_data = mux_s_data | ({32{slave_sel[j]}} & slave_data[j]);
mux_s_req_rdy = mux_s_req_rdy | ({1 {slave_sel[j]}} & slave_req_rdy[j]);
mux_s_rsp_vld = mux_s_rsp_vld | ({1 {slave_sel[j]}} & slave_rsp_vld[j]);
@ -288,25 +288,25 @@ module rib #(
wire[MASTER_NUM-1:0] demux_m_rsp_vld;
wire[32*MASTER_NUM-1:0] demux_m_data;
for (i = 0; i < MASTER_NUM; i = i + 1) begin
for (i = 0; i < MASTER_NUM; i = i + 1) begin: demux_m_sig
assign demux_m_req_rdy[i] = {1 {master_sel_vec[i]}} & mux_s_req_rdy;
assign demux_m_rsp_vld[i] = {1 {master_sel_vec[i]}} & mux_s_rsp_vld;
assign demux_m_data[(i+1)*32-1:32*i] = {32{master_sel_vec[i]}} & mux_s_data;
end
if (MASTER_NUM == 2) begin
if (MASTER_NUM == 2) begin: demux_m_sig_2
assign {m0_req_rdy_o, m1_req_rdy_o} = demux_m_req_rdy;
assign {m0_rsp_vld_o, m1_rsp_vld_o} = demux_m_rsp_vld;
assign {m0_data_o, m1_data_o} = demux_m_data;
end
if (MASTER_NUM == 3) begin
if (MASTER_NUM == 3) begin: demux_m_sig_3
assign {m0_req_rdy_o, m1_req_rdy_o, m2_req_rdy_o} = demux_m_req_rdy;
assign {m0_rsp_vld_o, m1_rsp_vld_o, m2_rsp_vld_o} = demux_m_rsp_vld;
assign {m0_data_o, m1_data_o, m2_data_o} = demux_m_data;
end
if (MASTER_NUM == 4) begin
if (MASTER_NUM == 4) begin: demux_m_sig_4
assign {m0_req_rdy_o, m1_req_rdy_o, m2_req_rdy_o, m3_req_rdy_o} = demux_m_req_rdy;
assign {m0_rsp_vld_o, m1_rsp_vld_o, m2_rsp_vld_o, m3_rsp_vld_o} = demux_m_rsp_vld;
assign {m0_data_o, m1_data_o, m2_data_o, m3_data_o} = demux_m_data;
@ -321,7 +321,7 @@ module rib #(
wire[SLAVE_NUM-1:0] demux_s_rsp_rdy;
wire[SLAVE_NUM-1:0] demux_s_we;
for (i = 0; i < SLAVE_NUM; i = i + 1) begin
for (i = 0; i < SLAVE_NUM; i = i + 1) begin: demux_s_sig
// 去掉外设基地址，只保留offset
assign demux_s_addr[(i+1)*32-1:32*i] = {32{slave_sel[i]}} & {4'h0, mux_m_addr[27:0]};
assign demux_s_data[(i+1)*32-1:32*i] = {32{slave_sel[i]}} & mux_m_data;
@ -331,7 +331,7 @@ module rib #(
assign demux_s_we[i] = {1 {slave_sel[i]}} & mux_m_we;
end
if (SLAVE_NUM == 2) begin
if (SLAVE_NUM == 2) begin: demux_s_sig_2
assign {s1_addr_o, s0_addr_o} = demux_s_addr;
assign {s1_data_o, s0_data_o} = demux_s_data;
assign {s1_sel_o, s0_sel_o} = demux_s_sel;
@ -340,7 +340,7 @@ module rib #(
assign {s1_we_o, s0_we_o} = demux_s_we;
end
if (SLAVE_NUM == 3) begin
if (SLAVE_NUM == 3) begin: demux_s_sig_3
assign {s2_addr_o, s1_addr_o, s0_addr_o} = demux_s_addr;
assign {s2_data_o, s1_data_o, s0_data_o} = demux_s_data;
assign {s2_sel_o, s1_sel_o, s0_sel_o} = demux_s_sel;
@ -349,7 +349,7 @@ module rib #(
assign {s2_we_o, s1_we_o, s0_we_o} = demux_s_we;
end
if (SLAVE_NUM == 4) begin
if (SLAVE_NUM == 4) begin: demux_s_sig_4
assign {s3_addr_o, s2_addr_o, s1_addr_o, s0_addr_o} = demux_s_addr;
assign {s3_data_o, s2_data_o, s1_data_o, s0_data_o} = demux_s_data;
assign {s3_sel_o, s2_sel_o, s1_sel_o, s0_sel_o} = demux_s_sel;
@ -358,7 +358,7 @@ module rib #(
assign {s3_we_o, s2_we_o, s1_we_o, s0_we_o} = demux_s_we;
end
if (SLAVE_NUM == 5) begin
if (SLAVE_NUM == 5) begin: demux_s_sig_5
assign {s4_addr_o, s3_addr_o, s2_addr_o, s1_addr_o, s0_addr_o} = demux_s_addr;
assign {s4_data_o, s3_data_o, s2_data_o, s1_data_o, s0_data_o} = demux_s_data;
assign {s4_sel_o, s3_sel_o, s2_sel_o, s1_sel_o, s0_sel_o} = demux_s_sel;

6
rtl/utils/gen_buf.v
View File

@ -32,10 +32,10 @@ module gen_ticks_sync #(
genvar i;
generate
for (i = 0; i < DP; i = i + 1) begin
if (i == 0) begin
for (i = 0; i < DP; i = i + 1) begin: ticks_sync
if (i == 0) begin: dp_is_0
gen_rst_0_dff #(DW) rst_0_dff(clk, rst_n, din, sync_dat[0]);
end else begin
end else begin: dp_is_not_0
gen_rst_0_dff #(DW) rst_0_dff(clk, rst_n, sync_dat[i-1], sync_dat[i]);
end
end

14
rtl/utils/gen_ram.v
View File

@ -52,16 +52,16 @@ module gen_ram #(
genvar i;
generate
for (i = 0; i < MW; i = i + 1) begin
if ((8 * i + 8) > DW) begin
always @ (posedge clk) begin
if (wen[i]) begin
for (i = 0; i < MW; i = i + 1) begin: sel_width
if ((8 * i + 8) > DW) begin: i_gt_8
always @ (posedge clk) begin: i_gt_8_ff
if (wen[i]) begin: gt_8_wen
ram[addr_i][DW-1:8*i] <= data_i[DW-1:8*i];
end
end
end else begin
always @ (posedge clk) begin
if (wen[i]) begin
end else begin: i_lt_8
always @ (posedge clk) begin: i_lt_8_ff
if (wen[i]) begin: lt_8_wen
ram[addr_i][8*i+7:8*i] <= data_i[8*i+7:8*i];
end
end