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fpga: constrs: add one more gpio 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-06-14 10:41:52 +08:00
parent 2619f26eae
commit 5c70814fc6
1 changed files with 22 additions and 5 deletions
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27
fpga/constrs/tinyriscv.xdc
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@ -1,52 +1,69 @@
# 时钟约束50MHz
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {clk}]; set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {clk}];
create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports {clk}]; create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports {clk}];
# 时钟引脚
set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN N14 [get_ports clk] set_property PACKAGE_PIN N14 [get_ports clk]
# 复位引脚
set_property IOSTANDARD LVCMOS33 [get_ports rst] set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN L13 [get_ports rst] set_property PACKAGE_PIN L13 [get_ports rst]
# 程序执行完毕指示引脚
set_property IOSTANDARD LVCMOS33 [get_ports over] set_property IOSTANDARD LVCMOS33 [get_ports over]
set_property PACKAGE_PIN M16 [get_ports over] set_property PACKAGE_PIN M16 [get_ports over]
# 程序执行成功指示引脚
set_property IOSTANDARD LVCMOS33 [get_ports succ] set_property IOSTANDARD LVCMOS33 [get_ports succ]
set_property PACKAGE_PIN N16 [get_ports succ] set_property PACKAGE_PIN N16 [get_ports succ]
# CPU停住指示引脚
set_property IOSTANDARD LVCMOS33 [get_ports halted_ind] set_property IOSTANDARD LVCMOS33 [get_ports halted_ind]
set_property PACKAGE_PIN P15 [get_ports halted_ind] set_property PACKAGE_PIN P15 [get_ports halted_ind]
# 串口发送引脚
set_property IOSTANDARD LVCMOS33 [get_ports tx_pin] set_property IOSTANDARD LVCMOS33 [get_ports tx_pin]
set_property PACKAGE_PIN M6 [get_ports tx_pin] set_property PACKAGE_PIN M6 [get_ports tx_pin]
set_property IOSTANDARD LVCMOS33 [get_ports io_pin] # GPIO0引脚
set_property PACKAGE_PIN P16 [get_ports io_pin] set_property IOSTANDARD LVCMOS33 [get_ports {gpio[0]}]
set_property PACKAGE_PIN P16 [get_ports {gpio[0]}]
# JTAG pin # GPIO1引脚
set_property IOSTANDARD LVCMOS33 [get_ports {gpio[1]}]
set_property PACKAGE_PIN T15 [get_ports {gpio[1]}]
# JTAG TCK引脚
set_property IOSTANDARD LVCMOS33 [get_ports jtag_TCK] set_property IOSTANDARD LVCMOS33 [get_ports jtag_TCK]
set_property PACKAGE_PIN N11 [get_ports jtag_TCK] set_property PACKAGE_PIN N11 [get_ports jtag_TCK]
create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK}]; create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK}];
# JTAG TMS引脚
set_property IOSTANDARD LVCMOS33 [get_ports jtag_TMS] set_property IOSTANDARD LVCMOS33 [get_ports jtag_TMS]
set_property PACKAGE_PIN N3 [get_ports jtag_TMS] set_property PACKAGE_PIN N3 [get_ports jtag_TMS]
# JTAG TDI引脚
set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDI] set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDI]
set_property PACKAGE_PIN N2 [get_ports jtag_TDI] set_property PACKAGE_PIN N2 [get_ports jtag_TDI]
# JTAG TDO引脚
set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDO] set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDO]
set_property PACKAGE_PIN M1 [get_ports jtag_TDO] set_property PACKAGE_PIN M1 [get_ports jtag_TDO]
# SPI pin # SPI MISO引脚
set_property IOSTANDARD LVCMOS33 [get_ports spi_miso] set_property IOSTANDARD LVCMOS33 [get_ports spi_miso]
set_property PACKAGE_PIN P1 [get_ports spi_miso] set_property PACKAGE_PIN P1 [get_ports spi_miso]
# SPI MOSI引脚
set_property IOSTANDARD LVCMOS33 [get_ports spi_mosi] set_property IOSTANDARD LVCMOS33 [get_ports spi_mosi]
set_property PACKAGE_PIN N1 [get_ports spi_mosi] set_property PACKAGE_PIN N1 [get_ports spi_mosi]
# SPI SS引脚
set_property IOSTANDARD LVCMOS33 [get_ports spi_ss] set_property IOSTANDARD LVCMOS33 [get_ports spi_ss]
set_property PACKAGE_PIN M5 [get_ports spi_ss] set_property PACKAGE_PIN M5 [get_ports spi_ss]
# SPI CLK引脚
set_property IOSTANDARD LVCMOS33 [get_ports spi_clk] set_property IOSTANDARD LVCMOS33 [get_ports spi_clk]
set_property PACKAGE_PIN N4 [get_ports spi_clk] set_property PACKAGE_PIN N4 [get_ports spi_clk]