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sim: add CFLAGS VL_DEBUG 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2022-01-05 17:30:29 +08:00
parent 92e89292b1
commit 5b7b657384
1 changed files with 1 additions and 1 deletions
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2
sim/Makefile
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@ -6,7 +6,7 @@ MAKE := make
VERILATOR := verilator VERILATOR := verilator
VERI_FLAGS += +vcd VERI_FLAGS += +vcd
VERI_CFLAGS += VERI_CFLAGS += -DVL_DEBUG
VERI_VFLAGS += -DTRACE_ENABLED VERI_VFLAGS += -DTRACE_ENABLED