zcy
/
tinyriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

temp commit 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-04-30 16:41:24 +08:00
parent dfa8bf490e
commit 53865371ce
4 changed files with 70 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/top/tinyriscv_soc_top.sv
View File

@ -219,7 +219,7 @@ module tinyriscv_soc_top(
`ifdef VERILATOR
sim_jtag #(
.TICK_DELAY(1),
.TICK_DELAY(10),
.PORT(9999)
) u_sim_jtag (
.clock ( clk ),

1
sim/jtag_compliance_test.cfg
View File

@ -21,6 +21,7 @@ riscv set_command_timeout_sec 2000
# prefer to use sba for system bus access
riscv set_prefer_sba on
riscv set_enable_virt2phys off
# dump jtag chain
scan_chain

1
sim/jtag_debug.cfg
View File

@ -21,6 +21,7 @@ riscv set_command_timeout_sec 2000
# prefer to use sba for system bus access
riscv set_prefer_sba on
riscv set_enable_virt2phys off
# dump jtag chain
scan_chain

57
sim/tb_top_verilator.cpp
View File

@ -1,21 +1,3 @@
// Copyright 2018 Robert Balas <balasr@student.ethz.ch>
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Top level wrapper for a verilator RI5CY testbench
// Contributor: Robert Balas <balasr@student.ethz.ch>
#include "svdpi.h"
#include "Vtb_top_verilator__Dpi.h"
#include "Vtb_top_verilator.h"
@ -30,7 +12,6 @@
#include <cstdint>
#include <cerrno>
//void dump_memory();
double sc_time_stamp();
static vluint64_t t = 0;
@ -42,36 +23,35 @@ int main(int argc, char **argv, char **env)
Verilated::traceEverOn(true);
top = new Vtb_top_verilator();
//svSetScope(svGetScopeFromName(
// "TOP.tb_top_verilator.u_ram.ram"));
//Verilated::scopesDump();
#ifdef VCD_TRACE
VerilatedVcdC *tfp = new VerilatedVcdC;
top->trace(tfp, 99);
tfp->open("verilator_tb.vcd");
#endif
top->clk_i = 0;
top->rst_ni = 0;
top->eval();
//dump_memory();
while (!Verilated::gotFinish()) {
if (t > 40)
top->rst_ni = 1;
top->clk_i = !top->clk_i;
top->eval();
#ifdef VCD_TRACE
tfp->dump(t);
#endif
t += 5;
//if (t > 2000)
// break;
}
#ifdef VCD_TRACE
tfp->close();
#endif
delete top;
exit(0);
}
@ -80,28 +60,3 @@ double sc_time_stamp()
{
return t;
}
/*
void dump_memory()
{
errno = 0;
std::ofstream mem_file;
svLogicVecVal addr = {0};
mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit);
try {
mem_file.open("memory_dump.bin");
for (size_t i = 0; i < 1048576; i++) {
addr.aval = i;
uint32_t val = read_byte(&addr);
mem_file << std::setfill('0') << std::setw(2) << std::hex << val
<< std::endl;
}
mem_file.close();
std::cout << "finished dumping memory" << std::endl;
} catch (std::ofstream::failure e) {
std::cerr << "exception opening/reading/closing file memory_dump.bin\n";
}
}
*/