From 4958cb66c2d89aa6d3dcc8e3e142bed40c593675 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sat, 6 Aug 2022 14:32:56 +0800
Subject: [PATCH] rtl: top: move out sim_jtag module

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl/top/tinyriscv_soc_top.sv | 48 +++---------------------------------
 sim/tb_top_verilator.cpp     |  8 ++++--
 sim/tb_top_verilator.sv      | 42 ++++++++++++++++++++++++++++---
 3 files changed, 48 insertions(+), 50 deletions(-)

diff --git a/rtl/top/tinyriscv_soc_top.sv b/rtl/top/tinyriscv_soc_top.sv
index eb85771..9922386 100644
--- a/rtl/top/tinyriscv_soc_top.sv
+++ b/rtl/top/tinyriscv_soc_top.sv
@@ -100,17 +100,7 @@ module tinyriscv_soc_top #(
     wire [31:0]    slave_addr_mask  [SLAVES];
     wire [31:0]    slave_addr_base  [SLAVES];
 
-`ifdef VERILATOR
-    wire           sim_jtag_tck;
-    wire           sim_jtag_tms;
-    wire           sim_jtag_tdi;
-    wire           sim_jtag_trstn;
-    wire           sim_jtag_tdo;
-    wire [31:0]    sim_jtag_exit;
-`endif
-
     wire clk;
-
     wire ndmreset;
     wire ndmreset_n;
     wire debug_req;
@@ -641,6 +631,7 @@ module tinyriscv_soc_top #(
     );
 `endif
 
+    // 内部总线
     obi_interconnect #(
         .MASTERS(MASTERS),
         .SLAVES(SLAVES)
@@ -679,6 +670,7 @@ module tinyriscv_soc_top #(
     );
 `endif
 
+    // 复位信号产生
     rst_gen #(
         .RESET_FIFO_DEPTH(5)
     ) u_rst (
@@ -689,7 +681,7 @@ module tinyriscv_soc_top #(
 
     assign slave_addr_mask[JtagDevice] = `DEBUG_ADDR_MASK;
     assign slave_addr_base[JtagDevice] = `DEBUG_ADDR_BASE;
-    // JTAG module
+    // JTAG模块
     jtag_top #(
 
     ) u_jtag (
@@ -698,19 +690,11 @@ module tinyriscv_soc_top #(
         .debug_req_o        (debug_req),
         .ndmreset_o         (ndmreset),
         .halted_o           (core_halted),
-`ifdef VERILATOR
-        .jtag_tck_i         (sim_jtag_tck),
-        .jtag_tdi_i         (sim_jtag_tdi),
-        .jtag_tms_i         (sim_jtag_tms),
-        .jtag_trst_ni       (sim_jtag_trstn),
-        .jtag_tdo_o         (sim_jtag_tdo),
-`else
         .jtag_tck_i         (jtag_TCK_pin),
         .jtag_tdi_i         (jtag_TDI_pin),
         .jtag_tms_i         (jtag_TMS_pin),
         .jtag_trst_ni       (rst_ext_ni),
         .jtag_tdo_o         (jtag_TDO_pin),
-`endif
         .master_req_o       (master_req[JtagHost]),
         .master_gnt_i       (master_gnt[JtagHost]),
         .master_rvalid_i    (master_rvalid[JtagHost]),
@@ -730,30 +714,4 @@ module tinyriscv_soc_top #(
         .slave_rdata_o      (slave_rdata[JtagDevice])
     );
 
-`ifdef VERILATOR
-    sim_jtag #(
-        .TICK_DELAY(10),
-        .PORT(9999)
-    ) u_sim_jtag (
-        .clock                ( clk                  ),
-        .reset                ( ~rst_ext_ni          ),
-        .enable               ( 1'b1                 ),
-        .init_done            ( rst_ext_ni           ),
-        .jtag_TCK             ( sim_jtag_tck         ),
-        .jtag_TMS             ( sim_jtag_tms         ),
-        .jtag_TDI             ( sim_jtag_tdi         ),
-        .jtag_TRSTn           ( sim_jtag_trstn       ),
-        .jtag_TDO_data        ( sim_jtag_tdo         ),
-        .jtag_TDO_driven      ( 1'b1                 ),
-        .exit                 ( sim_jtag_exit        )
-    );
-
-    always @ (*) begin
-        if (sim_jtag_exit) begin
-            $display("jtag exit...");
-            $finish(2);
-        end
-    end
-`endif
-
 endmodule
diff --git a/sim/tb_top_verilator.cpp b/sim/tb_top_verilator.cpp
index 57d6944..5c4de3d 100644
--- a/sim/tb_top_verilator.cpp
+++ b/sim/tb_top_verilator.cpp
@@ -35,8 +35,12 @@ int main(int argc, char **argv, char **env)
     top->eval();
 
     while (!Verilated::gotFinish()) {
-        if (t > 40)
-            top->rst_ni = 1;
+        if (t < 50)
+            top->rst_ni         = 1;
+        else if (t < 100)
+            top->rst_ni         = 0;
+        else if (t < 150)
+            top->rst_ni         = 1;
 
         top->clk_i = !top->clk_i;
         top->eval();
diff --git a/sim/tb_top_verilator.sv b/sim/tb_top_verilator.sv
index 69fe6a0..230acb9 100644
--- a/sim/tb_top_verilator.sv
+++ b/sim/tb_top_verilator.sv
@@ -105,15 +105,51 @@ module tb_top_verilator #(
         end
     end
 
+    wire           sim_jtag_tck;
+    wire           sim_jtag_tms;
+    wire           sim_jtag_tdi;
+    wire           sim_jtag_trstn;
+    wire           sim_jtag_tdo;
+    wire [31:0]    sim_jtag_exit;
+
     tinyriscv_soc_top #(
         .TRACE_ENABLE(1'b1)
     ) u_tinyriscv_soc_top (
-        .clk_50m_i(clk_i),
-        .rst_ext_ni(rst_ni),
+        .clk_50m_i     (clk_i),
+        .rst_ext_ni    (rst_ni),
         .dump_wave_en_o(dump_wave_en_o),
-        .halted_ind_pin(halted)
+        .halted_ind_pin(halted),
+        .jtag_TCK_pin  (sim_jtag_tck),
+        .jtag_TMS_pin  (sim_jtag_tms),
+        .jtag_TDI_pin  (sim_jtag_tdi),
+        .jtag_TDO_pin  (sim_jtag_tdo)
     );
 
+    sim_jtag #(
+        .TICK_DELAY(10),
+        .PORT(9999)
+    ) u_sim_jtag (
+        .clock                ( clk_i                ),
+        .reset                ( ~rst_ni              ),
+        .enable               ( 1'b1                 ),
+        .init_done            ( rst_ni               ),
+        .jtag_TCK             ( sim_jtag_tck         ),
+        .jtag_TMS             ( sim_jtag_tms         ),
+        .jtag_TDI             ( sim_jtag_tdi         ),
+        .jtag_TRSTn           ( sim_jtag_trstn       ),
+        .jtag_TDO_data        ( sim_jtag_tdo         ),
+        .jtag_TDO_driven      ( 1'b1                 ),
+        .exit                 ( sim_jtag_exit        )
+    );
+
+    always @ (*) begin
+        if (sim_jtag_exit) begin
+            $display("jtag exit...");
+            $finish(2);
+        end
+    end
+
+    // 默认不显示寄存器值
     wire display_regs = 1'b0;
 
     wire write_gpr_reg = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.we_i;