From 43aca8195c10c3bbdff7b996ba76a73a83740b19 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sat, 25 Apr 2020 17:08:46 +0800
Subject: [PATCH] add clint hold input signal

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl/core/ctrl.v | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/rtl/core/ctrl.v b/rtl/core/ctrl.v
index 6e719b2..9a2aaad 100644
--- a/rtl/core/ctrl.v
+++ b/rtl/core/ctrl.v
@@ -33,6 +33,9 @@ module ctrl(
     // from jtag
     input wire jtag_halt_flag_i,
 
+    // from clint
+    input wire hold_flag_clint_i,
+
     output reg[`Hold_Flag_Bus] hold_flag_o,
 
     // to pc_reg
@@ -53,7 +56,7 @@ module ctrl(
             // 默认不暂停
             hold_flag_o <= `Hold_None;
             // 按优先级处理不同模块的请求
-            if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin
+            if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin
                 // 暂停整条流水线
                 hold_flag_o <= `Hold_Id;
             end else if (hold_flag_rib_i == `HoldEnable) begin