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rtl:pinmux: add more spi mux 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-09-17 09:06:47 +08:00
parent d40f39a091
commit 3903d9e7f4
3 changed files with 246 additions and 228 deletions
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8
fpga/xilinx/constrs/tinyriscv.xdc
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@ -64,13 +64,13 @@ set_property PACKAGE_PIN T15 [get_ports {io_pins[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_pins[2]}]
set_property PACKAGE_PIN P5 [get_ports {io_pins[2]}]
set_property PACKAGE_PIN T13 [get_ports {io_pins[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_pins[1]}]
set_property PACKAGE_PIN L5 [get_ports {io_pins[1]}]
set_property PACKAGE_PIN R13 [get_ports {io_pins[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_pins[4]}]
set_property PACKAGE_PIN M2 [get_ports {io_pins[4]}]
set_property PACKAGE_PIN R7 [get_ports {io_pins[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_pins[5]}]
set_property PACKAGE_PIN N12 [get_ports {io_pins[5]}]
set_property PACKAGE_PIN R6 [get_ports {io_pins[5]}]
# JTAG TCK引脚

60
rtl/perips/pinmux/pinmux_core.sv
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@ -153,10 +153,10 @@ module pinmux_core #(
io_val_o[1] = uart_rx_val_i[1];
io_oe_o[1] = uart_rx_oe_i[1];
end
// GPIO1
// SPI_DQ0
2'b11: begin
io_val_o[1] = gpio_val_i[1];
io_oe_o[1] = gpio_oe_i[1];
io_val_o[1] = spi_dq_val_i[0][0];
io_oe_o[1] = spi_dq_oe_i[0][0];
end
default: ;
endcase
@ -183,10 +183,10 @@ module pinmux_core #(
io_val_o[2] = uart_rx_val_i[2];
io_oe_o[2] = uart_rx_oe_i[2];
end
// GPIO2
// SPI_DQ1
2'b11: begin
io_val_o[2] = gpio_val_i[2];
io_oe_o[2] = gpio_oe_i[2];
io_val_o[2] = spi_dq_val_i[0][1];
io_oe_o[2] = spi_dq_oe_i[0][1];
end
default: ;
endcase
@ -243,10 +243,10 @@ module pinmux_core #(
io_val_o[4] = uart_rx_val_i[1];
io_oe_o[4] = uart_rx_oe_i[1];
end
// GPIO4
// SPI_DQ2
2'b11: begin
io_val_o[4] = gpio_val_i[4];
io_oe_o[4] = gpio_oe_i[4];
io_val_o[4] = spi_dq_val_i[0][2];
io_oe_o[4] = spi_dq_oe_i[0][2];
end
default: ;
endcase
@ -273,10 +273,10 @@ module pinmux_core #(
io_val_o[5] = uart_rx_val_i[2];
io_oe_o[5] = uart_rx_oe_i[2];
end
// GPIO5
// SPI_DQ3
2'b11: begin
io_val_o[5] = gpio_val_i[5];
io_oe_o[5] = gpio_oe_i[5];
io_val_o[5] = spi_dq_val_i[0][3];
io_oe_o[5] = spi_dq_oe_i[0][3];
end
default: ;
endcase
@ -303,10 +303,10 @@ module pinmux_core #(
io_val_o[6] = i2c_sda_val_i[0];
io_oe_o[6] = i2c_sda_oe_i[0];
end
// GPIO6
// SPI_CLK
2'b11: begin
io_val_o[6] = gpio_val_i[6];
io_oe_o[6] = gpio_oe_i[6];
io_val_o[6] = spi_clk_val_i[0];
io_oe_o[6] = spi_clk_oe_i[0];
end
default: ;
endcase
@ -363,10 +363,10 @@ module pinmux_core #(
io_val_o[8] = i2c_sda_val_i[0];
io_oe_o[8] = i2c_sda_oe_i[0];
end
// GPIO8
// SPI_SS
2'b11: begin
io_val_o[8] = gpio_val_i[8];
io_oe_o[8] = gpio_oe_i[8];
io_val_o[8] = spi_ss_val_i[0];
io_oe_o[8] = spi_ss_oe_i[0];
end
default: ;
endcase
@ -591,12 +591,24 @@ module pinmux_core #(
(io9_mux == 2'b10) ? io_val_i[9] :
1'b0;
assign spi_clk_val_o[0] = (io10_mux == 2'b01) ? io_val_i[10] : 1'b0;
assign spi_ss_val_o[0] = (io11_mux == 2'b01) ? io_val_i[11] : 1'b0;
assign spi_dq_val_o[0][0] = (io12_mux == 2'b01) ? io_val_i[12] : 1'b0;
assign spi_dq_val_o[0][1] = (io13_mux == 2'b01) ? io_val_i[13] : 1'b0;
assign spi_dq_val_o[0][2] = (io14_mux == 2'b01) ? io_val_i[14] : 1'b0;
assign spi_dq_val_o[0][3] = (io15_mux == 2'b01) ? io_val_i[15] : 1'b0;
assign spi_clk_val_o[0] = (io10_mux == 2'b01) ? io_val_i[10] :
(io6_mux == 2'b11) ? io_val_i[6] :
1'b0;
assign spi_ss_val_o[0] = (io11_mux == 2'b01) ? io_val_i[11] :
(io8_mux == 2'b11) ? io_val_i[8] :
1'b0;
assign spi_dq_val_o[0][0] = (io12_mux == 2'b01) ? io_val_i[12] :
(io1_mux == 2'b11) ? io_val_i[1] :
1'b0;
assign spi_dq_val_o[0][1] = (io13_mux == 2'b01) ? io_val_i[13] :
(io2_mux == 2'b11) ? io_val_i[2] :
1'b0;
assign spi_dq_val_o[0][2] = (io14_mux == 2'b01) ? io_val_i[14] :
(io4_mux == 2'b11) ? io_val_i[4] :
1'b0;
assign spi_dq_val_o[0][3] = (io15_mux == 2'b01) ? io_val_i[15] :
(io5_mux == 2'b11) ? io_val_i[5] :
1'b0;
pinmux_reg_top u_pinmux_reg_top (
.clk_i (clk_i),

6
sdk/bsp/include/pinmux.h
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@ -29,12 +29,14 @@ typedef enum {
IO1_GPIO1 = 0x0,
IO1_UART1_TX,
IO1_UART1_RX,
IO1_SPI_DQ0,
} pinmux_io1_e;
typedef enum {
IO2_GPIO2 = 0x0,
IO2_UART2_TX,
IO2_UART2_RX,
IO2_SPI_DQ1,
} pinmux_io2_e;
typedef enum {
@ -47,18 +49,21 @@ typedef enum {
IO4_GPIO4 = 0x0,
IO4_UART1_TX,
IO4_UART1_RX,
IO4_SPI_DQ2,
} pinmux_io4_e;
typedef enum {
IO5_GPIO5 = 0x0,
IO5_UART2_TX,
IO5_UART2_RX,
IO5_SPI_DQ3,
} pinmux_io5_e;
typedef enum {
IO6_GPIO6 = 0x0,
IO6_I2C0_SCL,
IO6_I2C0_SDA,
IO6_SPI_CLK,
} pinmux_io6_e;
typedef enum {
@ -71,6 +76,7 @@ typedef enum {
IO8_GPIO8 = 0x0,
IO8_I2C0_SCL,
IO8_I2C0_SDA,
IO8_SPI_SS,
} pinmux_io8_e;
typedef enum {