fpga: xilinx: add tcl scripts
Signed-off-by: liangkangnan <liangkangnan@163.com>verilator
liangkangnan
parent
5b7b657384
commit
3666009efc
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@ -0,0 +1,22 @@
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VIVADO_BASE := /home/ubuntu/Xilinx/Vivado/2018.1/bin
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VIVADO := $(VIVADO_BASE)/vivado
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VIVADOFLAGS := \
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-nojournal -mode batch \
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-source scripts/init.tcl
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.PHONY: synth
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synth:
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$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl
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.PHONY: impl
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impl:
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$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl
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.PHONY: bit
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bit:
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$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit_stream.tcl -source scripts/report.tcl
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.PHONY: clean
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clean::
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rm -rf .Xil .ip_user_files *.log *.jou out usage_statistics_webtalk.xml usage_statistics_webtalk.html
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@ -0,0 +1,2 @@
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write_bitstream -force [file join $outdir "${top_module}.bit"]
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opt_design
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place_design
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phys_opt_design
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power_opt_design
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route_design
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set prj_name {tinyriscv}
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set part_fpga {xc7a35tftg256-1}
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set top_module {tinyriscv_soc_top}
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set scriptsdir ./scripts
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set constrsdir ./constrs
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set outdir ./out
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set ipdir [file join $outdir ip]
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set srcdir ../../rtl
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# 在某目录下递归查找所有指定文件
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proc rec_glob { basedir pattern } {
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set dirlist [glob -nocomplain -directory $basedir -type d *]
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set findlist [glob -nocomplain -directory $basedir $pattern]
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foreach dir $dirlist {
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set reclist [rec_glob $dir $pattern]
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set findlist [concat $findlist $reclist]
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}
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return $findlist
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}
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# 创建工程(内存模式)
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create_project -part $part_fpga -in_memory
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# 创建sources_1
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if {[get_filesets -quiet sources_1] eq ""} {
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create_fileset -srcset sources_1
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}
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set src_pkg_files [rec_glob $srcdir "*pkg.sv"]
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set src_verilog_files [rec_glob $srcdir "*.sv"]
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set src_all_files [concat $src_pkg_files $src_verilog_files]
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# 添加verilog文件
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add_files -norecurse -fileset sources_1 $src_all_files
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# 创建constrs_1
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if {[get_filesets -quiet constrs_1] eq ""} {
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create_fileset -constrset constrs_1
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}
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# 添加约束文件
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add_files -norecurse -fileset constrs_1 [glob -directory $constrsdir {*.xdc}]
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# 创建IP
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file mkdir $ipdir
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update_ip_catalog -rebuild
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source [file join $scriptsdir ip.tcl]
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set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
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set obj [get_ips]
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generate_target all $obj
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export_ip_user_files -of_objects $obj -no_script -force
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read_ip [glob -directory $ipdir [file join * {*.xci}]]
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# 综合
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synth_design -top $top_module -include_dirs $ipdir
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#set src_pkg_files [rec_glob $srcdir "*pkg.sv"]
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#set src_verilog_files [rec_glob $srcdir "*.sv"]
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#set src_all_files [concat $src_pkg_files $src_verilog_files]
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#read_verilog -sv $src_all_files
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#read_xdc ./constrs/tinyriscv.xdc
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create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name mmcm_main_clk -dir $ipdir -force
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set_property -dict [list \
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CONFIG.PRIM_IN_FREQ {50.000} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25.000} \
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CONFIG.RESET_TYPE {ACTIVE_LOW} \
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CONFIG.RESET_PORT {resetn}] \
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[get_ips mmcm_main_clk]
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set rptdir [file join $outdir report]
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file mkdir $rptdir
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set rptutil [file join $rptdir utilization.txt]
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report_datasheet -file [file join $rptdir datasheet.txt]
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report_utilization -hierarchical -file $rptutil
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report_clock_utilization -file $rptutil -append
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report_ram_utilization -file $rptutil -append -detail
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report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
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report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
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report_drc -file [file join $rptdir drc.txt]
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report_io -file [file join $rptdir io.txt]
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report_clocks -file [file join $rptdir clocks.txt]
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@ -0,0 +1,52 @@
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proc recglob { basedir pattern } {
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set dirlist [glob -nocomplain -directory $basedir -type d *]
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set findlist [glob -nocomplain -directory $basedir $pattern]
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foreach dir $dirlist {
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set reclist [recglob $dir $pattern]
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set findlist [concat $findlist $reclist]
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}
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return $findlist
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}
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proc findincludedir { basedir pattern } {
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#find all subdirectories containing ".vh" files
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set vhfiles [recglob $basedir $pattern]
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set vhdirs {}
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foreach match $vhfiles {
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lappend vhdirs [file dir $match]
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}
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set uniquevhdirs [lsort -unique $vhdirs]
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return $uniquevhdirs
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}
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file mkdir $ipdir
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source [file join $scriptsdir ip.tcl]
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update_ip_catalog -rebuild
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set obj [get_ips]
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generate_target all $obj
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read_ip [glob -directory $ipdir [file join * {*.xci}]]
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# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
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set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
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set obj [get_ips]
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generate_target all $obj
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export_ip_user_files -of_objects $obj -no_script -force
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set obj [current_fileset]
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# Xilinx bug workaround
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# scrape IP tree for directories containing .vh files
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# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
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set property_include_dirs [get_property include_dirs $obj]
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set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
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synth_design -top $top_module -include_dirs $ipdir
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