From 3666009efc011d865ae613e71d6f15c0ae28818a Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sat, 7 May 2022 17:55:56 +0800
Subject: [PATCH] fpga: xilinx: add tcl scripts

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 fpga/xilinx/Makefile               | 22 +++++++++++
 fpga/xilinx/scripts/bit_stream.tcl |  2 +
 fpga/xilinx/scripts/impl.tcl       |  8 ++++
 fpga/xilinx/scripts/init.tcl       | 61 ++++++++++++++++++++++++++++++
 fpga/xilinx/scripts/ip.tcl         |  9 +++++
 fpga/xilinx/scripts/mcs.tcl        |  0
 fpga/xilinx/scripts/report.tcl     | 13 +++++++
 fpga/xilinx/scripts/synth.tcl      | 52 +++++++++++++++++++++++++
 8 files changed, 167 insertions(+)
 create mode 100644 fpga/xilinx/Makefile
 create mode 100644 fpga/xilinx/scripts/bit_stream.tcl
 create mode 100644 fpga/xilinx/scripts/impl.tcl
 create mode 100644 fpga/xilinx/scripts/init.tcl
 create mode 100644 fpga/xilinx/scripts/ip.tcl
 create mode 100644 fpga/xilinx/scripts/mcs.tcl
 create mode 100644 fpga/xilinx/scripts/report.tcl
 create mode 100644 fpga/xilinx/scripts/synth.tcl

diff --git a/fpga/xilinx/Makefile b/fpga/xilinx/Makefile
new file mode 100644
index 0000000..8c5f88c
--- /dev/null
+++ b/fpga/xilinx/Makefile
@@ -0,0 +1,22 @@
+VIVADO_BASE := /home/ubuntu/Xilinx/Vivado/2018.1/bin
+VIVADO := $(VIVADO_BASE)/vivado
+
+VIVADOFLAGS := \
+	-nojournal -mode batch \
+	-source scripts/init.tcl
+
+.PHONY: synth
+synth:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl
+
+.PHONY: impl
+impl:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl
+
+.PHONY: bit
+bit:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit_stream.tcl -source scripts/report.tcl
+
+.PHONY: clean
+clean::
+	rm -rf .Xil .ip_user_files *.log *.jou out usage_statistics_webtalk.xml usage_statistics_webtalk.html
diff --git a/fpga/xilinx/scripts/bit_stream.tcl b/fpga/xilinx/scripts/bit_stream.tcl
new file mode 100644
index 0000000..b209c25
--- /dev/null
+++ b/fpga/xilinx/scripts/bit_stream.tcl
@@ -0,0 +1,2 @@
+
+write_bitstream -force [file join $outdir "${top_module}.bit"]
diff --git a/fpga/xilinx/scripts/impl.tcl b/fpga/xilinx/scripts/impl.tcl
new file mode 100644
index 0000000..5d1db21
--- /dev/null
+++ b/fpga/xilinx/scripts/impl.tcl
@@ -0,0 +1,8 @@
+
+opt_design
+
+place_design
+
+phys_opt_design
+power_opt_design
+route_design
diff --git a/fpga/xilinx/scripts/init.tcl b/fpga/xilinx/scripts/init.tcl
new file mode 100644
index 0000000..f669f62
--- /dev/null
+++ b/fpga/xilinx/scripts/init.tcl
@@ -0,0 +1,61 @@
+set prj_name {tinyriscv}
+set part_fpga {xc7a35tftg256-1}
+set top_module {tinyriscv_soc_top}
+
+set scriptsdir ./scripts
+set constrsdir ./constrs
+set outdir ./out
+set ipdir [file join $outdir ip]
+set srcdir ../../rtl
+
+# 在某目录下递归查找所有指定文件
+proc rec_glob { basedir pattern } {
+    set dirlist [glob -nocomplain -directory $basedir -type d *]
+    set findlist [glob -nocomplain -directory $basedir $pattern]
+    foreach dir $dirlist {
+        set reclist [rec_glob $dir $pattern]
+        set findlist [concat $findlist $reclist]
+    }
+    return $findlist
+}
+
+# 创建工程(内存模式)
+create_project -part $part_fpga -in_memory
+
+# 创建sources_1
+if {[get_filesets -quiet sources_1] eq ""} {
+    create_fileset -srcset sources_1
+}
+set src_pkg_files [rec_glob $srcdir "*pkg.sv"]
+set src_verilog_files [rec_glob $srcdir "*.sv"]
+set src_all_files [concat $src_pkg_files $src_verilog_files]
+# 添加verilog文件
+add_files -norecurse -fileset sources_1 $src_all_files
+
+# 创建constrs_1
+if {[get_filesets -quiet constrs_1] eq ""} {
+    create_fileset -constrset constrs_1
+}
+# 添加约束文件
+add_files -norecurse -fileset constrs_1 [glob -directory $constrsdir {*.xdc}]
+
+# 创建IP
+file mkdir $ipdir
+update_ip_catalog -rebuild
+source [file join $scriptsdir ip.tcl]
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+set obj [get_ips]
+generate_target all $obj
+export_ip_user_files -of_objects $obj -no_script -force
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+# 综合
+synth_design -top $top_module -include_dirs $ipdir
+
+
+#set src_pkg_files [rec_glob $srcdir "*pkg.sv"]
+#set src_verilog_files [rec_glob $srcdir "*.sv"]
+#set src_all_files [concat $src_pkg_files $src_verilog_files]
+#read_verilog -sv $src_all_files
+
+#read_xdc ./constrs/tinyriscv.xdc
diff --git a/fpga/xilinx/scripts/ip.tcl b/fpga/xilinx/scripts/ip.tcl
new file mode 100644
index 0000000..6098c88
--- /dev/null
+++ b/fpga/xilinx/scripts/ip.tcl
@@ -0,0 +1,9 @@
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name mmcm_main_clk -dir $ipdir -force
+
+set_property -dict [list \
+CONFIG.PRIM_IN_FREQ {50.000} \
+CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25.000} \
+CONFIG.RESET_TYPE {ACTIVE_LOW} \
+CONFIG.RESET_PORT {resetn}] \
+[get_ips mmcm_main_clk]
diff --git a/fpga/xilinx/scripts/mcs.tcl b/fpga/xilinx/scripts/mcs.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/xilinx/scripts/report.tcl b/fpga/xilinx/scripts/report.tcl
new file mode 100644
index 0000000..a4b5ca8
--- /dev/null
+++ b/fpga/xilinx/scripts/report.tcl
@@ -0,0 +1,13 @@
+
+set rptdir [file join $outdir report]
+file mkdir $rptdir
+set rptutil [file join $rptdir utilization.txt]
+report_datasheet -file [file join $rptdir datasheet.txt]
+report_utilization -hierarchical -file $rptutil
+report_clock_utilization -file $rptutil -append
+report_ram_utilization -file $rptutil -append -detail
+report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
+report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
+report_drc -file [file join $rptdir drc.txt]
+report_io -file [file join $rptdir io.txt]
+report_clocks -file [file join $rptdir clocks.txt]
diff --git a/fpga/xilinx/scripts/synth.tcl b/fpga/xilinx/scripts/synth.tcl
new file mode 100644
index 0000000..fe42674
--- /dev/null
+++ b/fpga/xilinx/scripts/synth.tcl
@@ -0,0 +1,52 @@
+proc recglob { basedir pattern } {
+  set dirlist [glob -nocomplain -directory $basedir -type d *]
+  set findlist [glob -nocomplain -directory $basedir $pattern]
+  foreach dir $dirlist {
+    set reclist [recglob $dir $pattern]
+    set findlist [concat $findlist $reclist]
+  }
+  return $findlist
+}
+
+proc findincludedir { basedir pattern } {
+  #find all subdirectories containing ".vh" files
+  set vhfiles [recglob $basedir $pattern]
+  set vhdirs {}
+  foreach match $vhfiles {
+    lappend vhdirs [file dir $match]
+  }
+  set uniquevhdirs [lsort -unique $vhdirs]
+  return $uniquevhdirs
+}
+
+
+file mkdir $ipdir
+
+source [file join $scriptsdir ip.tcl]
+
+update_ip_catalog -rebuild
+
+set obj [get_ips]
+generate_target all $obj
+
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+
+# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+set obj [get_ips]
+generate_target all $obj
+export_ip_user_files -of_objects $obj -no_script -force
+
+set obj [current_fileset]
+
+# Xilinx bug workaround
+# scrape IP tree for directories containing .vh files
+# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
+set property_include_dirs [get_property include_dirs $obj]
+set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
+
+
+synth_design -top $top_module -include_dirs $ipdir