From 362d1884582208bd7f5f0df3c696681ad016dfad Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Wed, 27 May 2020 23:07:14 +0800
Subject: [PATCH] use tb file in tb dir

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 FPGA/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FPGA/README.md b/FPGA/README.md
index ea3e396..6452284 100644
--- a/FPGA/README.md
+++ b/FPGA/README.md
@@ -158,7 +158,7 @@
 
 # 4.Vivado仿真设置
 
-如果要在vivado里进行RTL仿真的话，还需要添加sim目录里的tinyriscv_soc_tb.v文件，具体方法和添加RTL源文件类似，只是在源文件类型里选择simulation sources，如下图所示：
+如果要在vivado里进行RTL仿真的话，还需要添加tb目录里的tinyriscv_soc_tb.v文件，具体方法和添加RTL源文件类似，只是在源文件类型里选择simulation sources，如下图所示：
 
 ![add_sim](./images/add_sim.png)