From 2d9aab4ecb1a4786654c0a3c0955a04699bda63e Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Wed, 29 Sep 2021 09:24:04 +0800 Subject: [PATCH] sdk: add arg for multi perips Signed-off-by: liangkangnan --- sdk/bsp/include/i2c.h | 42 +-- sdk/bsp/include/rvic.h | 244 +++++++++-------- sdk/bsp/include/spi.h | 253 +++++++++--------- sdk/bsp/include/timer.h | 33 +-- sdk/bsp/include/uart.h | 47 +++- sdk/bsp/lib/i2c.c | 80 +++--- sdk/bsp/lib/spi.c | 144 +++++----- sdk/bsp/lib/timer.c | 42 +-- sdk/bsp/lib/uart.c | 154 ++++++++++- sdk/examples/coremark/core_portme.c | 2 +- .../freertos/Source/portable/RISC-V/port.c | 22 +- sdk/examples/gpio/main.c | 7 +- sdk/examples/hello_world/main.c | 2 +- sdk/examples/i2c_master/main.c | 46 ++-- sdk/examples/i2c_slave/main.c | 49 ++-- sdk/examples/int_preempt/main.c | 48 ++-- sdk/examples/spi_master/flash_n25q.c | 80 +++--- sdk/examples/spi_master/main.c | 11 +- sdk/examples/spi_master2/.gitignore | 8 + sdk/examples/spi_master2/Makefile | 21 ++ sdk/examples/spi_master2/README.md | 1 + sdk/examples/spi_master2/flash_w25q.c | 116 ++++++++ sdk/examples/spi_master2/flash_w25q.h | 24 ++ sdk/examples/spi_master2/main.c | 44 +++ sdk/examples/timer/main.c | 57 ++-- sdk/examples/uart_int/main.c | 41 +-- sdk/examples/uart_loopback/main.c | 4 +- 27 files changed, 1045 insertions(+), 577 deletions(-) create mode 100644 sdk/examples/spi_master2/.gitignore create mode 100644 sdk/examples/spi_master2/Makefile create mode 100644 sdk/examples/spi_master2/README.md create mode 100644 sdk/examples/spi_master2/flash_w25q.c create mode 100644 sdk/examples/spi_master2/flash_w25q.h create mode 100644 sdk/examples/spi_master2/main.c diff --git a/sdk/bsp/include/i2c.h b/sdk/bsp/include/i2c.h index ea5d1ff..6b95b53 100644 --- a/sdk/bsp/include/i2c.h +++ b/sdk/bsp/include/i2c.h @@ -16,33 +16,35 @@ extern "C" { // Register width #define I2C_PARAM_REG_WIDTH 32 -#define I2C0_BASE_ADDR (0x06000000) -#define I2C0_REG(offset) (*((volatile uint32_t *)(I2C0_BASE_ADDR + offset))) +#define I2C0_BASE_ADDR (0x06000000) +#define I2C1_BASE_ADDR (0x0B000000) -#define I2C1_BASE_ADDR (0x0B000000) -#define I2C1_REG(offset) (*((volatile uint32_t *)(I2C1_BASE_ADDR + offset))) +#define I2C0 (I2C0_BASE_ADDR) +#define I2C1 (I2C1_BASE_ADDR) + +#define I2C_REG(base, offset) (*((volatile uint32_t *)(base + offset))) typedef enum { I2C_MODE_MASTER = 0, I2C_MODE_SLAVE } i2c_mode_e; -void i2c0_set_clk(uint16_t clk_div); -void i2c0_set_mode(i2c_mode_e mode); -void i2c0_master_set_write(uint8_t yes); -void i2c0_set_interrupt_enable(uint8_t en); -void i2c0_clear_irq_pending(); -uint8_t i2c0_get_irq_pending(); -void i2c0_master_set_info(uint8_t addr, uint8_t reg, uint8_t data); -uint8_t i2c0_master_get_data(); -void i2c0_slave_set_address(uint8_t addr); -void i2c0_slave_set_ready(uint8_t yes); -uint8_t i2c0_slave_op_read(); -uint32_t i2c0_slave_get_op_address(); -uint32_t i2c0_slave_get_op_data(); -void i2c0_slave_set_rsp_data(uint32_t data); -void i2c0_start(); -void i2c0_stop(); +void i2c_set_clk(uint32_t base, uint16_t clk_div); +void i2c_set_mode(uint32_t base, i2c_mode_e mode); +void i2c_master_set_write(uint32_t base, uint8_t yes); +void i2c_set_interrupt_enable(uint32_t base, uint8_t en); +void i2c_clear_irq_pending(uint32_t base); +uint8_t i2c_get_irq_pending(uint32_t base); +void i2c_master_set_info(uint32_t base, uint8_t addr, uint8_t reg, uint8_t data); +uint8_t i2c_master_get_data(uint32_t base); +void i2c_slave_set_address(uint32_t base, uint8_t addr); +void i2c_slave_set_ready(uint32_t base, uint8_t yes); +uint8_t i2c_slave_op_read(uint32_t base); +uint32_t i2c_slave_get_op_address(uint32_t base); +uint32_t i2c_slave_get_op_data(uint32_t base); +void i2c_slave_set_rsp_data(uint32_t base, uint32_t data); +void i2c_start(uint32_t base); +void i2c_stop(uint32_t base); // I2C control register #define I2C_CTRL_REG_OFFSET 0x0 diff --git a/sdk/bsp/include/rvic.h b/sdk/bsp/include/rvic.h index e66437a..165855d 100644 --- a/sdk/bsp/include/rvic.h +++ b/sdk/bsp/include/rvic.h @@ -1,114 +1,132 @@ -// Generated register defines for rvic - -// Copyright information found in source file: -// Copyright lowRISC contributors. - -// Licensing information found in source file: -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef _RVIC_REG_DEFS_ -#define _RVIC_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define RVIC_PARAM_REG_WIDTH 32 - -#define RVIC_BASE (0xD0000000) -#define RVIC_REG(addr) (*((volatile uint32_t *)(RVIC_BASE + addr))) - -#define RVIC_PRIO_REG_NUM (8) - -typedef struct { - volatile uint32_t prio[RVIC_PRIO_REG_NUM]; -} rvic_prio_t; - -#define RVIC_PRIO ((rvic_prio_t *)(RVIC_BASE + RVIC_PRIORITY0_REG_OFFSET)) - -typedef enum { - RVIC_INT_ID_0 = 0, - RVIC_INT_ID_1, - RVIC_INT_ID_2, - RVIC_INT_ID_3, - RVIC_INT_ID_4, - RVIC_INT_ID_5, - RVIC_INT_ID_6, - RVIC_INT_ID_7, - RVIC_INT_ID_8, - RVIC_INT_ID_9, - RVIC_INT_ID_10, - RVIC_INT_ID_11, - RVIC_INT_ID_12, - RVIC_INT_ID_13, - RVIC_INT_ID_14, - RVIC_INT_ID_15, - RVIC_INT_ID_16, - RVIC_INT_ID_17, - RVIC_INT_ID_18, - RVIC_INT_ID_19, - RVIC_INT_ID_20, - RVIC_INT_ID_21, - RVIC_INT_ID_22, - RVIC_INT_ID_23, - RVIC_INT_ID_24, - RVIC_INT_ID_25, - RVIC_INT_ID_26, - RVIC_INT_ID_27, - RVIC_INT_ID_28, - RVIC_INT_ID_29, - RVIC_INT_ID_30, - RVIC_INT_ID_31, -} rvic_int_id_e; - -void rvic_irq_enable(rvic_int_id_e id); -void rvic_irq_disable(rvic_int_id_e id); -void rvic_clear_irq_pending(rvic_int_id_e id); -void rvic_set_irq_prio_level(rvic_int_id_e id, uint8_t level); - -// RVIC interrupt enable register -#define RVIC_ENABLE_REG_OFFSET 0x0 -#define RVIC_ENABLE_REG_RESVAL 0x0 - -// RVIC interrupt pending register -#define RVIC_PENDING_REG_OFFSET 0x4 -#define RVIC_PENDING_REG_RESVAL 0x0 - -// RVIC interrupt priority0 register -#define RVIC_PRIORITY0_REG_OFFSET 0x8 -#define RVIC_PRIORITY0_REG_RESVAL 0x0 - -// RVIC interrupt priority1 register -#define RVIC_PRIORITY1_REG_OFFSET 0xc -#define RVIC_PRIORITY1_REG_RESVAL 0x0 - -// RVIC interrupt priority2 register -#define RVIC_PRIORITY2_REG_OFFSET 0x10 -#define RVIC_PRIORITY2_REG_RESVAL 0x0 - -// RVIC interrupt priority3 register -#define RVIC_PRIORITY3_REG_OFFSET 0x14 -#define RVIC_PRIORITY3_REG_RESVAL 0x0 - -// RVIC interrupt priority4 register -#define RVIC_PRIORITY4_REG_OFFSET 0x18 -#define RVIC_PRIORITY4_REG_RESVAL 0x0 - -// RVIC interrupt priority5 register -#define RVIC_PRIORITY5_REG_OFFSET 0x1c -#define RVIC_PRIORITY5_REG_RESVAL 0x0 - -// RVIC interrupt priority6 register -#define RVIC_PRIORITY6_REG_OFFSET 0x20 -#define RVIC_PRIORITY6_REG_RESVAL 0x0 - -// RVIC interrupt priority7 register -#define RVIC_PRIORITY7_REG_OFFSET 0x24 -#define RVIC_PRIORITY7_REG_RESVAL 0x0 - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _RVIC_REG_DEFS_ +// Generated register defines for rvic + +// Copyright information found in source file: +// Copyright lowRISC contributors. + +// Licensing information found in source file: +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _RVIC_REG_DEFS_ +#define _RVIC_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define RVIC_PARAM_REG_WIDTH 32 + +#define RVIC_BASE (0xD0000000) +#define RVIC_REG(addr) (*((volatile uint32_t *)(RVIC_BASE + addr))) + +#define RVIC_PRIO_REG_NUM (8) + +typedef struct { + volatile uint32_t prio[RVIC_PRIO_REG_NUM]; +} rvic_prio_t; + +#define RVIC_PRIO ((rvic_prio_t *)(RVIC_BASE + RVIC_PRIORITY0_REG_OFFSET)) + +typedef enum { + RVIC_INT_ID_0 = 0, + RVIC_INT_ID_1, + RVIC_INT_ID_2, + RVIC_INT_ID_3, + RVIC_INT_ID_4, + RVIC_INT_ID_5, + RVIC_INT_ID_6, + RVIC_INT_ID_7, + RVIC_INT_ID_8, + RVIC_INT_ID_9, + RVIC_INT_ID_10, + RVIC_INT_ID_11, + RVIC_INT_ID_12, + RVIC_INT_ID_13, + RVIC_INT_ID_14, + RVIC_INT_ID_15, + RVIC_INT_ID_16, + RVIC_INT_ID_17, + RVIC_INT_ID_18, + RVIC_INT_ID_19, + RVIC_INT_ID_20, + RVIC_INT_ID_21, + RVIC_INT_ID_22, + RVIC_INT_ID_23, + RVIC_INT_ID_24, + RVIC_INT_ID_25, + RVIC_INT_ID_26, + RVIC_INT_ID_27, + RVIC_INT_ID_28, + RVIC_INT_ID_29, + RVIC_INT_ID_30, + RVIC_INT_ID_31, +} rvic_int_id_e; + +#define RVIC_TIMER0_INT_ID RVIC_INT_ID_0 +#define RVIC_UART0_INT_ID RVIC_INT_ID_1 +#define RVIC_GPIO0_INT_ID RVIC_INT_ID_2 +#define RVIC_GPIO1_INT_ID RVIC_INT_ID_3 +#define RVIC_I2C0_INT_ID RVIC_INT_ID_4 +#define RVIC_SPI0_INT_ID RVIC_INT_ID_5 +#define RVIC_GPIO2_4_INT_ID RVIC_INT_ID_6 +#define RVIC_GPIO5_7_INT_ID RVIC_INT_ID_7 +#define RVIC_GPIO8_INT_ID RVIC_INT_ID_8 +#define RVIC_GPIO9_INT_ID RVIC_INT_ID_9 +#define RVIC_GPIO10_12_INT_ID RVIC_INT_ID_10 +#define RVIC_GPIO13_15_INT_ID RVIC_INT_ID_11 +#define RVIC_UART1_INT_ID RVIC_INT_ID_12 +#define RVIC_UART2_INT_ID RVIC_INT_ID_13 +#define RVIC_I2C1_INT_ID RVIC_INT_ID_14 +#define RVIC_TIMER1_INT_ID RVIC_INT_ID_15 +#define RVIC_TIMER2_INT_ID RVIC_INT_ID_16 + +void rvic_irq_enable(rvic_int_id_e id); +void rvic_irq_disable(rvic_int_id_e id); +void rvic_clear_irq_pending(rvic_int_id_e id); +void rvic_set_irq_prio_level(rvic_int_id_e id, uint8_t level); + +// RVIC interrupt enable register +#define RVIC_ENABLE_REG_OFFSET 0x0 +#define RVIC_ENABLE_REG_RESVAL 0x0 + +// RVIC interrupt pending register +#define RVIC_PENDING_REG_OFFSET 0x4 +#define RVIC_PENDING_REG_RESVAL 0x0 + +// RVIC interrupt priority0 register +#define RVIC_PRIORITY0_REG_OFFSET 0x8 +#define RVIC_PRIORITY0_REG_RESVAL 0x0 + +// RVIC interrupt priority1 register +#define RVIC_PRIORITY1_REG_OFFSET 0xc +#define RVIC_PRIORITY1_REG_RESVAL 0x0 + +// RVIC interrupt priority2 register +#define RVIC_PRIORITY2_REG_OFFSET 0x10 +#define RVIC_PRIORITY2_REG_RESVAL 0x0 + +// RVIC interrupt priority3 register +#define RVIC_PRIORITY3_REG_OFFSET 0x14 +#define RVIC_PRIORITY3_REG_RESVAL 0x0 + +// RVIC interrupt priority4 register +#define RVIC_PRIORITY4_REG_OFFSET 0x18 +#define RVIC_PRIORITY4_REG_RESVAL 0x0 + +// RVIC interrupt priority5 register +#define RVIC_PRIORITY5_REG_OFFSET 0x1c +#define RVIC_PRIORITY5_REG_RESVAL 0x0 + +// RVIC interrupt priority6 register +#define RVIC_PRIORITY6_REG_OFFSET 0x20 +#define RVIC_PRIORITY6_REG_RESVAL 0x0 + +// RVIC interrupt priority7 register +#define RVIC_PRIORITY7_REG_OFFSET 0x24 +#define RVIC_PRIORITY7_REG_RESVAL 0x0 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _RVIC_REG_DEFS_ // End generated register defines for rvic \ No newline at end of file diff --git a/sdk/bsp/include/spi.h b/sdk/bsp/include/spi.h index d28c209..32a5128 100644 --- a/sdk/bsp/include/spi.h +++ b/sdk/bsp/include/spi.h @@ -1,126 +1,129 @@ -// Generated register defines for spi - -// Copyright information found in source file: -// Copyright lowRISC contributors. - -// Licensing information found in source file: -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef _SPI_REG_DEFS_ -#define _SPI_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define SPI_PARAM_REG_WIDTH 32 - -#define SPI0_BASE_ADDR (0x07000000) -#define SPI0_REG(offset) (*((volatile uint32_t *)(SPI0_BASE_ADDR + offset))) - -#define SPI0_TX_FIFO_LEN (8) -#define SPI0_RX_FIFO_LEN SPI0_TX_FIFO_LEN - -typedef enum { - SPI_ROLE_MODE_MASTER = 0, - SPI_ROLE_MODE_SLAVE -} spi_role_mode_e; - -typedef enum { - SPI_CPOL_0_CPHA_0 = 0, - SPI_CPOL_0_CPHA_1, - SPI_CPOL_1_CPHA_0, - SPI_CPOL_1_CPHA_1 -} spi_cp_mode_e; - -typedef enum { - SPI_MODE_STANDARD = 0, - SPI_MODE_DUAL, - SPI_MODE_QUAD -} spi_spi_mode_e; - -void spi0_set_clk_div(uint16_t div); -void spi0_set_role_mode(spi_role_mode_e mode); -void spi0_set_spi_mode(spi_spi_mode_e mode); -void spi0_set_cp_mode(spi_cp_mode_e mode); -void spi0_set_enable(uint8_t en); -void spi0_set_interrupt_enable(uint8_t en); -void spi0_set_msb_first(); -void spi0_set_lsb_first(); -void spi0_set_txdata(uint8_t data); -uint8_t spi0_get_rxdata(); -uint8_t spi0_reset_rxfifo(); -uint8_t spi0_tx_fifo_full(); -uint8_t spi0_tx_fifo_empty(); -uint8_t spi0_rx_fifo_full(); -uint8_t spi0_rx_fifo_empty(); -void spi0_set_ss_ctrl_by_sw(uint8_t yes); -void spi0_set_ss_level(uint8_t level); -uint8_t spi0_get_interrupt_pending(); -void spi0_clear_interrupt_pending(); -void spi0_master_set_read(); -void spi0_master_set_write(); -void spi0_master_set_ss_delay(uint8_t clk_num); -uint8_t spi0_master_transmiting(); -void spi0_master_write_bytes(uint8_t write_data[], uint32_t count); -void spi0_master_read_bytes(uint8_t read_data[], uint32_t count); - -// SPI control 0 register -#define SPI_CTRL0_REG_OFFSET 0x0 -#define SPI_CTRL0_REG_RESVAL 0x0 -#define SPI_CTRL0_ENABLE_BIT 0 -#define SPI_CTRL0_INT_EN_BIT 1 -#define SPI_CTRL0_INT_PENDING_BIT 2 -#define SPI_CTRL0_ROLE_MODE_BIT 3 -#define SPI_CTRL0_CP_MODE_MASK 0x3 -#define SPI_CTRL0_CP_MODE_OFFSET 4 -#define SPI_CTRL0_CP_MODE_FIELD \ - ((bitfield_field32_t) { .mask = SPI_CTRL0_CP_MODE_MASK, .index = SPI_CTRL0_CP_MODE_OFFSET }) -#define SPI_CTRL0_SPI_MODE_MASK 0x3 -#define SPI_CTRL0_SPI_MODE_OFFSET 6 -#define SPI_CTRL0_SPI_MODE_FIELD \ - ((bitfield_field32_t) { .mask = SPI_CTRL0_SPI_MODE_MASK, .index = SPI_CTRL0_SPI_MODE_OFFSET }) -#define SPI_CTRL0_READ_BIT 8 -#define SPI_CTRL0_MSB_FIRST_BIT 9 -#define SPI_CTRL0_SS_SW_CTRL_BIT 10 -#define SPI_CTRL0_SS_LEVEL_BIT 11 -#define SPI_CTRL0_SS_DELAY_MASK 0xf -#define SPI_CTRL0_SS_DELAY_OFFSET 12 -#define SPI_CTRL0_SS_DELAY_FIELD \ - ((bitfield_field32_t) { .mask = SPI_CTRL0_SS_DELAY_MASK, .index = SPI_CTRL0_SS_DELAY_OFFSET }) -#define SPI_CTRL0_CLK_DIV_MASK 0x7 -#define SPI_CTRL0_CLK_DIV_OFFSET 29 -#define SPI_CTRL0_CLK_DIV_FIELD \ - ((bitfield_field32_t) { .mask = SPI_CTRL0_CLK_DIV_MASK, .index = SPI_CTRL0_CLK_DIV_OFFSET }) - -// SPI status register -#define SPI_STATUS_REG_OFFSET 0x4 -#define SPI_STATUS_REG_RESVAL 0x0 -#define SPI_STATUS_TX_FIFO_FULL_BIT 0 -#define SPI_STATUS_TX_FIFO_EMPTY_BIT 1 -#define SPI_STATUS_RX_FIFO_FULL_BIT 2 -#define SPI_STATUS_RX_FIFO_EMPTY_BIT 3 -#define SPI_STATUS_BUSY_BIT 4 - -// SPI TX data register -#define SPI_TXDATA_REG_OFFSET 0x8 -#define SPI_TXDATA_REG_RESVAL 0x0 -#define SPI_TXDATA_TXDATA_MASK 0xff -#define SPI_TXDATA_TXDATA_OFFSET 0 -#define SPI_TXDATA_TXDATA_FIELD \ - ((bitfield_field32_t) { .mask = SPI_TXDATA_TXDATA_MASK, .index = SPI_TXDATA_TXDATA_OFFSET }) - -// SPI RX data register -#define SPI_RXDATA_REG_OFFSET 0xc -#define SPI_RXDATA_REG_RESVAL 0x0 -#define SPI_RXDATA_RXDATA_MASK 0xff -#define SPI_RXDATA_RXDATA_OFFSET 0 -#define SPI_RXDATA_RXDATA_FIELD \ - ((bitfield_field32_t) { .mask = SPI_RXDATA_RXDATA_MASK, .index = SPI_RXDATA_RXDATA_OFFSET }) - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _SPI_REG_DEFS_ +// Generated register defines for spi + +// Copyright information found in source file: +// Copyright lowRISC contributors. + +// Licensing information found in source file: +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _SPI_REG_DEFS_ +#define _SPI_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define SPI_PARAM_REG_WIDTH 32 + +#define SPI0_BASE_ADDR (0x07000000) + +#define SPI0 (SPI0_BASE_ADDR) + +#define SPI_REG(base, offset) (*((volatile uint32_t *)(base + offset))) + +#define SPI_TX_FIFO_LEN (8) +#define SPI_RX_FIFO_LEN SPI_TX_FIFO_LEN + +typedef enum { + SPI_ROLE_MODE_MASTER = 0, + SPI_ROLE_MODE_SLAVE +} spi_role_mode_e; + +typedef enum { + SPI_CPOL_0_CPHA_0 = 0, + SPI_CPOL_0_CPHA_1, + SPI_CPOL_1_CPHA_0, + SPI_CPOL_1_CPHA_1 +} spi_cp_mode_e; + +typedef enum { + SPI_MODE_STANDARD = 0, + SPI_MODE_DUAL, + SPI_MODE_QUAD +} spi_spi_mode_e; + +void spi_set_clk_div(uint32_t base, uint16_t div); +void spi_set_role_mode(uint32_t base, spi_role_mode_e mode); +void spi_set_spi_mode(uint32_t base, spi_spi_mode_e mode); +void spi_set_cp_mode(uint32_t base, spi_cp_mode_e mode); +void spi_set_enable(uint32_t base, uint8_t en); +void spi_set_interrupt_enable(uint32_t base, uint8_t en); +void spi_set_msb_first(uint32_t base); +void spi_set_lsb_first(uint32_t base); +void spi_set_txdata(uint32_t base, uint8_t data); +uint8_t spi_get_rxdata(uint32_t base); +uint8_t spi_reset_rxfifo(uint32_t base); +uint8_t spi_tx_fifo_full(uint32_t base); +uint8_t spi_tx_fifo_empty(uint32_t base); +uint8_t spi_rx_fifo_full(uint32_t base); +uint8_t spi_rx_fifo_empty(uint32_t base); +void spi_set_ss_ctrl_by_sw(uint32_t base, uint8_t yes); +void spi_set_ss_level(uint32_t base, uint8_t level); +uint8_t spi_get_interrupt_pending(uint32_t base); +void spi_clear_interrupt_pending(uint32_t base); +void spi_master_set_read(uint32_t base); +void spi_master_set_write(uint32_t base); +void spi_master_set_ss_delay(uint32_t base, uint8_t clk_num); +uint8_t spi_master_transmiting(uint32_t base); +void spi_master_write_bytes(uint32_t base, uint8_t write_data[], uint32_t count); +void spi_master_read_bytes(uint32_t base, uint8_t read_data[], uint32_t count); + +// SPI control 0 register +#define SPI_CTRL0_REG_OFFSET 0x0 +#define SPI_CTRL0_REG_RESVAL 0x0 +#define SPI_CTRL0_ENABLE_BIT 0 +#define SPI_CTRL0_INT_EN_BIT 1 +#define SPI_CTRL0_INT_PENDING_BIT 2 +#define SPI_CTRL0_ROLE_MODE_BIT 3 +#define SPI_CTRL0_CP_MODE_MASK 0x3 +#define SPI_CTRL0_CP_MODE_OFFSET 4 +#define SPI_CTRL0_CP_MODE_FIELD \ + ((bitfield_field32_t) { .mask = SPI_CTRL0_CP_MODE_MASK, .index = SPI_CTRL0_CP_MODE_OFFSET }) +#define SPI_CTRL0_SPI_MODE_MASK 0x3 +#define SPI_CTRL0_SPI_MODE_OFFSET 6 +#define SPI_CTRL0_SPI_MODE_FIELD \ + ((bitfield_field32_t) { .mask = SPI_CTRL0_SPI_MODE_MASK, .index = SPI_CTRL0_SPI_MODE_OFFSET }) +#define SPI_CTRL0_READ_BIT 8 +#define SPI_CTRL0_MSB_FIRST_BIT 9 +#define SPI_CTRL0_SS_SW_CTRL_BIT 10 +#define SPI_CTRL0_SS_LEVEL_BIT 11 +#define SPI_CTRL0_SS_DELAY_MASK 0xf +#define SPI_CTRL0_SS_DELAY_OFFSET 12 +#define SPI_CTRL0_SS_DELAY_FIELD \ + ((bitfield_field32_t) { .mask = SPI_CTRL0_SS_DELAY_MASK, .index = SPI_CTRL0_SS_DELAY_OFFSET }) +#define SPI_CTRL0_CLK_DIV_MASK 0x7 +#define SPI_CTRL0_CLK_DIV_OFFSET 29 +#define SPI_CTRL0_CLK_DIV_FIELD \ + ((bitfield_field32_t) { .mask = SPI_CTRL0_CLK_DIV_MASK, .index = SPI_CTRL0_CLK_DIV_OFFSET }) + +// SPI status register +#define SPI_STATUS_REG_OFFSET 0x4 +#define SPI_STATUS_REG_RESVAL 0x0 +#define SPI_STATUS_TX_FIFO_FULL_BIT 0 +#define SPI_STATUS_TX_FIFO_EMPTY_BIT 1 +#define SPI_STATUS_RX_FIFO_FULL_BIT 2 +#define SPI_STATUS_RX_FIFO_EMPTY_BIT 3 +#define SPI_STATUS_BUSY_BIT 4 + +// SPI TX data register +#define SPI_TXDATA_REG_OFFSET 0x8 +#define SPI_TXDATA_REG_RESVAL 0x0 +#define SPI_TXDATA_TXDATA_MASK 0xff +#define SPI_TXDATA_TXDATA_OFFSET 0 +#define SPI_TXDATA_TXDATA_FIELD \ + ((bitfield_field32_t) { .mask = SPI_TXDATA_TXDATA_MASK, .index = SPI_TXDATA_TXDATA_OFFSET }) + +// SPI RX data register +#define SPI_RXDATA_REG_OFFSET 0xc +#define SPI_RXDATA_REG_RESVAL 0x0 +#define SPI_RXDATA_RXDATA_MASK 0xff +#define SPI_RXDATA_RXDATA_OFFSET 0 +#define SPI_RXDATA_RXDATA_FIELD \ + ((bitfield_field32_t) { .mask = SPI_RXDATA_RXDATA_MASK, .index = SPI_RXDATA_RXDATA_OFFSET }) + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _SPI_REG_DEFS_ // End generated register defines for spi \ No newline at end of file diff --git a/sdk/bsp/include/timer.h b/sdk/bsp/include/timer.h index 3aaf5a1..18c0562 100644 --- a/sdk/bsp/include/timer.h +++ b/sdk/bsp/include/timer.h @@ -16,14 +16,25 @@ extern "C" { // Register width #define TIMER_PARAM_REG_WIDTH 32 -#define TIMER0_BASE_ADDR (0x04000000) -#define TIMER0_REG(offset) (*((volatile uint32_t *)(TIMER0_BASE_ADDR + offset))) +#define TIMER0_BASE_ADDR (0x04000000) +#define TIMER1_BASE_ADDR (0x0C000000) +#define TIMER2_BASE_ADDR (0x0D000000) -#define TIMER1_BASE_ADDR (0x0C000000) -#define TIMER1_REG(offset) (*((volatile uint32_t *)(TIMER1_BASE_ADDR + offset))) +#define TIMER0 (TIMER0_BASE_ADDR) +#define TIMER1 (TIMER1_BASE_ADDR) +#define TIMER2 (TIMER2_BASE_ADDR) -#define TIMER2_BASE_ADDR (0x0D000000) -#define TIMER2_REG(offset) (*((volatile uint32_t *)(TIMER2_BASE_ADDR + offset))) +#define TIMER_REG(base, offset) (*((volatile uint32_t *)(base + offset))) + +void timer_start(uint32_t base, uint8_t en); +void timer_set_value(uint32_t base, uint32_t val); +void timer_set_int_enable(uint32_t base, uint8_t en); +void timer_clear_int_pending(uint32_t base); +uint8_t timer_get_int_pending(uint32_t base); +uint32_t timer_get_current_count(uint32_t base); +void timer_set_mode_auto_reload(uint32_t base); +void timer_set_mode_ontshot(uint32_t base); +void timer_set_clk_div(uint32_t base, uint32_t div); // Timer control register #define TIMER_CTRL_REG_OFFSET 0x0 @@ -45,16 +56,6 @@ extern "C" { #define TIMER_COUNT_REG_OFFSET 0x8 #define TIMER_COUNT_REG_RESVAL 0x0 -void timer0_start(uint8_t en); -void timer0_set_value(uint32_t val); -void timer0_set_int_enable(uint8_t en); -void timer0_clear_int_pending(); -uint8_t timer0_get_int_pending(); -uint32_t timer0_get_current_count(); -void timer0_set_mode_auto_reload(); -void timer0_set_mode_ontshot(); -void timer0_set_div(uint32_t div); - #ifdef __cplusplus } // extern "C" #endif diff --git a/sdk/bsp/include/uart.h b/sdk/bsp/include/uart.h index 6f0bbca..e1ccce3 100644 --- a/sdk/bsp/include/uart.h +++ b/sdk/bsp/include/uart.h @@ -7,14 +7,43 @@ extern "C" { // Register width #define UART_PARAM_REG_WIDTH 32 -#define UART0_BASE_ADDR (0x05000000) -#define UART0_REG(offset) (*((volatile uint32_t *)(UART0_BASE_ADDR + offset))) +#define UART0_BASE_ADDR (0x05000000) +#define UART1_BASE_ADDR (0x09000000) +#define UART2_BASE_ADDR (0x0A000000) -#define UART1_BASE_ADDR (0x09000000) -#define UART1_REG(offset) (*((volatile uint32_t *)(UART1_BASE_ADDR + offset))) +#define UART0 (UART0_BASE_ADDR) +#define UART1 (UART1_BASE_ADDR) +#define UART2 (UART2_BASE_ADDR) -#define UART2_BASE_ADDR (0x0A000000) -#define UART2_REG(offset) (*((volatile uint32_t *)(UART2_BASE_ADDR + offset))) +#define UART_REG(base, offset) (*((volatile uint32_t *)(base + offset))) + +#define UART_TX_FIFO_LEN (8) +#define UART_RX_FIFO_LEN UART_TX_FIFO_LEN + +typedef void (*myputc)(uint8_t); + +void uart0_putc(uint8_t c); +uint8_t uart0_getc(); +void uart1_putc(uint8_t c); +uint8_t uart1_getc(); +void uart2_putc(uint8_t c); +uint8_t uart2_getc(); +void uart_init(uint32_t base, myputc put); +void uart_tx_enable(uint32_t base, uint8_t en); +void uart_rx_enable(uint32_t base, uint8_t en); +void uart_tx_fifo_empty_int_enable(uint32_t base, uint8_t en); +void uart_rx_fifo_not_empty_int_enable(uint32_t base, uint8_t en); +void uart_set_baud_div(uint32_t base, uint32_t div); +void uart_reset_tx_fifo(uint32_t base); +void uart_reset_rx_fifo(uint32_t base); +uint8_t uart_tx_fifo_full(uint32_t base); +uint8_t uart_rx_fifo_full(uint32_t base); +uint8_t uart_tx_fifo_empty(uint32_t base); +uint8_t uart_rx_fifo_empty(uint32_t base); +uint8_t uart_tx_idle(uint32_t base); +uint8_t uart_rx_idle(uint32_t base); +uint8_t uart_get_rx_fifo_data(uint32_t base); +void uart_set_tx_fifo_data(uint32_t base, uint8_t data); // UART control register #define UART_CTRL_REG_OFFSET 0x0 @@ -56,12 +85,6 @@ extern "C" { #define UART_RXDATA_RXDATA_FIELD \ ((bitfield_field32_t) { .mask = UART_RXDATA_RXDATA_MASK, .index = UART_RXDATA_RXDATA_OFFSET }) -typedef void (*myputc)(uint8_t); - -void uart0_init(myputc putc); -uint8_t uart0_getc(); -void uart0_putc(uint8_t c); - #ifdef __cplusplus } // extern "C" #endif diff --git a/sdk/bsp/lib/i2c.c b/sdk/bsp/lib/i2c.c index 0d7c397..ec34796 100644 --- a/sdk/bsp/lib/i2c.c +++ b/sdk/bsp/lib/i2c.c @@ -3,108 +3,108 @@ #include "../include/i2c.h" -void i2c0_set_clk(uint16_t clk_div) +void i2c_set_clk(uint32_t base, uint16_t clk_div) { - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(I2C_CTRL_CLK_DIV_MASK << I2C_CTRL_CLK_DIV_OFFSET); - I2C0_REG(I2C_CTRL_REG_OFFSET) |= clk_div << I2C_CTRL_CLK_DIV_OFFSET; + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(I2C_CTRL_CLK_DIV_MASK << I2C_CTRL_CLK_DIV_OFFSET); + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= clk_div << I2C_CTRL_CLK_DIV_OFFSET; } -void i2c0_set_mode(i2c_mode_e mode) +void i2c_set_mode(uint32_t base, i2c_mode_e mode) { if (mode == I2C_MODE_MASTER) - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_MODE_BIT); + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_MODE_BIT); else - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_MODE_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_MODE_BIT; } -void i2c0_master_set_write(uint8_t yes) +void i2c_master_set_write(uint32_t base, uint8_t yes) { if (yes) - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_WRITE_BIT); + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_WRITE_BIT); else - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_WRITE_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_WRITE_BIT; } -void i2c0_set_interrupt_enable(uint8_t en) +void i2c_set_interrupt_enable(uint32_t base, uint8_t en) { if (en) - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_INT_EN_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_INT_EN_BIT; else - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_INT_EN_BIT); + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_INT_EN_BIT); } -void i2c0_clear_irq_pending() +void i2c_clear_irq_pending(uint32_t base) { - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_INT_PENDING_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_INT_PENDING_BIT; } -uint8_t i2c0_get_irq_pending() +uint8_t i2c_get_irq_pending(uint32_t base) { - if (I2C0_REG(I2C_CTRL_REG_OFFSET) & (1 << I2C_CTRL_INT_PENDING_BIT)) + if (I2C_REG(base, I2C_CTRL_REG_OFFSET) & (1 << I2C_CTRL_INT_PENDING_BIT)) return 1; else return 0; } -void i2c0_master_set_info(uint8_t addr, uint8_t reg, uint8_t data) +void i2c_master_set_info(uint32_t base, uint8_t addr, uint8_t reg, uint8_t data) { - I2C0_REG(I2C_MASTER_DATA_REG_OFFSET) = (addr << I2C_MASTER_DATA_ADDRESS_OFFSET) | - (reg << I2C_MASTER_DATA_REGREG_OFFSET) | - (data << I2C_MASTER_DATA_DATA_OFFSET); + I2C_REG(base, I2C_MASTER_DATA_REG_OFFSET) = (addr << I2C_MASTER_DATA_ADDRESS_OFFSET) | + (reg << I2C_MASTER_DATA_REGREG_OFFSET) | + (data << I2C_MASTER_DATA_DATA_OFFSET); } -uint8_t i2c0_master_get_data() +uint8_t i2c_master_get_data(uint32_t base) { uint8_t data; - data = (I2C0_REG(I2C_MASTER_DATA_REG_OFFSET) >> I2C_MASTER_DATA_DATA_OFFSET) & I2C_MASTER_DATA_DATA_MASK; + data = (I2C_REG(base, I2C_MASTER_DATA_REG_OFFSET) >> I2C_MASTER_DATA_DATA_OFFSET) & I2C_MASTER_DATA_DATA_MASK; return data; } -void i2c0_slave_set_address(uint8_t addr) +void i2c_slave_set_address(uint32_t base, uint8_t addr) { - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(I2C_CTRL_SLAVE_ADDR_MASK << I2C_CTRL_SLAVE_ADDR_OFFSET); - I2C0_REG(I2C_CTRL_REG_OFFSET) |= addr << I2C_CTRL_SLAVE_ADDR_OFFSET; + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(I2C_CTRL_SLAVE_ADDR_MASK << I2C_CTRL_SLAVE_ADDR_OFFSET); + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= addr << I2C_CTRL_SLAVE_ADDR_OFFSET; } -void i2c0_slave_set_ready(uint8_t yes) +void i2c_slave_set_ready(uint32_t base, uint8_t yes) { if (yes) - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_SLAVE_RDY_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_SLAVE_RDY_BIT; else - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_SLAVE_RDY_BIT); + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_SLAVE_RDY_BIT); } -uint8_t i2c0_slave_op_read() +uint8_t i2c_slave_op_read(uint32_t base) { - if (I2C0_REG(I2C_CTRL_REG_OFFSET) & (1 << I2C_CTRL_SLAVE_WR_BIT)) + if (I2C_REG(base, I2C_CTRL_REG_OFFSET) & (1 << I2C_CTRL_SLAVE_WR_BIT)) return 1; else return 0; } -uint32_t i2c0_slave_get_op_address() +uint32_t i2c_slave_get_op_address(uint32_t base) { - return (I2C0_REG(I2C_SLAVE_ADDR_REG_OFFSET)); + return (I2C_REG(base, I2C_SLAVE_ADDR_REG_OFFSET)); } -uint32_t i2c0_slave_get_op_data() +uint32_t i2c_slave_get_op_data(uint32_t base) { - return (I2C0_REG(I2C_SLAVE_WDATA_REG_OFFSET)); + return (I2C_REG(base, I2C_SLAVE_WDATA_REG_OFFSET)); } -void i2c0_slave_set_rsp_data(uint32_t data) +void i2c_slave_set_rsp_data(uint32_t base, uint32_t data) { - I2C0_REG(I2C_SLAVE_RDATA_REG_OFFSET) = data; + I2C_REG(base, I2C_SLAVE_RDATA_REG_OFFSET) = data; } -void i2c0_start() +void i2c_start(uint32_t base) { - I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_START_BIT; + I2C_REG(base, I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_START_BIT; } -void i2c0_stop() +void i2c_stop(uint32_t base) { - I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_START_BIT); + I2C_REG(base, I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_START_BIT); } diff --git a/sdk/bsp/lib/spi.c b/sdk/bsp/lib/spi.c index 63694d8..58c0869 100644 --- a/sdk/bsp/lib/spi.c +++ b/sdk/bsp/lib/spi.c @@ -3,217 +3,217 @@ #include "../include/spi.h" -void spi0_set_clk_div(uint16_t div) +void spi_set_clk_div(uint32_t base, uint16_t div) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CLK_DIV_MASK << SPI_CTRL0_CLK_DIV_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= div << SPI_CTRL0_CLK_DIV_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CLK_DIV_MASK << SPI_CTRL0_CLK_DIV_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= div << SPI_CTRL0_CLK_DIV_OFFSET; } -void spi0_set_role_mode(spi_role_mode_e mode) +void spi_set_role_mode(uint32_t base, spi_role_mode_e mode) { if (mode == SPI_ROLE_MODE_MASTER) - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_ROLE_MODE_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_ROLE_MODE_BIT); else - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_ROLE_MODE_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_ROLE_MODE_BIT; } -void spi0_set_spi_mode(spi_spi_mode_e mode) +void spi_set_spi_mode(uint32_t base, spi_spi_mode_e mode) { switch (mode) { case SPI_MODE_STANDARD: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); break; case SPI_MODE_DUAL: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SPI_MODE_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SPI_MODE_OFFSET; break; case SPI_MODE_QUAD: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 2 << SPI_CTRL0_SPI_MODE_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SPI_MODE_MASK << SPI_CTRL0_SPI_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 2 << SPI_CTRL0_SPI_MODE_OFFSET; break; } } -void spi0_set_cp_mode(spi_cp_mode_e mode) +void spi_set_cp_mode(uint32_t base, spi_cp_mode_e mode) { switch (mode) { case SPI_CPOL_0_CPHA_0: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); break; case SPI_CPOL_0_CPHA_1: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_CP_MODE_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_CP_MODE_OFFSET; break; case SPI_CPOL_1_CPHA_0: - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 2 << SPI_CTRL0_CP_MODE_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_CP_MODE_MASK << SPI_CTRL0_CP_MODE_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 2 << SPI_CTRL0_CP_MODE_OFFSET; break; case SPI_CPOL_1_CPHA_1: - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 3 << SPI_CTRL0_CP_MODE_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 3 << SPI_CTRL0_CP_MODE_OFFSET; break; } } -void spi0_set_enable(uint8_t en) +void spi_set_enable(uint32_t base, uint8_t en) { if (en) - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_ENABLE_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_ENABLE_BIT; else - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_ENABLE_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_ENABLE_BIT); } -void spi0_set_interrupt_enable(uint8_t en) +void spi_set_interrupt_enable(uint32_t base, uint8_t en) { if (en) - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_INT_EN_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_INT_EN_BIT; else - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_INT_EN_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_INT_EN_BIT); } -void spi0_set_msb_first() +void spi_set_msb_first(uint32_t base) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_MSB_FIRST_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_MSB_FIRST_BIT; } -void spi0_set_lsb_first() +void spi_set_lsb_first(uint32_t base) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_MSB_FIRST_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_MSB_FIRST_BIT); } -void spi0_set_txdata(uint8_t data) +void spi_set_txdata(uint32_t base, uint8_t data) { - SPI0_REG(SPI_TXDATA_REG_OFFSET) |= data; + SPI_REG(base, SPI_TXDATA_REG_OFFSET) |= data; } -uint8_t spi0_get_rxdata() +uint8_t spi_get_rxdata(uint32_t base) { - return (SPI0_REG(SPI_RXDATA_REG_OFFSET)); + return (SPI_REG(base, SPI_RXDATA_REG_OFFSET)); } -uint8_t spi0_reset_rxfifo() +uint8_t spi_reset_rxfifo(uint32_t base) { uint8_t data; data = 0; - while (!(SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_EMPTY_BIT))) { - data = SPI0_REG(SPI_RXDATA_REG_OFFSET); + while (!(SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_EMPTY_BIT))) { + data = SPI_REG(base, SPI_RXDATA_REG_OFFSET); } return data; } -void spi0_set_ss_ctrl_by_sw(uint8_t yes) +void spi_set_ss_ctrl_by_sw(uint32_t base, uint8_t yes) { if (yes) - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SS_SW_CTRL_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SS_SW_CTRL_BIT; else - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_SS_SW_CTRL_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_SS_SW_CTRL_BIT); } -void spi0_set_ss_level(uint8_t level) +void spi_set_ss_level(uint32_t base, uint8_t level) { if (level) - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SS_LEVEL_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_SS_LEVEL_BIT; else - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_SS_LEVEL_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_SS_LEVEL_BIT); } -uint8_t spi0_tx_fifo_full() +uint8_t spi_tx_fifo_full(uint32_t base) { - if (SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_TX_FIFO_FULL_BIT)) + if (SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_TX_FIFO_FULL_BIT)) return 1; else return 0; } -uint8_t spi0_tx_fifo_empty() +uint8_t spi_tx_fifo_empty(uint32_t base) { - if (SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_TX_FIFO_EMPTY_BIT)) + if (SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_TX_FIFO_EMPTY_BIT)) return 1; else return 0; } -uint8_t spi0_rx_fifo_full() +uint8_t spi_rx_fifo_full(uint32_t base) { - if (SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_FULL_BIT)) + if (SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_FULL_BIT)) return 1; else return 0; } -uint8_t spi0_rx_fifo_empty() +uint8_t spi_rx_fifo_empty(uint32_t base) { - if (SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_EMPTY_BIT)) + if (SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_RX_FIFO_EMPTY_BIT)) return 1; else return 0; } -uint8_t spi0_get_interrupt_pending() +uint8_t spi_get_interrupt_pending(uint32_t base) { - if (SPI0_REG(SPI_CTRL0_REG_OFFSET) & (1 << SPI_CTRL0_INT_PENDING_BIT)) + if (SPI_REG(base, SPI_CTRL0_REG_OFFSET) & (1 << SPI_CTRL0_INT_PENDING_BIT)) return 1; else return 0; } -void spi0_clear_interrupt_pending() +void spi_clear_interrupt_pending(uint32_t base) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= (1 << SPI_CTRL0_INT_PENDING_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= (1 << SPI_CTRL0_INT_PENDING_BIT); } -void spi0_master_set_read() +void spi_master_set_read(uint32_t base) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_READ_BIT; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= 1 << SPI_CTRL0_READ_BIT; } -void spi0_master_set_write() +void spi_master_set_write(uint32_t base) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_READ_BIT); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(1 << SPI_CTRL0_READ_BIT); } -void spi0_master_set_ss_delay(uint8_t clk_num) +void spi_master_set_ss_delay(uint32_t base, uint8_t clk_num) { - SPI0_REG(SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SS_DELAY_MASK << SPI_CTRL0_SS_DELAY_OFFSET); - SPI0_REG(SPI_CTRL0_REG_OFFSET) |= (clk_num & SPI_CTRL0_SS_DELAY_MASK) << SPI_CTRL0_SS_DELAY_OFFSET; + SPI_REG(base, SPI_CTRL0_REG_OFFSET) &= ~(SPI_CTRL0_SS_DELAY_MASK << SPI_CTRL0_SS_DELAY_OFFSET); + SPI_REG(base, SPI_CTRL0_REG_OFFSET) |= (clk_num & SPI_CTRL0_SS_DELAY_MASK) << SPI_CTRL0_SS_DELAY_OFFSET; } -uint8_t spi0_master_transmiting() +uint8_t spi_master_transmiting(uint32_t base) { - if (SPI0_REG(SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_BUSY_BIT)) + if (SPI_REG(base, SPI_STATUS_REG_OFFSET) & (1 << SPI_STATUS_BUSY_BIT)) return 1; else return 0; } -void spi0_master_write_bytes(uint8_t write_data[], uint32_t count) +void spi_master_write_bytes(uint32_t base, uint8_t write_data[], uint32_t count) { uint32_t i; - spi0_master_set_write(); + spi_master_set_write(base); for (i = 0; i < count; i++) { - spi0_set_txdata(write_data[i]); - while (spi0_master_transmiting()); + spi_set_txdata(base, write_data[i]); + while (spi_master_transmiting(base)); } } -void spi0_master_read_bytes(uint8_t read_data[], uint32_t count) +void spi_master_read_bytes(uint32_t base, uint8_t read_data[], uint32_t count) { uint32_t i; - spi0_master_set_read(); + spi_master_set_read(base); for (i = 0; i < count; i++) { - spi0_set_txdata(0xff); - while (spi0_master_transmiting()); - read_data[i] = spi0_get_rxdata(); + spi_set_txdata(base, 0xff); + while (spi_master_transmiting(base)); + read_data[i] = spi_get_rxdata(base); } } diff --git a/sdk/bsp/lib/timer.c b/sdk/bsp/lib/timer.c index ac60063..f26ffda 100644 --- a/sdk/bsp/lib/timer.c +++ b/sdk/bsp/lib/timer.c @@ -3,57 +3,57 @@ #include "../include/timer.h" -void timer0_start(uint8_t en) +void timer_start(uint32_t base, uint8_t en) { if (en) - TIMER0_REG(TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_EN_BIT; + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_EN_BIT; else - TIMER0_REG(TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_EN_BIT); + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_EN_BIT); } -void timer0_set_value(uint32_t val) +void timer_set_value(uint32_t base, uint32_t val) { - TIMER0_REG(TIMER_VALUE_REG_OFFSET) = val; + TIMER_REG(base, TIMER_VALUE_REG_OFFSET) = val; } -void timer0_set_int_enable(uint8_t en) +void timer_set_int_enable(uint32_t base, uint8_t en) { if (en) - TIMER0_REG(TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_INT_EN_BIT; + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_INT_EN_BIT; else - TIMER0_REG(TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_INT_EN_BIT); + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_INT_EN_BIT); } -void timer0_clear_int_pending() +void timer_clear_int_pending(uint32_t base) { - TIMER0_REG(TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_INT_PENDING_BIT; + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_INT_PENDING_BIT; } -uint8_t timer0_get_int_pending() +uint8_t timer_get_int_pending(uint32_t base) { - if (TIMER0_REG(TIMER_CTRL_REG_OFFSET) & (1 << TIMER_CTRL_INT_PENDING_BIT)) + if (TIMER_REG(base, TIMER_CTRL_REG_OFFSET) & (1 << TIMER_CTRL_INT_PENDING_BIT)) return 1; else return 0; } -uint32_t timer0_get_current_count() +uint32_t timer_get_current_count(uint32_t base) { - return TIMER0_REG(TIMER_COUNT_REG_OFFSET); + return TIMER_REG(base, TIMER_COUNT_REG_OFFSET); } -void timer0_set_mode_auto_reload() +void timer_set_mode_auto_reload(uint32_t base) { - TIMER0_REG(TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_MODE_BIT; + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) |= 1 << TIMER_CTRL_MODE_BIT; } -void timer0_set_mode_ontshot() +void timer_set_mode_ontshot(uint32_t base) { - TIMER0_REG(TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_MODE_BIT); + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) &= ~(1 << TIMER_CTRL_MODE_BIT); } -void timer0_set_div(uint32_t div) +void timer_set_clk_div(uint32_t base, uint32_t div) { - TIMER0_REG(TIMER_CTRL_REG_OFFSET) &= ~(TIMER_CTRL_CLK_DIV_MASK << TIMER_CTRL_CLK_DIV_OFFSET); - TIMER0_REG(TIMER_CTRL_REG_OFFSET) |= div << TIMER_CTRL_CLK_DIV_OFFSET; + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) &= ~(TIMER_CTRL_CLK_DIV_MASK << TIMER_CTRL_CLK_DIV_OFFSET); + TIMER_REG(base, TIMER_CTRL_REG_OFFSET) |= div << TIMER_CTRL_CLK_DIV_OFFSET; } diff --git a/sdk/bsp/lib/uart.c b/sdk/bsp/lib/uart.c index 9a52f2f..328824d 100644 --- a/sdk/bsp/lib/uart.c +++ b/sdk/bsp/lib/uart.c @@ -7,24 +7,166 @@ // send one char to uart void uart0_putc(uint8_t c) { - while (UART0_REG(UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXFULL_BIT)); + while (UART_REG(UART0, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXFULL_BIT)); - UART0_REG(UART_TXDATA_REG_OFFSET) = c; + UART_REG(UART0, UART_TXDATA_REG_OFFSET) = c; } // Block, get one char from uart. uint8_t uart0_getc() { - while ((UART0_REG(UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT))); + while ((UART_REG(UART0, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT))); - return (UART0_REG(UART_RXDATA_REG_OFFSET) & 0xff); + return (UART_REG(UART0, UART_RXDATA_REG_OFFSET) & 0xff); +} + +// send one char to uart +void uart1_putc(uint8_t c) +{ + while (UART_REG(UART1, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXFULL_BIT)); + + UART_REG(UART1, UART_TXDATA_REG_OFFSET) = c; +} + +// Block, get one char from uart. +uint8_t uart1_getc() +{ + while ((UART_REG(UART1, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT))); + + return (UART_REG(UART1, UART_RXDATA_REG_OFFSET) & 0xff); +} + +// send one char to uart +void uart2_putc(uint8_t c) +{ + while (UART_REG(UART2, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXFULL_BIT)); + + UART_REG(UART2, UART_TXDATA_REG_OFFSET) = c; +} + +// Block, get one char from uart. +uint8_t uart2_getc() +{ + while ((UART_REG(UART2, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT))); + + return (UART_REG(UART2, UART_RXDATA_REG_OFFSET) & 0xff); } // 115200bps, 8 N 1 -void uart0_init(myputc put) +void uart_init(uint32_t base, myputc put) { // enable tx and rx - UART0_REG(UART_CTRL_REG_OFFSET) |= 0x3; + UART_REG(base, UART_CTRL_REG_OFFSET) |= (1 << UART_CTRL_TX_EN_BIT) | (1 << UART_CTRL_RX_EN_BIT); xdev_out(put); } + +void uart_tx_enable(uint32_t base, uint8_t en) +{ + if (en) + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_TX_EN_BIT; + else + UART_REG(base, UART_CTRL_REG_OFFSET) &= ~(1 << UART_CTRL_TX_EN_BIT); +} + +void uart_rx_enable(uint32_t base, uint8_t en) +{ + if (en) + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_RX_EN_BIT; + else + UART_REG(base, UART_CTRL_REG_OFFSET) &= ~(1 << UART_CTRL_RX_EN_BIT); +} + +void uart_tx_fifo_empty_int_enable(uint32_t base, uint8_t en) +{ + if (en) + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_TX_FIFO_EMPTY_INT_EN_BIT; + else + UART_REG(base, UART_CTRL_REG_OFFSET) &= ~(1 << UART_CTRL_TX_FIFO_EMPTY_INT_EN_BIT); +} + +void uart_rx_fifo_not_empty_int_enable(uint32_t base, uint8_t en) +{ + if (en) + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_RX_FIFO_NOT_EMPTY_INT_EN_BIT; + else + UART_REG(base, UART_CTRL_REG_OFFSET) &= ~(1 << UART_CTRL_RX_FIFO_NOT_EMPTY_INT_EN_BIT); +} + +void uart_set_baud_div(uint32_t base, uint32_t div) +{ + UART_REG(base, UART_CTRL_REG_OFFSET) &= ~(UART_CTRL_BAUD_DIV_MASK << UART_CTRL_BAUD_DIV_OFFSET); + UART_REG(base, UART_CTRL_REG_OFFSET) |= div << UART_CTRL_BAUD_DIV_OFFSET; +} + +void uart_reset_tx_fifo(uint32_t base) +{ + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_TX_FIFO_RST_BIT; +} + +void uart_reset_rx_fifo(uint32_t base) +{ + UART_REG(base, UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_RX_FIFO_RST_BIT; +} + +uint8_t uart_tx_fifo_full(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXFULL_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_rx_fifo_full(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXFULL_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_tx_fifo_empty(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXEMPTY_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_rx_fifo_empty(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_tx_idle(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXIDLE_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_rx_idle(uint32_t base) +{ + if (UART_REG(base, UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXIDLE_BIT)) + return 1; + else + return 0; +} + +uint8_t uart_get_rx_fifo_data(uint32_t base) +{ + uint8_t data; + + data = UART_REG(base, UART_RXDATA_REG_OFFSET); + + return data; +} + +void uart_set_tx_fifo_data(uint32_t base, uint8_t data) +{ + UART_REG(base, UART_TXDATA_REG_OFFSET) = data; +} diff --git a/sdk/examples/coremark/core_portme.c b/sdk/examples/coremark/core_portme.c index 2f1cd7e..35fa382 100644 --- a/sdk/examples/coremark/core_portme.c +++ b/sdk/examples/coremark/core_portme.c @@ -57,5 +57,5 @@ void portable_init(core_portable *p, int *argc, char *argv[]) { pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); - uart0_init(uart0_putc); + uart_init(UART0, uart0_putc); } diff --git a/sdk/examples/freertos/Source/portable/RISC-V/port.c b/sdk/examples/freertos/Source/portable/RISC-V/port.c index b17e469..72da609 100644 --- a/sdk/examples/freertos/Source/portable/RISC-V/port.c +++ b/sdk/examples/freertos/Source/portable/RISC-V/port.c @@ -134,24 +134,24 @@ volatile uint32_t ulHartId; #endif #ifdef SIMULATION - timer0_set_div(50); - timer0_set_value(100); // 100us period + timer_set_clk_div(TIMER0, 50); + timer_set_value(TIMER0, 100); // 100us period #else - timer0_set_div(configCPU_CLOCK_HZ/1000000); - timer0_set_value(1000000/configTICK_RATE_HZ); // 10ms period + timer_set_clk_div(TIMER0, configCPU_CLOCK_HZ/1000000); + timer_set_value(TIMER0, 1000000/configTICK_RATE_HZ); // 10ms period #endif - timer0_set_int_enable(1); - timer0_set_mode_auto_reload(); - rvic_set_irq_prio_level(0, 1); - rvic_irq_enable(0); - timer0_start(1); // start timer + timer_set_int_enable(TIMER0, 1); + timer_set_mode_auto_reload(TIMER0); + rvic_set_irq_prio_level(RVIC_TIMER0_INT_ID, 1); + rvic_irq_enable(RVIC_TIMER0_INT_ID); + timer_start(TIMER0, 1); // start timer } /*-----------------------------------------------------------*/ void xPortClearTimerIntPending() { - timer0_clear_int_pending(); - rvic_clear_irq_pending(0); + timer_clear_int_pending(TIMER0); + rvic_clear_irq_pending(RVIC_TIMER0_INT_ID); } BaseType_t xPortStartScheduler( void ) diff --git a/sdk/examples/gpio/main.c b/sdk/examples/gpio/main.c index ff49474..39ee5d5 100644 --- a/sdk/examples/gpio/main.c +++ b/sdk/examples/gpio/main.c @@ -18,19 +18,20 @@ int main() // gpio9双沿中断模式 gpio_set_interrupt_mode(GPIO9, GPIO_INTR_DOUBLE_EDGE); // 使能RVIC中断 - rvic_irq_enable(RVIC_INT_ID_9); + rvic_irq_enable(RVIC_GPIO9_INT_ID); // gpio9中断优先级为1 - rvic_set_irq_prio_level(RVIC_INT_ID_9, 1); + rvic_set_irq_prio_level(RVIC_GPIO9_INT_ID, 1); // 使能全局中断 global_irq_enable(); while (1); } +// GPIO9中断处理函数 void gpio9_irq_handler() { gpio_clear_intr_pending(GPIO9); - rvic_clear_irq_pending(RVIC_INT_ID_9); + rvic_clear_irq_pending(RVIC_GPIO9_INT_ID); // 如果GPIO9输入高 if (gpio_get_input_data(GPIO9)) diff --git a/sdk/examples/hello_world/main.c b/sdk/examples/hello_world/main.c index 7a10fc3..75626af 100644 --- a/sdk/examples/hello_world/main.c +++ b/sdk/examples/hello_world/main.c @@ -11,7 +11,7 @@ int main() #ifdef SIMULATION sim_ctrl_init(); #else - uart0_init(uart0_putc); + uart_init(UART0, uart0_putc); pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); #endif diff --git a/sdk/examples/i2c_master/main.c b/sdk/examples/i2c_master/main.c index f07ebd0..af43f7e 100644 --- a/sdk/examples/i2c_master/main.c +++ b/sdk/examples/i2c_master/main.c @@ -15,9 +15,9 @@ static volatile uint8_t i2c_done; static void i2c_master_write(uint8_t addr, uint8_t data) { i2c_done = 0; - i2c0_master_set_write(1); - i2c0_master_set_info(SLAVE_ADDR, addr, data); - i2c0_start(); + i2c_master_set_write(I2C0, 1); + i2c_master_set_info(I2C0, SLAVE_ADDR, addr, data); + i2c_start(I2C0); while (!i2c_done); } @@ -25,41 +25,48 @@ static void i2c_master_write(uint8_t addr, uint8_t data) static uint8_t i2c_master_read(uint8_t addr) { i2c_done = 0; - i2c0_master_set_write(0); - i2c0_master_set_info(SLAVE_ADDR, addr, 0); - i2c0_start(); + i2c_master_set_write(I2C0, 0); + i2c_master_set_info(I2C0, SLAVE_ADDR, addr, 0); + i2c_start(I2C0); while (!i2c_done); - return (i2c0_master_get_data()); + return (i2c_master_get_data(I2C0)); } int main() { uint8_t data, i; - uart0_init(uart0_putc); + // UART0引脚配置 pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); + // I2C0引脚配置 pinmux_set_io6_func(IO6_I2C0_SCL); pinmux_set_io8_func(IO8_I2C0_SDA); - - i2c0_set_clk(0x7D); // 200KHZ - i2c0_set_mode(I2C_MODE_MASTER); - i2c0_set_interrupt_enable(1); - - rvic_set_irq_prio_level(RVIC_INT_ID_4, 1); - rvic_irq_enable(RVIC_INT_ID_4); + // 初始化串口0 + uart_init(UART0, uart0_putc); + // 设置I2C0时钟, 200KHZ + i2c_set_clk(I2C0, 0x7D); + // 设置I2C0 master模式 + i2c_set_mode(I2C0, I2C_MODE_MASTER); + // 使能I2C0模块中断 + i2c_set_interrupt_enable(I2C0, 1); + // 设置I2C0中断优先级为1 + rvic_set_irq_prio_level(RVIC_I2C0_INT_ID, 1); + // 使能RVIC中断 + rvic_irq_enable(RVIC_I2C0_INT_ID); + // 使能CPU中断 global_irq_enable(); - // 写 + // 写测试 for (i = 0; i < 10; i++) { i2c_master_write(i, i); xprintf("write[%d] = 0x%x\n", i, i); busy_wait(100 * 1000); } - // 读 + // 读测试 for (i = 0; i < 10; i++) { data = i2c_master_read(i); xprintf("read[%d] = 0x%x\n", i, data); @@ -68,10 +75,11 @@ int main() while (1); } +// I2C0中断处理函数 void i2c0_irq_handler() { i2c_done = 1; - i2c0_clear_irq_pending(); - rvic_clear_irq_pending(RVIC_INT_ID_4); + i2c_clear_irq_pending(I2C0); + rvic_clear_irq_pending(RVIC_I2C0_INT_ID); } diff --git a/sdk/examples/i2c_slave/main.c b/sdk/examples/i2c_slave/main.c index 9d89525..cde23db 100644 --- a/sdk/examples/i2c_slave/main.c +++ b/sdk/examples/i2c_slave/main.c @@ -20,48 +20,59 @@ static volatile op_e op; int main() { + // UART0引脚配置 pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); + // I2C0引脚配置 pinmux_set_io6_func(IO6_I2C0_SCL); pinmux_set_io8_func(IO8_I2C0_SDA); + // 初始化串口0 + uart_init(UART0, uart0_putc); + // 设置I2C0为slave模式 + i2c_set_mode(I2C0, I2C_MODE_SLAVE); + // 设置slave地址 + i2c_slave_set_address(I2C0, SLAVE_ADDR); + // 使能I2C0中断 + i2c_set_interrupt_enable(I2C0, 1); + // I2C0 ready + i2c_slave_set_ready(I2C0, 1); - uart0_init(uart0_putc); - - i2c0_set_mode(I2C_MODE_SLAVE); - i2c0_slave_set_address(SLAVE_ADDR); - i2c0_slave_set_ready(1); - i2c0_set_interrupt_enable(1); - - rvic_set_irq_prio_level(RVIC_INT_ID_4, 1); - rvic_irq_enable(RVIC_INT_ID_4); + // 设置I2C0中断优先级为1 + rvic_set_irq_prio_level(RVIC_I2C0_INT_ID, 1); + // 使能I2C0中断 + rvic_irq_enable(RVIC_I2C0_INT_ID); + // 使能全局中断 global_irq_enable(); - i2c0_start(); + // 启动I2C0 + i2c_start(I2C0); op = OP_NONE; while (1) { if (op == OP_READ) { - xprintf("op read addr = 0x%x\n", i2c0_slave_get_op_address()); - i2c0_slave_set_rsp_data(0x12345678); - i2c0_slave_set_ready(1); + xprintf("master read addr = 0x%x\n", i2c_slave_get_op_address(I2C0)); + i2c_slave_set_rsp_data(I2C0, 0x12345678); + i2c_slave_set_ready(I2C0, 1); op = OP_NONE; } else if (op == OP_WRITE) { - xprintf("op write addr = 0x%x\n", i2c0_slave_get_op_address()); - xprintf("op write data = 0x%x\n", i2c0_slave_get_op_data()); - i2c0_slave_set_ready(1); + xprintf("master write addr = 0x%x\n", i2c_slave_get_op_address(I2C0)); + xprintf("master write data = 0x%x\n", i2c_slave_get_op_data(I2C0)); + i2c_slave_set_ready(I2C0, 1); op = OP_NONE; } } } +// I2C0中断处理函数 void i2c0_irq_handler() { - if (i2c0_slave_op_read()) + // master是否为读操作 + if (i2c_slave_op_read(I2C0)) op = OP_READ; else op = OP_WRITE; - i2c0_clear_irq_pending(); - rvic_clear_irq_pending(RVIC_INT_ID_4); + i2c_clear_irq_pending(I2C0); + rvic_clear_irq_pending(RVIC_I2C0_INT_ID); } diff --git a/sdk/examples/int_preempt/main.c b/sdk/examples/int_preempt/main.c index e01b027..f8c0389 100644 --- a/sdk/examples/int_preempt/main.c +++ b/sdk/examples/int_preempt/main.c @@ -8,27 +8,40 @@ #include "../../bsp/include/xprintf.h" #include "../../bsp/include/pinmux.h" +/* 1.设置GPIO9中断优先级比timer0中断优先级高. + * 2.count初始值为0，在timer0中断处理程序里等待count计数值为3, GPIO9每次中断触发时将count计数加1， + * 当count计数值等于3时，将GPIO7状态每500ms取反. +*/ + static volatile uint32_t count; int main() { count = 0; + // 配置UART0引脚 pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); - - uart0_init(uart0_putc); - - timer0_set_div(25); - timer0_set_value(10000); // 10ms period - timer0_clear_int_pending(); - timer0_set_int_enable(1); - timer0_set_mode_ontshot(); + // 初始化UART0 + uart_init(UART0, uart0_putc); + // 设置timer0 25分频 + timer_set_clk_div(TIMER0, 25); + // timer0定时10ms + timer_set_value(TIMER0, 10000); + // 清timer0中断pending + timer_clear_int_pending(TIMER0); + // 使能timer0中断 + timer_set_int_enable(TIMER0, 1); + // 设置timer0自动装载模式 + timer_set_mode_ontshot(TIMER0); // timer0中断优先级为1 - rvic_set_irq_prio_level(RVIC_INT_ID_0, 1); + rvic_set_irq_prio_level(RVIC_TIMER0_INT_ID, 1); + // 使能RVIC中断 + rvic_irq_enable(RVIC_TIMER0_INT_ID); + // 使能全局中断 global_irq_enable(); - rvic_irq_enable(RVIC_INT_ID_0); - timer0_start(1); + // 启动timer0 + timer_start(TIMER0, 1); // IO7用作GPIO7 pinmux_set_io7_func(IO7_GPIO7); @@ -40,9 +53,9 @@ int main() gpio_set_mode(GPIO9, GPIO_MODE_INPUT); // gpio9双沿中断 gpio_set_interrupt_mode(GPIO9, GPIO_INTR_DOUBLE_EDGE); - rvic_irq_enable(RVIC_INT_ID_9); + rvic_irq_enable(RVIC_GPIO9_INT_ID); // gpio9中断优先级为2 - rvic_set_irq_prio_level(RVIC_INT_ID_9, 2); + rvic_set_irq_prio_level(RVIC_GPIO9_INT_ID, 2); while (1) { if (count == 3) { @@ -52,10 +65,11 @@ int main() } } +// timer0中断处理函数 void timer0_irq_handler() { - timer0_clear_int_pending(); - rvic_clear_irq_pending(0); + timer_clear_int_pending(TIMER0); + rvic_clear_irq_pending(RVIC_TIMER0_INT_ID); xprintf("timer0 isr enter\n"); // GPIO0对应LED为灭 @@ -66,11 +80,13 @@ void timer0_irq_handler() xprintf("timer0 isr exit\n"); } +// GPIO9中断处理函数 void gpio9_irq_handler() { gpio_clear_intr_pending(GPIO9); - rvic_clear_irq_pending(RVIC_INT_ID_9); + rvic_clear_irq_pending(RVIC_GPIO9_INT_ID); xprintf("gpio1 isr\n"); + count++; } diff --git a/sdk/examples/spi_master/flash_n25q.c b/sdk/examples/spi_master/flash_n25q.c index cd4fda8..58f206d 100644 --- a/sdk/examples/spi_master/flash_n25q.c +++ b/sdk/examples/spi_master/flash_n25q.c @@ -18,15 +18,15 @@ static uint8_t current_spi_mode; void flash_n25q_init(uint16_t clk_div) { - spi0_set_clk_div(clk_div); - spi0_set_role_mode(SPI_ROLE_MODE_MASTER); - spi0_set_spi_mode(SPI_MODE_STANDARD); - spi0_set_cp_mode(SPI_CPOL_0_CPHA_0); - spi0_set_msb_first(); - spi0_master_set_ss_delay(1); - spi0_set_ss_level(1); - spi0_set_ss_ctrl_by_sw(1); - spi0_set_enable(1); + spi_set_clk_div(SPI0, clk_div); + spi_set_role_mode(SPI0, SPI_ROLE_MODE_MASTER); + spi_set_spi_mode(SPI0, SPI_MODE_STANDARD); + spi_set_cp_mode(SPI0, SPI_CPOL_0_CPHA_0); + spi_set_msb_first(SPI0); + spi_master_set_ss_delay(SPI0, 1); + spi_set_ss_level(SPI0, 1); + spi_set_ss_ctrl_by_sw(SPI0, 1); + spi_set_enable(SPI0, 1); current_spi_mode = SPI_MODE_STANDARD; } @@ -42,9 +42,9 @@ void flash_n25q_write_enable(uint8_t en) else cmd = CMD_WRITE_DISABLE; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_set_ss_level(SPI0, 1); } // 读寄存器 @@ -52,10 +52,10 @@ uint8_t flash_n25q_read_reg(uint8_t cmd) { uint8_t data; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_read_bytes(&data, 1); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_read_bytes(SPI0, &data, 1); + spi_set_ss_level(SPI0, 1); return data; } @@ -63,10 +63,10 @@ uint8_t flash_n25q_read_reg(uint8_t cmd) // 写寄存器 void flash_n25q_write_reg(uint8_t cmd, uint8_t data) { - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_write_bytes(&data, 1); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_write_bytes(SPI0, &data, 1); + spi_set_ss_level(SPI0, 1); } // 读状态寄存器 @@ -104,16 +104,16 @@ void flash_n25q_read(uint8_t data[], uint32_t len, uint32_t addr) tran_addr[1] = (addr >> 8) & 0xff; tran_addr[2] = (addr >> 0) & 0xff; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_write_bytes(tran_addr, 3); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_write_bytes(SPI0, tran_addr, 3); if (current_spi_mode != SPI_MODE_STANDARD) { for (i = 0; i < (DUMMY_CNT >> 1); i++) - spi0_master_read_bytes(data, 1); - spi0_reset_rxfifo(); + spi_master_read_bytes(SPI0, data, 1); + spi_reset_rxfifo(SPI0); } - spi0_master_read_bytes(data, len); - spi0_set_ss_level(1); + spi_master_read_bytes(SPI0, data, len); + spi_set_ss_level(SPI0, 1); } static void sector_erase(uint8_t cmd, uint32_t addr) @@ -126,10 +126,10 @@ static void sector_erase(uint8_t cmd, uint32_t addr) tran_addr[1] = (addr >> 8) & 0xff; tran_addr[2] = (addr >> 0) & 0xff; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_write_bytes(tran_addr, 3); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_write_bytes(SPI0, tran_addr, 3); + spi_set_ss_level(SPI0, 1); while (flash_n25q_is_busy()); @@ -167,11 +167,11 @@ void flash_n25q_page_program(uint8_t data[], uint32_t len, uint32_t page) cmd = CMD_PAGE_PROGRAM; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_write_bytes(tran_addr, 3); - spi0_master_write_bytes(data, len); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_write_bytes(SPI0, tran_addr, 3); + spi_master_write_bytes(SPI0, data, len); + spi_set_ss_level(SPI0, 1); while (flash_n25q_is_busy()); @@ -255,10 +255,10 @@ n25q_id_t flash_n25q_read_id() else cmd = CMD_MULTI_IO_READ_ID; - spi0_set_ss_level(0); - spi0_master_write_bytes(&cmd, 1); - spi0_master_read_bytes(data, 3); - spi0_set_ss_level(1); + spi_set_ss_level(SPI0, 0); + spi_master_write_bytes(SPI0, &cmd, 1); + spi_master_read_bytes(SPI0, data, 3); + spi_set_ss_level(SPI0, 1); id.manf_id = data[0]; id.mem_type = data[1]; diff --git a/sdk/examples/spi_master/main.c b/sdk/examples/spi_master/main.c index e487664..1ae8fc6 100644 --- a/sdk/examples/spi_master/main.c +++ b/sdk/examples/spi_master/main.c @@ -15,7 +15,7 @@ uint8_t program_data[BUFFER_SIZE]; uint8_t read_data[BUFFER_SIZE]; - +// 标准三线SPI测试 static void standard_spi_test() { uint16_t i; @@ -23,6 +23,7 @@ static void standard_spi_test() xprintf("Standard SPI test started...\n"); + // 读flash ID id = flash_n25q_read_id(); xprintf("manf id = 0x%2x\n", id.manf_id); xprintf("mem type = 0x%2x\n", id.mem_type); @@ -50,6 +51,7 @@ static void standard_spi_test() xprintf("Standard SPI test end...\n"); } +// QSPI测试 static void quad_spi_test() { uint16_t i; @@ -61,8 +63,9 @@ static void quad_spi_test() // 使能N25Q QSPI模式 flash_n25q_enable_quad_mode(1); // 使能SPI控制器QSPI模式 - spi0_set_spi_mode(SPI_MODE_QUAD); + spi_set_spi_mode(SPI0, SPI_MODE_QUAD); + // 读flash ID id = flash_n25q_read_id(); xprintf("manf id = 0x%2x\n", id.manf_id); xprintf("mem type = 0x%2x\n", id.mem_type); @@ -89,7 +92,7 @@ static void quad_spi_test() // 失能N25Q QSPI模式 flash_n25q_enable_quad_mode(0); - spi0_set_spi_mode(SPI_MODE_STANDARD); + spi_set_spi_mode(SPI0, SPI_MODE_STANDARD); xprintf("Quad SPI test end...\n"); } @@ -107,7 +110,7 @@ int main() pinmux_set_io14_func(IO14_SPI_DQ2); pinmux_set_io15_func(IO15_SPI_DQ3); - uart0_init(uart0_putc); + uart_init(UART0, uart0_putc); flash_n25q_init(5); standard_spi_test(); diff --git a/sdk/examples/spi_master2/.gitignore b/sdk/examples/spi_master2/.gitignore new file mode 100644 index 0000000..80a4578 --- /dev/null +++ b/sdk/examples/spi_master2/.gitignore @@ -0,0 +1,8 @@ +# Object files +*.o +*.ko +*.obj +*.bin +*.dump +*.mem +spi_master diff --git a/sdk/examples/spi_master2/Makefile b/sdk/examples/spi_master2/Makefile new file mode 100644 index 0000000..e5f03e7 --- /dev/null +++ b/sdk/examples/spi_master2/Makefile @@ -0,0 +1,21 @@ +RISCV_ARCH := rv32im +RISCV_ABI := ilp32 +RISCV_MCMODEL := medlow + + +TARGET = spi_master + + +#CFLAGS += -DSIMULATION +#CFLAGS += -O2 +#ASM_SRCS += +#LDFLAGS += +#INCLUDES += -I. + +C_SRCS := \ + main.c \ + flash_w25q.c + + +BSP_DIR = ../../bsp +include ../../bsp/bsp.mk diff --git a/sdk/examples/spi_master2/README.md b/sdk/examples/spi_master2/README.md new file mode 100644 index 0000000..9f12e40 --- /dev/null +++ b/sdk/examples/spi_master2/README.md @@ -0,0 +1 @@ +spi_master例程。 \ No newline at end of file diff --git a/sdk/examples/spi_master2/flash_w25q.c b/sdk/examples/spi_master2/flash_w25q.c new file mode 100644 index 0000000..89a0358 --- /dev/null +++ b/sdk/examples/spi_master2/flash_w25q.c @@ -0,0 +1,116 @@ +#include + +#include "../../bsp/include/spi.h" +#include "../../bsp/include/rvic.h" +#include "../../bsp/include/utils.h" +#include "flash_w25q.h" + + +void flash_w25q_init(uint16_t clk_div) +{ + spi0_set_clk_div(clk_div); + spi0_set_role_mode(SPI_ROLE_MODE_MASTER); + spi0_set_spi_mode(SPI_MODE_STANDARD); + spi0_set_cp_mode(SPI_CPOL_0_CPHA_0); + spi0_set_msb_first(); + spi0_master_set_ss_delay(1); + spi0_set_ss_level(1); + spi0_set_ss_ctrl_by_sw(1); + spi0_set_enable(1); +} + +uint8_t flash_w25q_read_reg(uint8_t cmd) +{ + uint8_t data; + + spi0_set_ss_level(0); + spi0_master_write_bytes(&cmd, 1); + spi0_master_read_bytes(&data, 1); + spi0_set_ss_level(1); + + return data; +} + +uint8_t flash_w25q_write_reg(uint8_t cmd, uint8_t data) +{ + spi0_set_ss_level(0); + spi0_master_write_bytes(&cmd, 1); + spi0_master_write_bytes(&data, 1); + spi0_set_ss_level(1); +} + +uint8_t flash_w25q_send_cmd(uint8_t cmd) +{ + spi0_set_ss_level(0); + spi0_master_write_bytes(&cmd, 1); + spi0_set_ss_level(1); +} + +void flash_w25q_volatile_status_reg_write_enable() +{ + flash_w25q_send_cmd(CMD_WRITE_ENABLE_FOR_VOL_STATUS_REG); +} + +// 读flash ID +w25q_id_t flash_w25q_read_id() +{ + w25q_id_t id; + uint8_t cmd; + uint8_t data[2]; + uint8_t addr[3]; + + cmd = CMD_READ_ID; + addr[0] = 0x0; + addr[1] = 0x0; + addr[2] = 0x0; + + spi0_set_ss_level(0); + spi0_master_write_bytes(&cmd, 1); + spi0_master_write_bytes(addr, 3); + spi0_master_read_bytes(data, 2); + spi0_set_ss_level(1); + + id.manf_id = data[0]; + id.device_id = data[1]; + + return id; +} + +void flash_w25q_enable_qspi(uint8_t en) +{ + uint8_t data; + + flash_w25q_volatile_status_reg_write_enable(); + data = flash_w25q_read_reg(CMD_READ_STATUS_REG2); + if (en) + data |= 1 << 1; + else + data &= ~(1 << 1); + flash_w25q_write_reg(CMD_WRITE_STATUS_REG2, data); +} + +w25q_id_t flash_w25q_read_id_quad() +{ + w25q_id_t id; + uint8_t cmd; + uint8_t data[2]; + uint8_t addr[3]; + + cmd = CMD_READ_ID_QUAD; + addr[0] = 0x0; + addr[1] = 0x0; + addr[2] = 0x0; + + spi0_set_ss_level(0); + spi0_master_write_bytes(&cmd, 1); + spi0_set_spi_mode(SPI_MODE_QUAD); + spi0_master_write_bytes(addr, 3); + spi0_master_read_bytes(data, 2); + spi0_master_read_bytes(data, 2); + spi0_set_ss_level(1); + + id.manf_id = data[0]; + id.device_id = data[1]; + + return id; +} diff --git a/sdk/examples/spi_master2/flash_w25q.h b/sdk/examples/spi_master2/flash_w25q.h new file mode 100644 index 0000000..219811e --- /dev/null +++ b/sdk/examples/spi_master2/flash_w25q.h @@ -0,0 +1,24 @@ +#ifndef _FLASH_W25Q_H_ +#define _FLASH_W25Q_H_ + + + +#define CMD_READ_ID (0x90) +#define CMD_READ_ID_QUAD (0x94) +#define CMD_READ_STATUS_REG2 (0x35) +#define CMD_WRITE_STATUS_REG2 (0x31) +#define CMD_WRITE_ENABLE_FOR_VOL_STATUS_REG (0x50) + + +typedef struct { + uint8_t manf_id; + uint8_t device_id; +} w25q_id_t; + +void flash_w25q_init(uint16_t clk_div); +w25q_id_t flash_w25q_read_id(); +void flash_w25q_enable_qspi(uint8_t en); +w25q_id_t flash_w25q_read_id_quad(); + + +#endif diff --git a/sdk/examples/spi_master2/main.c b/sdk/examples/spi_master2/main.c new file mode 100644 index 0000000..9087f3c --- /dev/null +++ b/sdk/examples/spi_master2/main.c @@ -0,0 +1,44 @@ +#include + +#include "../../bsp/include/uart.h" +#include "../../bsp/include/spi.h" +#include "../../bsp/include/xprintf.h" +#include "../../bsp/include/utils.h" +#include "../../bsp/include/rvic.h" +#include "../../bsp/include/pinmux.h" +#include "../../bsp/include/sim_ctrl.h" +#include "flash_w25q.h" + + + +int main() +{ + w25q_id_t id; + + pinmux_set_io0_func(IO0_UART0_TX); + pinmux_set_io3_func(IO3_UART0_RX); + + pinmux_set_io6_func(IO6_SPI_CLK); + pinmux_set_io8_func(IO8_SPI_SS); + pinmux_set_io1_func(IO1_SPI_DQ0); + pinmux_set_io2_func(IO2_SPI_DQ1); + pinmux_set_io4_func(IO4_SPI_DQ2); + pinmux_set_io5_func(IO5_SPI_DQ3); + + uart0_init(uart0_putc); + flash_w25q_init(5); + + xprintf("read id:\n"); + id = flash_w25q_read_id(); + xprintf("manf id = 0x%2x\n", id.manf_id); + xprintf("device id = 0x%2x\n", id.device_id); + + flash_w25q_enable_qspi(1); + xprintf("quad read id:\n"); + id = flash_w25q_read_id_quad(); + xprintf("manf id = 0x%2x\n", id.manf_id); + xprintf("device id = 0x%2x\n", id.device_id); + flash_w25q_enable_qspi(0); + + while (1); +} diff --git a/sdk/examples/timer/main.c b/sdk/examples/timer/main.c index ff67c30..e097488 100644 --- a/sdk/examples/timer/main.c +++ b/sdk/examples/timer/main.c @@ -13,19 +13,21 @@ int main() count = 0; #ifdef SIMULATION - timer0_set_div(50); - timer0_set_value(100); // 100us period - timer0_clear_int_pending(); - timer0_set_int_enable(1); - timer0_set_mode_auto_reload(); - rvic_set_irq_prio_level(0, 1); + + timer_set_clk_div(TIMER0, 50); + timer_set_value(TIMER0, 100); // 100us period + timer_clear_int_pending(TIMER0); + timer_set_int_enable(TIMER0, 1); + timer_set_mode_auto_reload(TIMER0); + rvic_set_irq_prio_level(RVIC_TIMER0_INT_ID, 1); + rvic_irq_enable(RVIC_TIMER0_INT_ID); global_irq_enable(); - rvic_irq_enable(0); - timer0_start(1); + + timer_start(TIMER0, 1); while (1) { if (count == 3) { - timer0_start(0); + timer_start(TIMER0, 0); // TODO: do something set_test_pass(); break; @@ -33,35 +35,50 @@ int main() } return 0; + #else - timer0_set_div(25); - timer0_set_value(10000); // 10ms period - timer0_clear_int_pending(); - timer0_set_int_enable(1); - timer0_set_mode_auto_reload(); - rvic_set_irq_prio_level(0, 1); + + // timer0时钟25分频，即1MHZ + timer_set_clk_div(TIMER0, 25); + // timer0定时时间10ms + timer_set_value(TIMER0, 10000); + // 清timer0中断pending + timer_clear_int_pending(TIMER0); + // 使能timer0中断 + timer_set_int_enable(TIMER0, 1); + // 设置timer0自动装载模式 + timer_set_mode_auto_reload(TIMER0); + // 设置timer0中断优先级为1 + rvic_set_irq_prio_level(RVIC_TIMER0_INT_ID, 1); + // 使能RVIC中断 + rvic_irq_enable(RVIC_TIMER0_INT_ID); + // 使能全局中断 global_irq_enable(); - rvic_irq_enable(0); - timer0_start(1); + + // 启动timer0 + timer_start(TIMER0, 1); // IO7用作GPIO7 pinmux_set_io7_func(IO7_GPIO7); + // GPIO7输出使能 gpio_set_mode(GPIO7, GPIO_MODE_OUTPUT); while (1) { // 500ms if (count == 50) { count = 0; + // 取反GPIO7状态 gpio_set_output_toggle(GPIO7); // toggle led } } #endif } +// timer0中断处理函数 void timer0_irq_handler() { - count++; + timer_clear_int_pending(TIMER0); + rvic_clear_irq_pending(RVIC_TIMER0_INT_ID); - timer0_clear_int_pending(); - rvic_clear_irq_pending(0); + count++; } diff --git a/sdk/examples/uart_int/main.c b/sdk/examples/uart_int/main.c index 341bb00..d9ac1c6 100644 --- a/sdk/examples/uart_int/main.c +++ b/sdk/examples/uart_int/main.c @@ -29,52 +29,59 @@ static void uart_putc(uint8_t c) global_irq_disable(); fifo.tct++; // 使能TX FIFO空中断 - UART0_REG(UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_TX_FIFO_EMPTY_INT_EN_BIT; + uart_tx_fifo_empty_int_enable(UART0, 1); global_irq_enable(); } int main() { + // UART0引脚配置 pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); - - uart0_init(uart_putc); - rvic_irq_enable(1); - rvic_set_irq_prio_level(1, 1); + // UART0初始化 + uart_init(UART0, uart_putc); + // 使能RVIC中断 + rvic_irq_enable(RVIC_UART0_INT_ID); + // 设置UART0中断优先级为1 + rvic_set_irq_prio_level(RVIC_UART0_INT_ID, 1); // 使能RX FIFO非空中断 - UART0_REG(UART_CTRL_REG_OFFSET) |= 1 << UART_CTRL_RX_FIFO_NOT_EMPTY_INT_EN_BIT; + uart_rx_fifo_not_empty_int_enable(UART0, 1); + // 使能全局中断 global_irq_enable(); + fifo.tri = 0; fifo.twi = 0; fifo.tct = 0; xprintf("uart interrupt test\n"); while (1); } +// UART0中断处理函数 void uart0_irq_handler() { uint16_t i, count, index; uint8_t data; // 如果RX FIFO非空 - while (!(UART0_REG(UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_RXEMPTY_BIT))) { - data = UART0_REG(UART_RXDATA_REG_OFFSET); - UART0_REG(UART_TXDATA_REG_OFFSET) = data; + while (!uart_rx_fifo_empty(UART0)) { + data = uart_get_rx_fifo_data(UART0); + uart_set_tx_fifo_data(UART0, data); } // 如果TX FIFO为空 - if ((UART0_REG(UART_STATUS_REG_OFFSET) & (1 << UART_STATUS_TXEMPTY_BIT)) && - (fifo.tct > 0)) { - + if (uart_tx_fifo_empty(UART0) && (fifo.tct > 0)) { count = fifo.tct; - if (count > 8) - count = 8; + if (count > UART_TX_FIFO_LEN) + count = UART_TX_FIFO_LEN; for (index = 0; index < count; index++) { fifo.tct--; i = fifo.tri; - UART0_REG(UART_TXDATA_REG_OFFSET) = fifo.tbuf[i]; + // 发送数据 + uart_set_tx_fifo_data(UART0, fifo.tbuf[i]); fifo.tri = ++i % UART_TXB; } + // 如果发完数据，则关闭TX FIFO空中断 if (fifo.tct == 0) - UART0_REG(UART_CTRL_REG_OFFSET) &= ~(1 << UART_CTRL_TX_FIFO_EMPTY_INT_EN_BIT); + uart_tx_fifo_empty_int_enable(UART0, 0); } - rvic_clear_irq_pending(1); + + rvic_clear_irq_pending(RVIC_UART0_INT_ID); } diff --git a/sdk/examples/uart_loopback/main.c b/sdk/examples/uart_loopback/main.c index e687771..8888595 100644 --- a/sdk/examples/uart_loopback/main.c +++ b/sdk/examples/uart_loopback/main.c @@ -7,9 +7,11 @@ int main() { - uart0_init(uart0_putc); + // UART0引脚配置 pinmux_set_io0_func(IO0_UART0_TX); pinmux_set_io3_func(IO3_UART0_RX); + // UART0初始化 + uart_init(UART0, uart0_putc); while (1) { // loopback