rtl:perips:spi: fix ss delay ctrl by sw
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/4/head
parent
1e510dab9d
commit
274b19363b
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@ -25,7 +25,7 @@ module spi_master (
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input logic [1:0] cp_mode_i, // [1]表示CPOL, [0]表示CPHA
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input logic [2:0] div_ratio_i, // 分频比
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input logic msb_first_i, // 1: MSB, 0: LSB
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input logic [3:0] ss_delay_cnt_i, // SS信号延时时钟个数
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input logic [3:0] ss_delay_cnt_i, // SS信号延时时钟个数, 当ss_sw_ctrl_i=0时才有效
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input logic ss_sw_ctrl_i, // 软件控制SS信号
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input logic ss_level_i, // SS输出电平,仅当ss_sw_ctrl_i=1时有效
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output logic [7:0] data_o, // 接收到的数据
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@ -89,7 +89,12 @@ module spi_master (
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ready_d = 1'b1;
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if (start_i) begin
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out_data_d = data_i;
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state_d = S_SS_ACTIVE;
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if (ss_sw_ctrl_i) begin
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state_d = S_TRANSMIT;
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start_d = 1'b1;
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end else begin
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state_d = S_SS_ACTIVE;
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end
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ss_delay_cnt_d = '0;
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ready_d = 1'b0;
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end
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@ -111,7 +116,11 @@ module spi_master (
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start_d = 1'b1;
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// 没有数据要传输
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end else if (data_valid && (!start_i)) begin
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state_d = S_SS_INACTIVE;
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if (ss_sw_ctrl_i) begin
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state_d = S_IDLE;
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end else begin
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state_d = S_SS_INACTIVE;
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end
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ss_delay_cnt_d = '0;
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end
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end
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