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add mepc reg 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-18 11:22:20 +08:00
parent 96f8d6e5a0
commit 2638240d0b
2 changed files with 18 additions and 2 deletions
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14
rtl/core/csr_reg.v
View File

@ -41,6 +41,7 @@ module csr_reg(
reg[`DoubleRegBus] cycle; reg[`DoubleRegBus] cycle;
reg[`RegBus] mtvec; reg[`RegBus] mtvec;
reg[`RegBus] mcause; reg[`RegBus] mcause;
reg[`RegBus] mepc;
// cycle counter // cycle counter
@ -57,6 +58,7 @@ module csr_reg(
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
mtvec <= `ZeroWord; mtvec <= `ZeroWord;
mcause <= `ZeroWord; mcause <= `ZeroWord;
mepc <= `ZeroWord;
end else begin end else begin
if (we_i == `WriteEnable) begin if (we_i == `WriteEnable) begin
case (waddr_i[11:0]) case (waddr_i[11:0])
@ -66,6 +68,9 @@ module csr_reg(
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
mcause <= data_i; mcause <= data_i;
end end
`CSR_MEPC: begin
mepc <= data_i;
end
default: begin default: begin
end end
@ -78,6 +83,9 @@ module csr_reg(
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
mcause <= clint_data_i; mcause <= clint_data_i;
end end
`CSR_MEPC: begin
mepc <= clint_data_i;
end
default: begin default: begin
end end
@ -104,6 +112,9 @@ module csr_reg(
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
data_o <= mcause; data_o <= mcause;
end end
`CSR_MEPC: begin
data_o <= mepc;
end
default: begin default: begin
data_o <= `ZeroWord; data_o <= `ZeroWord;
end end
@ -129,6 +140,9 @@ module csr_reg(
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
clint_data_o <= mcause; clint_data_o <= mcause;
end end
`CSR_MEPC: begin
clint_data_o <= mepc;
end
default: begin default: begin
clint_data_o <= `ZeroWord; clint_data_o <= `ZeroWord;
end end

6
rtl/core/defines.v
View File

@ -14,11 +14,12 @@
limitations under the License. limitations under the License.
*/ */
`define CpuResetAddr 32'h00000000 `define CpuResetAddr 32'h0
`define RstEnable 1'b0 `define RstEnable 1'b0
`define RstDisable 1'b1 `define RstDisable 1'b1
`define ZeroWord 32'h00000000 `define ZeroWord 32'h0
`define ZeroReg 5'h0
`define WriteEnable 1'b1 `define WriteEnable 1'b1
`define WriteDisable 1'b0 `define WriteDisable 1'b0
`define ReadEnable 1'b1 `define ReadEnable 1'b1
@ -137,6 +138,7 @@
`define CSR_CYCLEH 12'hc80 `define CSR_CYCLEH 12'hc80
`define CSR_MTVEC 12'h305 `define CSR_MTVEC 12'h305
`define CSR_MCAUSE 12'h342 `define CSR_MCAUSE 12'h342
`define CSR_MEPC 12'h341
`define RomNum 2048 // rom depth(how many words) `define RomNum 2048 // rom depth(how many words)