From 2638240d0b0474074e8e1fab4eb9c40c45bcf4b8 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Sat, 18 Apr 2020 11:22:20 +0800 Subject: [PATCH] add mepc reg Signed-off-by: liangkangnan --- rtl/core/csr_reg.v | 14 ++++++++++++++ rtl/core/defines.v | 6 ++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/rtl/core/csr_reg.v b/rtl/core/csr_reg.v index feac6cb..9943db0 100644 --- a/rtl/core/csr_reg.v +++ b/rtl/core/csr_reg.v @@ -41,6 +41,7 @@ module csr_reg( reg[`DoubleRegBus] cycle; reg[`RegBus] mtvec; reg[`RegBus] mcause; + reg[`RegBus] mepc; // cycle counter @@ -57,6 +58,7 @@ module csr_reg( if (rst == `RstEnable) begin mtvec <= `ZeroWord; mcause <= `ZeroWord; + mepc <= `ZeroWord; end else begin if (we_i == `WriteEnable) begin case (waddr_i[11:0]) @@ -66,6 +68,9 @@ module csr_reg( `CSR_MCAUSE: begin mcause <= data_i; end + `CSR_MEPC: begin + mepc <= data_i; + end default: begin end @@ -78,6 +83,9 @@ module csr_reg( `CSR_MCAUSE: begin mcause <= clint_data_i; end + `CSR_MEPC: begin + mepc <= clint_data_i; + end default: begin end @@ -104,6 +112,9 @@ module csr_reg( `CSR_MCAUSE: begin data_o <= mcause; end + `CSR_MEPC: begin + data_o <= mepc; + end default: begin data_o <= `ZeroWord; end @@ -129,6 +140,9 @@ module csr_reg( `CSR_MCAUSE: begin clint_data_o <= mcause; end + `CSR_MEPC: begin + clint_data_o <= mepc; + end default: begin clint_data_o <= `ZeroWord; end diff --git a/rtl/core/defines.v b/rtl/core/defines.v index 97958c7..71b30ce 100644 --- a/rtl/core/defines.v +++ b/rtl/core/defines.v @@ -14,11 +14,12 @@ limitations under the License. */ -`define CpuResetAddr 32'h00000000 +`define CpuResetAddr 32'h0 `define RstEnable 1'b0 `define RstDisable 1'b1 -`define ZeroWord 32'h00000000 +`define ZeroWord 32'h0 +`define ZeroReg 5'h0 `define WriteEnable 1'b1 `define WriteDisable 1'b0 `define ReadEnable 1'b1 @@ -137,6 +138,7 @@ `define CSR_CYCLEH 12'hc80 `define CSR_MTVEC 12'h305 `define CSR_MCAUSE 12'h342 +`define CSR_MEPC 12'h341 `define RomNum 2048 // rom depth(how many words)