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temp commit 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-05-28 15:10:37 +08:00
parent cd9ac0adae
commit 247a5b6354
1 changed files with 6 additions and 6 deletions
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12
rtl/debug/jtag_dtm.sv
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@ -75,22 +75,22 @@ module jtag_dtm #(
wire[DTM_RESP_BITS-1:0] busy_response;
wire dtm_busy;
wire[DMI_OP_BITS-1:0] op;
wire[1:0] dtm_state;
wire[DMI_ADDR_BITS-1:0] addr_bits = DMI_ADDR_BITS[6:0];
wire[1:0] dmistat;
wire[DMI_ADDR_BITS-1:0] abits = DMI_ADDR_BITS[6:0];
assign idcode_o = {IDCODE_VERSION, IDCODE_PART_NUMBER, IDCODE_MANUFLD, 1'h1};
assign dtmcs_o = {14'b0,
1'b0, // dmihardreset
1'b0, // dmireset
1'b0,
3'h5, // idle
dtm_state, // dmistat
addr_bits, // abits
3'h1, // idle
dmistat, // dmistat
abits, // abits
DTM_VERSION}; // version
assign busy_response = {{(DMI_ADDR_BITS + DMI_DATA_BITS){1'b0}}, {(DMI_OP_BITS){1'b1}}}; // op = 2'b11
assign dtm_state = is_busy ? 2'b01 : 2'b00;
assign dmistat = is_busy ? 2'b11 : 2'b00;
assign op = tap_data_i[DMI_OP_BITS-1:0];