From 247a5b635465dee9375d122f08e580dcd30f65ba Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Fri, 28 May 2021 15:10:37 +0800 Subject: [PATCH] temp commit Signed-off-by: liangkangnan --- rtl/debug/jtag_dtm.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/rtl/debug/jtag_dtm.sv b/rtl/debug/jtag_dtm.sv index 5f071fd..327acb9 100644 --- a/rtl/debug/jtag_dtm.sv +++ b/rtl/debug/jtag_dtm.sv @@ -75,22 +75,22 @@ module jtag_dtm #( wire[DTM_RESP_BITS-1:0] busy_response; wire dtm_busy; wire[DMI_OP_BITS-1:0] op; - wire[1:0] dtm_state; - wire[DMI_ADDR_BITS-1:0] addr_bits = DMI_ADDR_BITS[6:0]; + wire[1:0] dmistat; + wire[DMI_ADDR_BITS-1:0] abits = DMI_ADDR_BITS[6:0]; assign idcode_o = {IDCODE_VERSION, IDCODE_PART_NUMBER, IDCODE_MANUFLD, 1'h1}; assign dtmcs_o = {14'b0, 1'b0, // dmihardreset 1'b0, // dmireset 1'b0, - 3'h5, // idle - dtm_state, // dmistat - addr_bits, // abits + 3'h1, // idle + dmistat, // dmistat + abits, // abits DTM_VERSION}; // version assign busy_response = {{(DMI_ADDR_BITS + DMI_DATA_BITS){1'b0}}, {(DMI_OP_BITS){1'b1}}}; // op = 2'b11 - assign dtm_state = is_busy ? 2'b01 : 2'b00; + assign dmistat = is_busy ? 2'b11 : 2'b00; assign op = tap_data_i[DMI_OP_BITS-1:0];