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use oneshot mode 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-18 11:37:22 +08:00
parent ce225394df
commit 18577d9b61
1 changed files with 38 additions and 45 deletions
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83
rtl/perips/timer.v
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@ -29,7 +29,7 @@ module timer(
input wire req_i, input wire req_i,
output reg[31:0] data_o, output reg[31:0] data_o,
output wire int_sig_o, output reg int_sig_o,
output reg ack_o output reg ack_o
); );
@ -53,46 +53,6 @@ module timer(
reg[31:0] timer_value; reg[31:0] timer_value;
assign int_sig_o = (timer_ctrl[2:1] == 3'h3)? `INT_ASSERT: `INT_DEASSERT;
// write ctrl reg
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_ctrl <= `ZeroWord;
end else begin
if (we_i == `WriteEnable) begin
if (addr_i[3:0] == REG_CTRL) begin
if (data_i[2] == 1'b0) begin
timer_ctrl <= {data_i[31:3], timer_ctrl[2], data_i[1:0]};
// write 1 to clear pending
end else begin
timer_ctrl <= {data_i[31:3], 1'b0, data_i[1:0]};
end
end
end else begin
// generate int pending
if (timer_count >= timer_value && timer_value > 32'h0) begin
timer_ctrl[2] <= 1'b1;
timer_ctrl[0] <= 1'b0;
end
end
end
end
// write value reg
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_value <= `ZeroWord;
end else begin
if (we_i == `WriteEnable) begin
if (addr_i[3:0] == REG_VALUE) begin
timer_value <= data_i;
end
end
end
end
// counter // counter
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
@ -100,16 +60,49 @@ module timer(
end else begin end else begin
if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin
timer_count <= timer_count + 1'b1; timer_count <= timer_count + 1'b1;
//if (timer_count == timer_value) begin
// timer_count <= `ZeroWord;
//end
end else begin end else begin
timer_count <= `ZeroWord; timer_count <= `ZeroWord;
end end
end end
end end
// read timer regs // int signal
always @ (posedge clk) begin
if (rst == `RstEnable) begin
int_sig_o <= `INT_DEASSERT;
end else begin
if (timer_count >= timer_value && timer_value > 32'h0) begin
int_sig_o <= `INT_ASSERT;
end else if (we_i == `WriteEnable && addr_i[3:0] == REG_CTRL && timer_ctrl[2] == 1'b1) begin
int_sig_o <= `INT_DEASSERT;
end
end
end
// write regs
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_ctrl <= `ZeroWord;
timer_value <= `ZeroWord;
end else begin
if (we_i == `WriteEnable) begin
case (addr_i[3:0])
REG_CTRL: begin
timer_ctrl <= data_i;
end
REG_VALUE: begin
timer_value <= data_i;
end
endcase
end else begin
if (timer_count >= timer_value && timer_value > 32'h0) begin
timer_ctrl[0] <= 1'b0;
end
end
end
end
// read regs
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o <= `ZeroWord; data_o <= `ZeroWord;