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sim: add uart_debug.v 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-07-04 17:21:50 +08:00
parent f7b3dc8327
commit 15f10fbf35
3 changed files with 3 additions and 2 deletions
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1
sim/compliance_test/compliance_test.py
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@ -41,6 +41,7 @@ iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v') iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v')
# ..\rtl\soc # ..\rtl\soc
iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v') iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')

2
sim/sim_default_nowave.bat
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@ -1,2 +1,2 @@
iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp vvp out.vvp

2
sim/sim_new_nowave.bat
View File

@ -1,3 +1,3 @@
..\tools\BinToMem_CLI.exe %1 %2 ..\tools\BinToMem_CLI.exe %1 %2
iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp vvp out.vvp