sdk: rename to timer0_irq_handler

Signed-off-by: liangkangnan <liangkangnan@163.com>

sdk/bsp/trap_entry.S

@@ -16,10 +16,11 @@ vector_table:
     .word store_misaligned_handler
     .word handle_exception_unknown
     .word handle_exception_unknown
-    .word timer_irq_handler
+    .word timer0_irq_handler
     .word uart0_irq_handler
     .word gpio0_irq_handler
     .word gpio1_irq_handler
+    .word i2c0_irq_handler
     /* add your ISR here */
 
 .weak illegal_instruction_handler
@@ -29,10 +30,11 @@ vector_table:
 .weak load_misaligned_handler
 .weak store_misaligned_handler
 .weak handle_exception_unknown
-.weak timer_irq_handler
+.weak timer0_irq_handler
 .weak uart0_irq_handler
 .weak gpio0_irq_handler
 .weak gpio1_irq_handler
+.weak i2c0_irq_handler
 
 handle_exception_unknown:
     j handle_exception_unknown
@@ -61,8 +63,8 @@ load_misaligned_handler:
 store_misaligned_handler:
     j store_misaligned_handler
 
-timer_irq_handler:
-    j timer_irq_handler
+timer0_irq_handler:
+    j timer0_irq_handler
 
 uart0_irq_handler:
     j uart0_irq_handler
@@ -73,6 +75,9 @@ gpio0_irq_handler:
 gpio1_irq_handler:
     j gpio1_irq_handler
 
+i2c0_irq_handler:
+    j i2c0_irq_handler
+
 /* 异常和中断总入口 */
 trap_entry:
     addi sp, sp, -32*17

sdk/examples/freertos/Source/portable/RISC-V/portASM.S

@@ -80,7 +80,7 @@ specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
 at the top of this file. */
 #define portCONTEXT_SIZE ( 28 * portWORD_SIZE )
 
-.global timer_irq_handler
+.global timer0_irq_handler
 .global ecall_handler
 .global xPortStartFirstTask
 .global freertos_risc_v_trap_handler
@@ -172,7 +172,7 @@ freertos_risc_v_trap_handler:
 
 .align 3
 .func
-timer_irq_handler:
+timer0_irq_handler:
     addi s1, ra, 0                      /* save return address */
 
     load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */

sdk/examples/timer/main.c

@@ -55,7 +55,7 @@ int main()
 #endif
 }
 
-void timer_irq_handler()
+void timer0_irq_handler()
 {
     count++;