rtl: fix combilation loop

Signed-off-by: liangkangnan <liangkangnan@163.com>

fpga/constrs/tinyriscv.xdc

@@ -1,53 +0,0 @@
-# 时钟约束50MHz
-set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {clk}]; 
-create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports {clk}];
-
-# 时钟引脚
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-set_property PACKAGE_PIN N14 [get_ports clk]
-
-# 复位引脚
-set_property IOSTANDARD LVCMOS33 [get_ports rst_ext_i]
-set_property PACKAGE_PIN L13 [get_ports rst_ext_i]
-
-# CPU停住指示引脚
-set_property IOSTANDARD LVCMOS33 [get_ports halted_ind]
-set_property PACKAGE_PIN P15 [get_ports halted_ind]
-
-# 串口发送引脚
-set_property IOSTANDARD LVCMOS33 [get_ports uart_tx_pin]
-set_property PACKAGE_PIN M6 [get_ports uart_tx_pin]
-
-# 串口接收引脚
-set_property IOSTANDARD LVCMOS33 [get_ports uart_rx_pin]
-set_property PACKAGE_PIN N6 [get_ports uart_rx_pin]
-
-# GPIO0引脚
-set_property IOSTANDARD LVCMOS33 [get_ports {gpio[0]}]
-set_property PACKAGE_PIN P16 [get_ports {gpio[0]}]
-
-# GPIO1引脚
-set_property IOSTANDARD LVCMOS33 [get_ports {gpio[1]}]
-set_property PACKAGE_PIN T15 [get_ports {gpio[1]}]
-
-# JTAG TCK引脚
-set_property IOSTANDARD LVCMOS33 [get_ports jtag_TCK]
-set_property PACKAGE_PIN N11 [get_ports jtag_TCK]
-
-#create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK}];
-
-# JTAG TMS引脚
-set_property IOSTANDARD LVCMOS33 [get_ports jtag_TMS]
-set_property PACKAGE_PIN N3 [get_ports jtag_TMS]
-
-# JTAG TDI引脚
-set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDI]
-set_property PACKAGE_PIN N2 [get_ports jtag_TDI]
-
-# JTAG TDO引脚
-set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDO]
-set_property PACKAGE_PIN M1 [get_ports jtag_TDO]
-
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]  
-set_property CONFIG_MODE SPIx4 [current_design] 
-set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

fpga/xilinx/constrs/tinyriscv.xdc

@@ -0,0 +1,53 @@
+# 时钟约束50MHz
+set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {clk}]; 
+create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports {clk}];
+
+# 时钟引脚
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property PACKAGE_PIN N14 [get_ports clk]
+
+# 复位引脚
+set_property IOSTANDARD LVCMOS33 [get_ports rst_ext_ni]
+set_property PACKAGE_PIN L13 [get_ports rst_ext_ni]
+
+# CPU停住指示引脚
+set_property IOSTANDARD LVCMOS33 [get_ports halted_ind_pin]
+set_property PACKAGE_PIN P15 [get_ports halted_ind_pin]
+
+# 串口发送引脚
+set_property IOSTANDARD LVCMOS33 [get_ports uart_tx_pin]
+set_property PACKAGE_PIN M6 [get_ports uart_tx_pin]
+
+# 串口接收引脚
+set_property IOSTANDARD LVCMOS33 [get_ports uart_rx_pin]
+set_property PACKAGE_PIN N6 [get_ports uart_rx_pin]
+
+# GPIO0引脚
+set_property IOSTANDARD LVCMOS33 [get_ports {gpio_pins[0]}]
+set_property PACKAGE_PIN P16 [get_ports {gpio_pins[0]}]
+
+# GPIO1引脚
+set_property IOSTANDARD LVCMOS33 [get_ports {gpio_pins[1]}]
+set_property PACKAGE_PIN T15 [get_ports {gpio_pins[1]}]
+
+# JTAG TCK引脚
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_TCK_pin]
+set_property PACKAGE_PIN N11 [get_ports jtag_TCK_pin]
+
+#create_clock -name jtag_clk_pin -period 300 [get_ports {jtag_TCK_pin}];
+
+# JTAG TMS引脚
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_TMS_pin]
+set_property PACKAGE_PIN N3 [get_ports jtag_TMS_pin]
+
+# JTAG TDI引脚
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDI_pin]
+set_property PACKAGE_PIN N2 [get_ports jtag_TDI_pin]
+
+# JTAG TDO引脚
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_TDO_pin]
+set_property PACKAGE_PIN M1 [get_ports jtag_TDO_pin]
+
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]  
+set_property CONFIG_MODE SPIx4 [current_design] 
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

rtl/core/tinyriscv_core.sv

@@ -310,7 +310,7 @@ module tinyriscv_core #(
     exception u_exception(
         .clk(clk),
         .rst_n(rst_n),
-        .inst_valid_i(ex_inst_valid_o),
+        .inst_valid_i(ie_inst_valid_o),
         .inst_ecall_i(ex_inst_ecall_o),
         .inst_ebreak_i(ex_inst_ebreak_o),
         .inst_mret_i(ex_inst_mret_o),

rtl/top/tinyriscv_soc_top.sv

@@ -195,11 +195,19 @@ module tinyriscv_soc_top(
         .debug_req_o        (debug_req),
         .ndmreset_o         (ndmreset),
         .halted_o           (core_halted),
+`ifdef VERILATOR
         .jtag_tck_i         (sim_jtag_tck),
         .jtag_tdi_i         (sim_jtag_tdi),
         .jtag_tms_i         (sim_jtag_tms),
         .jtag_trst_ni       (sim_jtag_trstn),
         .jtag_tdo_o         (sim_jtag_tdo),
+`else
+        .jtag_tck_i         (jtag_TCK_pin),
+        .jtag_tdi_i         (jtag_TDI_pin),
+        .jtag_tms_i         (jtag_TMS_pin),
+        .jtag_trst_ni       (rst_ext_ni),
+        .jtag_tdo_o         (jtag_TDO_pin),
+`endif
         .master_req_o       (master_req[JtagHost]),
         .master_gnt_i       (master_gnt[JtagHost]),
         .master_rvalid_i    (master_rvalid[JtagHost]),

tools/openocd/tinyriscv_cmsisdap.cfg

@@ -15,8 +15,15 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
-riscv set_reset_timeout_sec 1
+riscv set_reset_timeout_sec 10
+riscv set_command_timeout_sec 10
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba on
+riscv set_enable_virt2phys off
 
 init
 
 halt
+
+echo "Ready for Remote Connections"